blob: ffaf517a8bbe05e354cdb3aa7eca04c2dcb3d109 [file] [log] [blame]
Michael Walle4ceb5c62020-10-15 23:08:57 +02001// SPDX-License-Identifier: GPL-2.0+
2
3#include <common.h>
4#include <asm/io.h>
5#include <asm/spl.h>
Michael Walle805b2422021-01-08 00:08:59 +01006#include <asm/arch-fsl-layerscape/fsl_serdes.h>
7#include <asm/arch-fsl-layerscape/soc.h>
Michael Walle67b5dab2022-08-23 11:30:15 +02008#include <spi_flash.h>
9
10#include "sl28.h"
Michael Walle4ceb5c62020-10-15 23:08:57 +020011
12#define DCFG_RCWSR25 0x160
13#define GPINFO_HW_VARIANT_MASK 0xff
14
Michael Walle805b2422021-01-08 00:08:59 +010015#define SERDES_LNDGCR0 0x1ea08c0
16#define LNDGCR0_PROTS_MASK GENMASK(11, 7)
17#define LNDGCR0_PROTS_SATA (0x2 << 7)
18#define SERDES_LNDGCR1 0x1ea08c4
19#define LNDGCR1_RDAT_INV BIT(31)
20
21/*
22 * On this board the SMARC PCIe lane D might be switched to SATA mode. This
23 * makes sense if this lane is connected to a Mini PCI slot and a mSATA card
24 * is plugged in. In this case, the RX pair is swapped and we need to invert
25 * the received data.
26 */
27static void fixup_sata_rx_polarity(void)
28{
29 u32 prot = in_le32(SERDES_LNDGCR0) & LNDGCR0_PROTS_MASK;
30 u32 tmp;
31
32 if (prot == LNDGCR0_PROTS_SATA) {
33 tmp = in_le32(SERDES_LNDGCR1);
34 tmp |= LNDGCR1_RDAT_INV;
35 out_le32(SERDES_LNDGCR1, tmp);
36 }
37}
38
Michael Walle4ceb5c62020-10-15 23:08:57 +020039int sl28_variant(void)
40{
41 return in_le32(DCFG_BASE + DCFG_RCWSR25) & GPINFO_HW_VARIANT_MASK;
42}
43
44int board_fit_config_name_match(const char *name)
45{
46 int variant = sl28_variant();
47
48 switch (variant) {
Michael Walle4029d352021-01-08 00:08:57 +010049 case 1:
50 return strcmp(name, "fsl-ls1028a-kontron-sl28-var1");
Michael Walleb4630102021-01-08 00:08:58 +010051 case 2:
52 return strcmp(name, "fsl-ls1028a-kontron-sl28-var2");
Michael Walle4ceb5c62020-10-15 23:08:57 +020053 case 3:
54 return strcmp(name, "fsl-ls1028a-kontron-sl28-var3");
55 case 4:
56 return strcmp(name, "fsl-ls1028a-kontron-sl28-var4");
57 default:
58 return strcmp(name, "fsl-ls1028a-kontron-sl28");
59 }
60}
61
62void board_boot_order(u32 *spl_boot_list)
63{
Michael Walle67b5dab2022-08-23 11:30:15 +020064 enum boot_source src = sl28_boot_source();
65
66 switch (src) {
67 case BOOT_SOURCE_SDHC:
68 spl_boot_list[0] = BOOT_DEVICE_MMC2;
69 break;
70 case BOOT_SOURCE_SPI:
71 case BOOT_SOURCE_I2C:
72 spl_boot_list[0] = BOOT_DEVICE_SPI;
73 break;
74 case BOOT_SOURCE_MMC:
75 spl_boot_list[0] = BOOT_DEVICE_MMC1;
76 break;
77 default:
78 panic("unexpected bootsource (%d)\n", src);
79 break;
80 }
81}
82
83unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash)
84{
85 enum boot_source src = sl28_boot_source();
86
87 switch (src) {
88 case BOOT_SOURCE_SPI:
89 return 0x000000;
90 case BOOT_SOURCE_I2C:
91 return 0x230000;
92 default:
93 panic("unexpected bootsource (%d)\n", src);
94 break;
95 }
96}
97
Michael Walle9f461172022-08-23 11:30:16 +020098const char *spl_board_loader_name(u32 boot_device)
99{
100 enum boot_source src = sl28_boot_source();
101
102 switch (src) {
103 case BOOT_SOURCE_SDHC:
104 return "SD card (Test mode)";
105 case BOOT_SOURCE_SPI:
106 return "Failsafe SPI flash";
107 case BOOT_SOURCE_I2C:
108 return "SPI flash";
109 case BOOT_SOURCE_MMC:
110 return "eMMC";
111 default:
112 return "(unknown)";
113 }
Michael Walle4ceb5c62020-10-15 23:08:57 +0200114}
Michael Walle805b2422021-01-08 00:08:59 +0100115
116int board_early_init_f(void)
117{
118 fixup_sata_rx_polarity();
119 fsl_lsch3_early_init_f();
120
121 return 0;
122}