blob: ac7e469469aa3cee81393f18b9c6f0b90f24a3d3 [file] [log] [blame]
Vignesh Raghavendra7e91f6c2019-10-01 17:26:33 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * Cadence USBSS DRD Driver - gadget side.
4 *
5 * Copyright (C) 2018-2019 Cadence Design Systems.
6 * Copyright (C) 2017-2018 NXP
7 *
8 * Authors: Pawel Jez <pjez@cadence.com>,
9 * Pawel Laszczak <pawell@cadence.com>
10 * Peter Chen <peter.chen@nxp.com>
11 */
12
13/*
14 * Work around 1:
15 * At some situations, the controller may get stale data address in TRB
16 * at below sequences:
17 * 1. Controller read TRB includes data address
18 * 2. Software updates TRBs includes data address and Cycle bit
19 * 3. Controller read TRB which includes Cycle bit
20 * 4. DMA run with stale data address
21 *
22 * To fix this problem, driver needs to make the first TRB in TD as invalid.
23 * After preparing all TRBs driver needs to check the position of DMA and
24 * if the DMA point to the first just added TRB and doorbell is 1,
25 * then driver must defer making this TRB as valid. This TRB will be make
26 * as valid during adding next TRB only if DMA is stopped or at TRBERR
27 * interrupt.
28 *
29 * Issue has been fixed in DEV_VER_V3 version of controller.
30 *
31 * Work around 2:
32 * Controller for OUT endpoints has shared on-chip buffers for all incoming
33 * packets, including ep0out. It's FIFO buffer, so packets must be handle by DMA
34 * in correct order. If the first packet in the buffer will not be handled,
35 * then the following packets directed for other endpoints and functions
36 * will be blocked.
37 * Additionally the packets directed to one endpoint can block entire on-chip
38 * buffers. In this case transfer to other endpoints also will blocked.
39 *
40 * To resolve this issue after raising the descriptor missing interrupt
41 * driver prepares internal usb_request object and use it to arm DMA transfer.
42 *
43 * The problematic situation was observed in case when endpoint has been enabled
44 * but no usb_request were queued. Driver try detects such endpoints and will
45 * use this workaround only for these endpoint.
46 *
47 * Driver use limited number of buffer. This number can be set by macro
48 * CDNS3_WA2_NUM_BUFFERS.
49 *
50 * Such blocking situation was observed on ACM gadget. For this function
51 * host send OUT data packet but ACM function is not prepared for this packet.
52 * It's cause that buffer placed in on chip memory block transfer to other
53 * endpoints.
54 *
55 * Issue has been fixed in DEV_VER_V2 version of controller.
56 *
57 */
58
59#include <dm.h>
Simon Glass336d4612020-02-03 07:36:16 -070060#include <dm/device_compat.h>
Simon Glass61b29b82020-02-03 07:36:15 -070061#include <dm/devres.h>
Simon Glasscd93d622020-05-10 11:40:13 -060062#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060063#include <linux/delay.h>
Simon Glass61b29b82020-02-03 07:36:15 -070064#include <linux/err.h>
Simon Glass1e94b462023-09-14 18:21:46 -060065#include <linux/printk.h>
Vignesh Raghavendra7e91f6c2019-10-01 17:26:33 +053066#include <linux/usb/gadget.h>
67#include <linux/compat.h>
68#include <linux/iopoll.h>
Masahiro Yamada9d86b892020-02-14 16:40:19 +090069#include <linux/dma-mapping.h>
Vignesh Raghavendra7e91f6c2019-10-01 17:26:33 +053070#include <linux/bitmap.h>
71#include <linux/bug.h>
72
73#include "core.h"
74#include "gadget-export.h"
75#include "gadget.h"
76#include "trace.h"
77#include "drd.h"
78
79#define readl_poll_timeout_atomic readl_poll_timeout
80#define usleep_range(a, b) udelay((b))
81
82static int __cdns3_gadget_ep_queue(struct usb_ep *ep,
83 struct usb_request *request,
84 gfp_t gfp_flags);
85
Ravi Gunasekaran15cba562023-07-19 14:29:08 +053086static void cdns3_gadget_udc_set_speed(struct usb_gadget *gadget,
87 enum usb_device_speed speed);
88
Vignesh Raghavendra7e91f6c2019-10-01 17:26:33 +053089/**
90 * cdns3_set_register_bit - set bit in given register.
91 * @ptr: address of device controller register to be read and changed
92 * @mask: bits requested to set
93 */
94void cdns3_set_register_bit(void __iomem *ptr, u32 mask)
95{
96 mask = readl(ptr) | mask;
97 writel(mask, ptr);
98}
99
100/**
101 * cdns3_ep_addr_to_index - Macro converts endpoint address to
102 * index of endpoint object in cdns3_device.eps[] container
103 * @ep_addr: endpoint address for which endpoint object is required
104 *
105 */
106u8 cdns3_ep_addr_to_index(u8 ep_addr)
107{
108 return (((ep_addr & 0x7F)) + ((ep_addr & USB_DIR_IN) ? 16 : 0));
109}
110
111static int cdns3_get_dma_pos(struct cdns3_device *priv_dev,
112 struct cdns3_endpoint *priv_ep)
113{
114 int dma_index;
115
116 dma_index = readl(&priv_dev->regs->ep_traddr) - priv_ep->trb_pool_dma;
117
118 return dma_index / TRB_SIZE;
119}
120
121/**
122 * cdns3_next_request - returns next request from list
123 * @list: list containing requests
124 *
125 * Returns request or NULL if no requests in list
126 */
127struct usb_request *cdns3_next_request(struct list_head *list)
128{
129 return list_first_entry_or_null(list, struct usb_request, list);
130}
131
132/**
133 * cdns3_next_align_buf - returns next buffer from list
134 * @list: list containing buffers
135 *
136 * Returns buffer or NULL if no buffers in list
137 */
138struct cdns3_aligned_buf *cdns3_next_align_buf(struct list_head *list)
139{
140 return list_first_entry_or_null(list, struct cdns3_aligned_buf, list);
141}
142
143/**
144 * cdns3_next_priv_request - returns next request from list
145 * @list: list containing requests
146 *
147 * Returns request or NULL if no requests in list
148 */
149struct cdns3_request *cdns3_next_priv_request(struct list_head *list)
150{
151 return list_first_entry_or_null(list, struct cdns3_request, list);
152}
153
154/**
155 * select_ep - selects endpoint
156 * @priv_dev: extended gadget object
157 * @ep: endpoint address
158 */
159void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep)
160{
161 if (priv_dev->selected_ep == ep)
162 return;
163
164 priv_dev->selected_ep = ep;
165 writel(ep, &priv_dev->regs->ep_sel);
166}
167
168dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep,
169 struct cdns3_trb *trb)
170{
171 u32 offset = (char *)trb - (char *)priv_ep->trb_pool;
172
173 return priv_ep->trb_pool_dma + offset;
174}
175
176int cdns3_ring_size(struct cdns3_endpoint *priv_ep)
177{
178 switch (priv_ep->type) {
179 case USB_ENDPOINT_XFER_ISOC:
180 return TRB_ISO_RING_SIZE;
181 case USB_ENDPOINT_XFER_CONTROL:
182 return TRB_CTRL_RING_SIZE;
183 default:
184 return TRB_RING_SIZE;
185 }
186}
187
188/**
189 * cdns3_allocate_trb_pool - Allocates TRB's pool for selected endpoint
190 * @priv_ep: endpoint object
191 *
192 * Function will return 0 on success or -ENOMEM on allocation error
193 */
194int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep)
195{
196 int ring_size = cdns3_ring_size(priv_ep);
197 struct cdns3_trb *link_trb;
198
199 if (!priv_ep->trb_pool) {
200 priv_ep->trb_pool =
201 dma_alloc_coherent(ring_size,
202 (unsigned long *)&priv_ep->trb_pool_dma);
203 if (!priv_ep->trb_pool)
204 return -ENOMEM;
205 } else {
206 memset(priv_ep->trb_pool, 0, ring_size);
207 }
208
209 if (!priv_ep->num)
210 return 0;
211
212 priv_ep->num_trbs = ring_size / TRB_SIZE;
213 /* Initialize the last TRB as Link TRB. */
214 link_trb = (priv_ep->trb_pool + (priv_ep->num_trbs - 1));
215 link_trb->buffer = TRB_BUFFER(priv_ep->trb_pool_dma);
216 link_trb->control = TRB_CYCLE | TRB_TYPE(TRB_LINK) | TRB_TOGGLE;
217
218 return 0;
219}
220
221static void cdns3_free_trb_pool(struct cdns3_endpoint *priv_ep)
222{
223 if (priv_ep->trb_pool) {
224 dma_free_coherent(priv_ep->trb_pool);
225 priv_ep->trb_pool = NULL;
226 }
227}
228
229/**
230 * cdns3_ep_stall_flush - Stalls and flushes selected endpoint
231 * @priv_ep: endpoint object
232 *
233 * Endpoint must be selected before call to this function
234 */
235static void cdns3_ep_stall_flush(struct cdns3_endpoint *priv_ep)
236{
237 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
238 int val;
239
240 trace_cdns3_halt(priv_ep, 1, 1);
241
242 writel(EP_CMD_DFLUSH | EP_CMD_ERDY | EP_CMD_SSTALL,
243 &priv_dev->regs->ep_cmd);
244
245 /* wait for DFLUSH cleared */
246 readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
247 !(val & EP_CMD_DFLUSH), 1000);
248 priv_ep->flags |= EP_STALLED;
249 priv_ep->flags &= ~EP_STALL_PENDING;
250}
251
252/**
253 * cdns3_hw_reset_eps_config - reset endpoints configuration kept by controller.
254 * @priv_dev: extended gadget object
255 */
256void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev)
257{
258 writel(USB_CONF_CFGRST, &priv_dev->regs->usb_conf);
259
260 cdns3_allow_enable_l1(priv_dev, 0);
261 priv_dev->hw_configured_flag = 0;
262 priv_dev->onchip_used_size = 0;
263 priv_dev->out_mem_is_allocated = 0;
264 priv_dev->wait_for_setup = 0;
265}
266
267/**
268 * cdns3_ep_inc_trb - increment a trb index.
269 * @index: Pointer to the TRB index to increment.
270 * @cs: Cycle state
271 * @trb_in_seg: number of TRBs in segment
272 *
273 * The index should never point to the link TRB. After incrementing,
274 * if it is point to the link TRB, wrap around to the beginning and revert
275 * cycle state bit The
276 * link TRB is always at the last TRB entry.
277 */
278static void cdns3_ep_inc_trb(int *index, u8 *cs, int trb_in_seg)
279{
280 (*index)++;
281 if (*index == (trb_in_seg - 1)) {
282 *index = 0;
283 *cs ^= 1;
284 }
285}
286
287/**
288 * cdns3_ep_inc_enq - increment endpoint's enqueue pointer
289 * @priv_ep: The endpoint whose enqueue pointer we're incrementing
290 */
291static void cdns3_ep_inc_enq(struct cdns3_endpoint *priv_ep)
292{
293 priv_ep->free_trbs--;
294 cdns3_ep_inc_trb(&priv_ep->enqueue, &priv_ep->pcs, priv_ep->num_trbs);
295}
296
297/**
298 * cdns3_ep_inc_deq - increment endpoint's dequeue pointer
299 * @priv_ep: The endpoint whose dequeue pointer we're incrementing
300 */
301static void cdns3_ep_inc_deq(struct cdns3_endpoint *priv_ep)
302{
303 priv_ep->free_trbs++;
304 cdns3_ep_inc_trb(&priv_ep->dequeue, &priv_ep->ccs, priv_ep->num_trbs);
305}
306
307void cdns3_move_deq_to_next_trb(struct cdns3_request *priv_req)
308{
309 struct cdns3_endpoint *priv_ep = priv_req->priv_ep;
310 int current_trb = priv_req->start_trb;
311
312 while (current_trb != priv_req->end_trb) {
313 cdns3_ep_inc_deq(priv_ep);
314 current_trb = priv_ep->dequeue;
315 }
316
317 cdns3_ep_inc_deq(priv_ep);
318}
319
320/**
321 * cdns3_allow_enable_l1 - enable/disable permits to transition to L1.
322 * @priv_dev: Extended gadget object
323 * @enable: Enable/disable permit to transition to L1.
324 *
325 * If bit USB_CONF_L1EN is set and device receive Extended Token packet,
326 * then controller answer with ACK handshake.
327 * If bit USB_CONF_L1DS is set and device receive Extended Token packet,
328 * then controller answer with NYET handshake.
329 */
330void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable)
331{
332 if (enable)
333 writel(USB_CONF_L1EN, &priv_dev->regs->usb_conf);
334 else
335 writel(USB_CONF_L1DS, &priv_dev->regs->usb_conf);
336}
337
338enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev)
339{
340 u32 reg;
341
342 reg = readl(&priv_dev->regs->usb_sts);
343
344 if (DEV_SUPERSPEED(reg))
345 return USB_SPEED_SUPER;
346 else if (DEV_HIGHSPEED(reg))
347 return USB_SPEED_HIGH;
348 else if (DEV_FULLSPEED(reg))
349 return USB_SPEED_FULL;
350 else if (DEV_LOWSPEED(reg))
351 return USB_SPEED_LOW;
352 return USB_SPEED_UNKNOWN;
353}
354
355/**
356 * cdns3_start_all_request - add to ring all request not started
357 * @priv_dev: Extended gadget object
358 * @priv_ep: The endpoint for whom request will be started.
359 *
360 * Returns return ENOMEM if transfer ring i not enough TRBs to start
361 * all requests.
362 */
363static int cdns3_start_all_request(struct cdns3_device *priv_dev,
364 struct cdns3_endpoint *priv_ep)
365{
366 struct usb_request *request;
367 int ret = 0;
368
369 while (!list_empty(&priv_ep->deferred_req_list)) {
370 request = cdns3_next_request(&priv_ep->deferred_req_list);
371
372 ret = cdns3_ep_run_transfer(priv_ep, request);
373 if (ret)
374 return ret;
375
376 list_del(&request->list);
377 list_add_tail(&request->list,
378 &priv_ep->pending_req_list);
379 }
380
381 priv_ep->flags &= ~EP_RING_FULL;
382 return ret;
383}
384
385/*
386 * WA2: Set flag for all not ISOC OUT endpoints. If this flag is set
387 * driver try to detect whether endpoint need additional internal
388 * buffer for unblocking on-chip FIFO buffer. This flag will be cleared
389 * if before first DESCMISS interrupt the DMA will be armed.
390 */
391#define cdns3_wa2_enable_detection(priv_dev, ep_priv, reg) do { \
392 if (!priv_ep->dir && priv_ep->type != USB_ENDPOINT_XFER_ISOC) { \
393 priv_ep->flags |= EP_QUIRK_EXTRA_BUF_DET; \
394 (reg) |= EP_STS_EN_DESCMISEN; \
395 } } while (0)
396
397/**
398 * cdns3_wa2_descmiss_copy_data copy data from internal requests to
399 * request queued by class driver.
400 * @priv_ep: extended endpoint object
401 * @request: request object
402 */
403static void cdns3_wa2_descmiss_copy_data(struct cdns3_endpoint *priv_ep,
404 struct usb_request *request)
405{
406 struct usb_request *descmiss_req;
407 struct cdns3_request *descmiss_priv_req;
408
409 while (!list_empty(&priv_ep->wa2_descmiss_req_list)) {
410 int chunk_end;
411 int length;
412
413 descmiss_priv_req =
414 cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list);
415 descmiss_req = &descmiss_priv_req->request;
416
417 /* driver can't touch pending request */
418 if (descmiss_priv_req->flags & REQUEST_PENDING)
419 break;
420
421 chunk_end = descmiss_priv_req->flags & REQUEST_INTERNAL_CH;
422 length = request->actual + descmiss_req->actual;
423
424 request->status = descmiss_req->status;
425
426 if (length <= request->length) {
427 memcpy(&((u8 *)request->buf)[request->actual],
428 descmiss_req->buf,
429 descmiss_req->actual);
430 request->actual = length;
431 } else {
432 /* It should never occur */
433 request->status = -ENOMEM;
434 }
435
436 list_del_init(&descmiss_priv_req->list);
437
438 kfree(descmiss_req->buf);
439 cdns3_gadget_ep_free_request(&priv_ep->endpoint, descmiss_req);
440 --priv_ep->wa2_counter;
441
442 if (!chunk_end)
443 break;
444 }
445}
446
447struct usb_request *cdns3_wa2_gadget_giveback(struct cdns3_device *priv_dev,
448 struct cdns3_endpoint *priv_ep,
449 struct cdns3_request *priv_req)
450{
451 if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN &&
452 priv_req->flags & REQUEST_INTERNAL) {
453 struct usb_request *req;
454
455 req = cdns3_next_request(&priv_ep->deferred_req_list);
456
457 priv_ep->descmis_req = NULL;
458
459 if (!req)
460 return NULL;
461
462 cdns3_wa2_descmiss_copy_data(priv_ep, req);
463 if (!(priv_ep->flags & EP_QUIRK_END_TRANSFER) &&
464 req->length != req->actual) {
465 /* wait for next part of transfer */
466 return NULL;
467 }
468
469 if (req->status == -EINPROGRESS)
470 req->status = 0;
471
472 list_del_init(&req->list);
473 cdns3_start_all_request(priv_dev, priv_ep);
474 return req;
475 }
476
477 return &priv_req->request;
478}
479
480int cdns3_wa2_gadget_ep_queue(struct cdns3_device *priv_dev,
481 struct cdns3_endpoint *priv_ep,
482 struct cdns3_request *priv_req)
483{
484 int deferred = 0;
485
486 /*
487 * If transfer was queued before DESCMISS appear than we
488 * can disable handling of DESCMISS interrupt. Driver assumes that it
489 * can disable special treatment for this endpoint.
490 */
491 if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_DET) {
492 u32 reg;
493
494 cdns3_select_ep(priv_dev, priv_ep->num | priv_ep->dir);
495 priv_ep->flags &= ~EP_QUIRK_EXTRA_BUF_DET;
496 reg = readl(&priv_dev->regs->ep_sts_en);
497 reg &= ~EP_STS_EN_DESCMISEN;
498 trace_cdns3_wa2(priv_ep, "workaround disabled\n");
499 writel(reg, &priv_dev->regs->ep_sts_en);
500 }
501
502 if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN) {
503 u8 pending_empty = list_empty(&priv_ep->pending_req_list);
504 u8 descmiss_empty = list_empty(&priv_ep->wa2_descmiss_req_list);
505
506 /*
507 * DESCMISS transfer has been finished, so data will be
508 * directly copied from internal allocated usb_request
509 * objects.
510 */
511 if (pending_empty && !descmiss_empty &&
512 !(priv_req->flags & REQUEST_INTERNAL)) {
513 cdns3_wa2_descmiss_copy_data(priv_ep,
514 &priv_req->request);
515
516 trace_cdns3_wa2(priv_ep, "get internal stored data");
517
518 list_add_tail(&priv_req->request.list,
519 &priv_ep->pending_req_list);
520 cdns3_gadget_giveback(priv_ep, priv_req,
521 priv_req->request.status);
522
523 /*
524 * Intentionally driver returns positive value as
525 * correct value. It informs that transfer has
526 * been finished.
527 */
528 return EINPROGRESS;
529 }
530
531 /*
532 * Driver will wait for completion DESCMISS transfer,
533 * before starts new, not DESCMISS transfer.
534 */
535 if (!pending_empty && !descmiss_empty) {
536 trace_cdns3_wa2(priv_ep, "wait for pending transfer\n");
537 deferred = 1;
538 }
539
540 if (priv_req->flags & REQUEST_INTERNAL)
541 list_add_tail(&priv_req->list,
542 &priv_ep->wa2_descmiss_req_list);
543 }
544
545 return deferred;
546}
547
548static void cdns3_wa2_remove_old_request(struct cdns3_endpoint *priv_ep)
549{
550 struct cdns3_request *priv_req;
551
552 while (!list_empty(&priv_ep->wa2_descmiss_req_list)) {
553 u8 chain;
554
555 priv_req = cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list);
556 chain = !!(priv_req->flags & REQUEST_INTERNAL_CH);
557
558 trace_cdns3_wa2(priv_ep, "removes eldest request");
559
560 kfree(priv_req->request.buf);
561 cdns3_gadget_ep_free_request(&priv_ep->endpoint,
562 &priv_req->request);
563 list_del_init(&priv_req->list);
564 --priv_ep->wa2_counter;
565
566 if (!chain)
567 break;
568 }
569}
570
571/**
572 * cdns3_wa2_descmissing_packet - handles descriptor missing event.
573 * @priv_dev: extended gadget object
574 *
575 * This function is used only for WA2. For more information see Work around 2
576 * description.
577 */
578static void cdns3_wa2_descmissing_packet(struct cdns3_endpoint *priv_ep)
579{
580 struct cdns3_request *priv_req;
581 struct usb_request *request;
582
583 if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_DET) {
584 priv_ep->flags &= ~EP_QUIRK_EXTRA_BUF_DET;
585 priv_ep->flags |= EP_QUIRK_EXTRA_BUF_EN;
586 }
587
588 trace_cdns3_wa2(priv_ep, "Description Missing detected\n");
589
590 if (priv_ep->wa2_counter >= CDNS3_WA2_NUM_BUFFERS)
591 cdns3_wa2_remove_old_request(priv_ep);
592
593 request = cdns3_gadget_ep_alloc_request(&priv_ep->endpoint,
594 GFP_ATOMIC);
595 if (!request)
596 goto err;
597
598 priv_req = to_cdns3_request(request);
599 priv_req->flags |= REQUEST_INTERNAL;
600
601 /* if this field is still assigned it indicate that transfer related
602 * with this request has not been finished yet. Driver in this
603 * case simply allocate next request and assign flag REQUEST_INTERNAL_CH
604 * flag to previous one. It will indicate that current request is
605 * part of the previous one.
606 */
607 if (priv_ep->descmis_req)
608 priv_ep->descmis_req->flags |= REQUEST_INTERNAL_CH;
609
610 priv_req->request.buf = kzalloc(CDNS3_DESCMIS_BUF_SIZE,
611 GFP_ATOMIC);
612 priv_ep->wa2_counter++;
613
614 if (!priv_req->request.buf) {
615 cdns3_gadget_ep_free_request(&priv_ep->endpoint, request);
616 goto err;
617 }
618
619 priv_req->request.length = CDNS3_DESCMIS_BUF_SIZE;
620 priv_ep->descmis_req = priv_req;
621
622 __cdns3_gadget_ep_queue(&priv_ep->endpoint,
623 &priv_ep->descmis_req->request,
624 GFP_ATOMIC);
625
626 return;
627
628err:
629 dev_err(priv_ep->cdns3_dev->dev,
630 "Failed: No sufficient memory for DESCMIS\n");
631}
632
633/**
634 * cdns3_gadget_giveback - call struct usb_request's ->complete callback
635 * @priv_ep: The endpoint to whom the request belongs to
636 * @priv_req: The request we're giving back
637 * @status: completion code for the request
638 *
639 * Must be called with controller's lock held and interrupts disabled. This
640 * function will unmap @req and call its ->complete() callback to notify upper
641 * layers that it has completed.
642 */
643void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep,
644 struct cdns3_request *priv_req,
645 int status)
646{
647 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
648 struct usb_request *request = &priv_req->request;
649
650 list_del_init(&request->list);
651
652 if (request->status == -EINPROGRESS)
653 request->status = status;
654
655 usb_gadget_unmap_request(&priv_dev->gadget, request,
656 priv_ep->dir);
657
658 if ((priv_req->flags & REQUEST_UNALIGNED) &&
659 priv_ep->dir == USB_DIR_OUT && !request->status)
660 memcpy(request->buf, priv_req->aligned_buf->buf,
661 request->length);
662
663 priv_req->flags &= ~(REQUEST_PENDING | REQUEST_UNALIGNED);
664 trace_cdns3_gadget_giveback(priv_req);
665
666 if (priv_dev->dev_ver < DEV_VER_V2) {
667 request = cdns3_wa2_gadget_giveback(priv_dev, priv_ep,
668 priv_req);
669 if (!request)
670 return;
671 }
672
673 if (request->complete) {
674 spin_unlock(&priv_dev->lock);
675 usb_gadget_giveback_request(&priv_ep->endpoint,
676 request);
677 spin_lock(&priv_dev->lock);
678 }
679
680 if (request->buf == priv_dev->zlp_buf)
681 cdns3_gadget_ep_free_request(&priv_ep->endpoint, request);
682}
683
684void cdns3_wa1_restore_cycle_bit(struct cdns3_endpoint *priv_ep)
685{
686 /* Work around for stale data address in TRB*/
687 if (priv_ep->wa1_set) {
688 trace_cdns3_wa1(priv_ep, "restore cycle bit");
689
690 priv_ep->wa1_set = 0;
691 priv_ep->wa1_trb_index = 0xFFFF;
692 if (priv_ep->wa1_cycle_bit) {
693 priv_ep->wa1_trb->control =
694 priv_ep->wa1_trb->control | 0x1;
695 } else {
696 priv_ep->wa1_trb->control =
697 priv_ep->wa1_trb->control & ~0x1;
698 }
699 }
700}
701
702static void cdns3_free_aligned_request_buf(struct cdns3_device *priv_dev)
703{
704 struct cdns3_aligned_buf *buf, *tmp;
705 unsigned long flags;
706
707 spin_lock_irqsave(&priv_dev->lock, flags);
708
709 list_for_each_entry_safe(buf, tmp, &priv_dev->aligned_buf_list, list) {
710 if (!buf->in_use) {
711 list_del(&buf->list);
712
713 /*
714 * Re-enable interrupts to free DMA capable memory.
715 * Driver can't free this memory with disabled
716 * interrupts.
717 */
718 spin_unlock_irqrestore(&priv_dev->lock, flags);
719 dma_free_coherent(buf->buf);
720 kfree(buf);
721 spin_lock_irqsave(&priv_dev->lock, flags);
722 }
723 }
724
725 spin_unlock_irqrestore(&priv_dev->lock, flags);
726}
727
728static int cdns3_prepare_aligned_request_buf(struct cdns3_request *priv_req)
729{
730 struct cdns3_endpoint *priv_ep = priv_req->priv_ep;
731 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
732 struct cdns3_aligned_buf *buf;
733
734 /* check if buffer is aligned to 8. */
735 if (!((uintptr_t)priv_req->request.buf & 0x7))
736 return 0;
737
738 buf = priv_req->aligned_buf;
739
740 if (!buf || priv_req->request.length > buf->size) {
741 buf = kzalloc(sizeof(*buf), GFP_ATOMIC);
742 if (!buf)
743 return -ENOMEM;
744
745 buf->size = priv_req->request.length;
746
747 buf->buf = dma_alloc_coherent(buf->size,
748 (unsigned long *)&buf->dma);
749 if (!buf->buf) {
750 kfree(buf);
751 return -ENOMEM;
752 }
753
754 if (priv_req->aligned_buf) {
755 trace_cdns3_free_aligned_request(priv_req);
756 priv_req->aligned_buf->in_use = 0;
757#ifndef __UBOOT__
758 queue_work(system_freezable_wq,
759 &priv_dev->aligned_buf_wq);
760#else
761 cdns3_free_aligned_request_buf(priv_dev);
762#endif
763 }
764
765 buf->in_use = 1;
766 priv_req->aligned_buf = buf;
767
768 list_add_tail(&buf->list,
769 &priv_dev->aligned_buf_list);
770 }
771
772 if (priv_ep->dir == USB_DIR_IN) {
773 memcpy(buf->buf, priv_req->request.buf,
774 priv_req->request.length);
775 }
776
777 priv_req->flags |= REQUEST_UNALIGNED;
778 trace_cdns3_prepare_aligned_request(priv_req);
779
780 return 0;
781}
782
783static int cdns3_wa1_update_guard(struct cdns3_endpoint *priv_ep,
784 struct cdns3_trb *trb)
785{
786 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
787
788 if (!priv_ep->wa1_set) {
789 u32 doorbell;
790
791 doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY);
792
793 if (doorbell) {
794 priv_ep->wa1_cycle_bit = priv_ep->pcs ? TRB_CYCLE : 0;
795 priv_ep->wa1_set = 1;
796 priv_ep->wa1_trb = trb;
797 priv_ep->wa1_trb_index = priv_ep->enqueue;
798 trace_cdns3_wa1(priv_ep, "set guard");
799 return 0;
800 }
801 }
802 return 1;
803}
804
805static void cdns3_wa1_tray_restore_cycle_bit(struct cdns3_device *priv_dev,
806 struct cdns3_endpoint *priv_ep)
807{
808 int dma_index;
809 u32 doorbell;
810
811 doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY);
812 dma_index = cdns3_get_dma_pos(priv_dev, priv_ep);
813
814 if (!doorbell || dma_index != priv_ep->wa1_trb_index)
815 cdns3_wa1_restore_cycle_bit(priv_ep);
816}
817
818/**
819 * cdns3_ep_run_transfer - start transfer on no-default endpoint hardware
820 * @priv_ep: endpoint object
821 *
822 * Returns zero on success or negative value on failure
823 */
824int cdns3_ep_run_transfer(struct cdns3_endpoint *priv_ep,
825 struct usb_request *request)
826{
827 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
828 struct cdns3_request *priv_req;
829 struct cdns3_trb *trb;
830 dma_addr_t trb_dma;
831 u32 togle_pcs = 1;
832 int sg_iter = 0;
833 int num_trb = 1;
834 int address;
835 u32 control;
836 int pcs;
837
838 if (num_trb > priv_ep->free_trbs) {
839 priv_ep->flags |= EP_RING_FULL;
840 return -ENOBUFS;
841 }
842
843 priv_req = to_cdns3_request(request);
844 address = priv_ep->endpoint.desc->bEndpointAddress;
845
846 priv_ep->flags |= EP_PENDING_REQUEST;
847
848 /* must allocate buffer aligned to 8 */
849 if (priv_req->flags & REQUEST_UNALIGNED)
850 trb_dma = priv_req->aligned_buf->dma;
851 else
852 trb_dma = request->dma;
853
854 trb = priv_ep->trb_pool + priv_ep->enqueue;
855 priv_req->start_trb = priv_ep->enqueue;
856 priv_req->trb = trb;
857
858 cdns3_select_ep(priv_ep->cdns3_dev, address);
859
860 /* prepare ring */
861 if ((priv_ep->enqueue + num_trb) >= (priv_ep->num_trbs - 1)) {
862 struct cdns3_trb *link_trb;
863 int doorbell, dma_index;
864 u32 ch_bit = 0;
865
866 doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY);
867 dma_index = cdns3_get_dma_pos(priv_dev, priv_ep);
868
869 /* Driver can't update LINK TRB if it is current processed. */
870 if (doorbell && dma_index == priv_ep->num_trbs - 1) {
871 priv_ep->flags |= EP_DEFERRED_DRDY;
872 return -ENOBUFS;
873 }
874
875 /*updating C bt in Link TRB before starting DMA*/
876 link_trb = priv_ep->trb_pool + (priv_ep->num_trbs - 1);
877 /*
878 * For TRs size equal 2 enabling TRB_CHAIN for epXin causes
879 * that DMA stuck at the LINK TRB.
880 * On the other hand, removing TRB_CHAIN for longer TRs for
881 * epXout cause that DMA stuck after handling LINK TRB.
882 * To eliminate this strange behavioral driver set TRB_CHAIN
883 * bit only for TR size > 2.
884 */
885 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC ||
886 TRBS_PER_SEGMENT > 2)
887 ch_bit = TRB_CHAIN;
888
889 link_trb->control = ((priv_ep->pcs) ? TRB_CYCLE : 0) |
890 TRB_TYPE(TRB_LINK) | TRB_TOGGLE | ch_bit;
891 }
892
893 if (priv_dev->dev_ver <= DEV_VER_V2)
894 togle_pcs = cdns3_wa1_update_guard(priv_ep, trb);
895
896 /* set incorrect Cycle Bit for first trb*/
897 control = priv_ep->pcs ? 0 : TRB_CYCLE;
898
899 do {
900 u32 length;
901 u16 td_size = 0;
902
903 /* fill TRB */
904 control |= TRB_TYPE(TRB_NORMAL);
905 trb->buffer = TRB_BUFFER(trb_dma);
906
907 length = request->length;
908
909 if (likely(priv_dev->dev_ver >= DEV_VER_V2))
910 td_size = DIV_ROUND_UP(length,
911 priv_ep->endpoint.maxpacket);
912
913 trb->length = TRB_BURST_LEN(priv_ep->trb_burst_size) |
914 TRB_LEN(length);
915 if (priv_dev->gadget.speed == USB_SPEED_SUPER)
916 trb->length |= TRB_TDL_SS_SIZE(td_size);
917 else
918 control |= TRB_TDL_HS_SIZE(td_size);
919
920 pcs = priv_ep->pcs ? TRB_CYCLE : 0;
921
922 /*
923 * first trb should be prepared as last to avoid processing
924 * transfer to early
925 */
926 if (sg_iter != 0)
927 control |= pcs;
928
929 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir) {
930 control |= TRB_IOC | TRB_ISP;
931 } else {
932 /* for last element in TD or in SG list */
933 if (sg_iter == (num_trb - 1) && sg_iter != 0)
934 control |= pcs | TRB_IOC | TRB_ISP;
935 }
936
937 if (sg_iter)
938 trb->control = control;
939 else
940 priv_req->trb->control = control;
941
942 control = 0;
943 ++sg_iter;
944 priv_req->end_trb = priv_ep->enqueue;
945 cdns3_ep_inc_enq(priv_ep);
946 trb = priv_ep->trb_pool + priv_ep->enqueue;
947 } while (sg_iter < num_trb);
948
949 trb = priv_req->trb;
950
951 priv_req->flags |= REQUEST_PENDING;
952
953 if (sg_iter == 1)
954 trb->control |= TRB_IOC | TRB_ISP;
955
956 /*
957 * Memory barrier - cycle bit must be set before other filds in trb.
958 */
959 dmb();
960
961 /* give the TD to the consumer*/
962 if (togle_pcs)
963 trb->control = trb->control ^ 1;
964
965 if (priv_dev->dev_ver <= DEV_VER_V2)
966 cdns3_wa1_tray_restore_cycle_bit(priv_dev, priv_ep);
967
Siddharth Vadapalli17da9792024-09-30 15:04:07 +0530968 /* Flush TRBs */
969 flush_dcache_range((unsigned long)priv_ep->trb_pool,
970 (unsigned long)priv_ep->trb_pool +
971 ROUND(sizeof(struct cdns3_trb) * priv_ep->num_trbs,
972 CONFIG_SYS_CACHELINE_SIZE));
973
Vignesh Raghavendra7e91f6c2019-10-01 17:26:33 +0530974 trace_cdns3_prepare_trb(priv_ep, priv_req->trb);
975
976 /*
977 * Memory barrier - Cycle Bit must be set before trb->length and
978 * trb->buffer fields.
979 */
980 dmb();
981
982 /*
983 * For DMULT mode we can set address to transfer ring only once after
984 * enabling endpoint.
985 */
986 if (priv_ep->flags & EP_UPDATE_EP_TRBADDR) {
987 /*
988 * Until SW is not ready to handle the OUT transfer the ISO OUT
989 * Endpoint should be disabled (EP_CFG.ENABLE = 0).
990 * EP_CFG_ENABLE must be set before updating ep_traddr.
991 */
992 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir &&
993 !(priv_ep->flags & EP_QUIRK_ISO_OUT_EN)) {
994 priv_ep->flags |= EP_QUIRK_ISO_OUT_EN;
995 cdns3_set_register_bit(&priv_dev->regs->ep_cfg,
996 EP_CFG_ENABLE);
997 }
998
999 writel(EP_TRADDR_TRADDR(priv_ep->trb_pool_dma +
1000 priv_req->start_trb * TRB_SIZE),
1001 &priv_dev->regs->ep_traddr);
1002
1003 priv_ep->flags &= ~EP_UPDATE_EP_TRBADDR;
1004 }
1005
1006 if (!priv_ep->wa1_set && !(priv_ep->flags & EP_STALLED)) {
1007 trace_cdns3_ring(priv_ep);
1008 /*clearing TRBERR and EP_STS_DESCMIS before seting DRDY*/
1009 writel(EP_STS_TRBERR | EP_STS_DESCMIS, &priv_dev->regs->ep_sts);
1010 writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd);
1011 trace_cdns3_doorbell_epx(priv_ep->name,
1012 readl(&priv_dev->regs->ep_traddr));
1013 }
1014
1015 /* WORKAROUND for transition to L0 */
1016 __cdns3_gadget_wakeup(priv_dev);
1017
1018 return 0;
1019}
1020
1021void cdns3_set_hw_configuration(struct cdns3_device *priv_dev)
1022{
1023 struct cdns3_endpoint *priv_ep;
1024 struct usb_ep *ep;
1025 int val;
1026
1027 if (priv_dev->hw_configured_flag)
1028 return;
1029
1030 writel(USB_CONF_CFGSET, &priv_dev->regs->usb_conf);
1031 writel(EP_CMD_ERDY | EP_CMD_REQ_CMPL, &priv_dev->regs->ep_cmd);
1032
1033 cdns3_set_register_bit(&priv_dev->regs->usb_conf,
1034 USB_CONF_U1EN | USB_CONF_U2EN);
1035
1036 /* wait until configuration set */
1037 readl_poll_timeout_atomic(&priv_dev->regs->usb_sts, val,
1038 val & USB_STS_CFGSTS_MASK, 100);
1039
1040 priv_dev->hw_configured_flag = 1;
1041
1042 list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) {
1043 priv_ep = ep_to_cdns3_ep(ep);
1044 if (priv_ep->flags & EP_ENABLED)
1045 cdns3_start_all_request(priv_dev, priv_ep);
1046 }
1047}
1048
1049/**
1050 * cdns3_request_handled - check whether request has been handled by DMA
1051 *
1052 * @priv_ep: extended endpoint object.
1053 * @priv_req: request object for checking
1054 *
1055 * Endpoint must be selected before invoking this function.
1056 *
1057 * Returns false if request has not been handled by DMA, else returns true.
1058 *
1059 * SR - start ring
1060 * ER - end ring
1061 * DQ = priv_ep->dequeue - dequeue position
1062 * EQ = priv_ep->enqueue - enqueue position
1063 * ST = priv_req->start_trb - index of first TRB in transfer ring
1064 * ET = priv_req->end_trb - index of last TRB in transfer ring
1065 * CI = current_index - index of processed TRB by DMA.
1066 *
1067 * As first step, function checks if cycle bit for priv_req->start_trb is
1068 * correct.
1069 *
1070 * some rules:
1071 * 1. priv_ep->dequeue never exceed current_index.
1072 * 2 priv_ep->enqueue never exceed priv_ep->dequeue
1073 * 3. exception: priv_ep->enqueue == priv_ep->dequeue
1074 * and priv_ep->free_trbs is zero.
1075 * This case indicate that TR is full.
1076 *
1077 * Then We can split recognition into two parts:
1078 * Case 1 - priv_ep->dequeue < current_index
1079 * SR ... EQ ... DQ ... CI ... ER
1080 * SR ... DQ ... CI ... EQ ... ER
1081 *
1082 * Request has been handled by DMA if ST and ET is between DQ and CI.
1083 *
1084 * Case 2 - priv_ep->dequeue > current_index
1085 * This situation take place when CI go through the LINK TRB at the end of
1086 * transfer ring.
1087 * SR ... CI ... EQ ... DQ ... ER
1088 *
1089 * Request has been handled by DMA if ET is less then CI or
1090 * ET is greater or equal DQ.
1091 */
1092static bool cdns3_request_handled(struct cdns3_endpoint *priv_ep,
1093 struct cdns3_request *priv_req)
1094{
1095 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
1096 struct cdns3_trb *trb = priv_req->trb;
1097 int current_index = 0;
1098 int handled = 0;
1099 int doorbell;
1100
1101 current_index = cdns3_get_dma_pos(priv_dev, priv_ep);
1102 doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY);
1103
1104 trb = &priv_ep->trb_pool[priv_req->start_trb];
1105
1106 if ((trb->control & TRB_CYCLE) != priv_ep->ccs)
1107 goto finish;
1108
1109 if (doorbell == 1 && current_index == priv_ep->dequeue)
1110 goto finish;
1111
1112 /* The corner case for TRBS_PER_SEGMENT equal 2). */
1113 if (TRBS_PER_SEGMENT == 2 && priv_ep->type != USB_ENDPOINT_XFER_ISOC) {
1114 handled = 1;
1115 goto finish;
1116 }
1117
1118 if (priv_ep->enqueue == priv_ep->dequeue &&
1119 priv_ep->free_trbs == 0) {
1120 handled = 1;
1121 } else if (priv_ep->dequeue < current_index) {
1122 if ((current_index == (priv_ep->num_trbs - 1)) &&
1123 !priv_ep->dequeue)
1124 goto finish;
1125
1126 if (priv_req->end_trb >= priv_ep->dequeue &&
1127 priv_req->end_trb < current_index)
1128 handled = 1;
1129 } else if (priv_ep->dequeue > current_index) {
1130 if (priv_req->end_trb < current_index ||
1131 priv_req->end_trb >= priv_ep->dequeue)
1132 handled = 1;
1133 }
1134
1135finish:
1136 trace_cdns3_request_handled(priv_req, current_index, handled);
1137
1138 return handled;
1139}
1140
1141static void cdns3_transfer_completed(struct cdns3_device *priv_dev,
1142 struct cdns3_endpoint *priv_ep)
1143{
1144 struct cdns3_request *priv_req;
1145 struct usb_request *request;
1146 struct cdns3_trb *trb;
1147
1148 while (!list_empty(&priv_ep->pending_req_list)) {
1149 request = cdns3_next_request(&priv_ep->pending_req_list);
1150 priv_req = to_cdns3_request(request);
1151
1152 /* Re-select endpoint. It could be changed by other CPU during
1153 * handling usb_gadget_giveback_request.
1154 */
1155#ifndef __UBOOT__
1156 cdns3_select_ep(priv_dev, priv_ep->endpoint.address);
1157#else
1158 cdns3_select_ep(priv_dev,
1159 priv_ep->endpoint.desc->bEndpointAddress);
1160#endif
1161
Siddharth Vadapalli17da9792024-09-30 15:04:07 +05301162 /* Invalidate TRBs */
1163 invalidate_dcache_range((unsigned long)priv_ep->trb_pool,
1164 (unsigned long)priv_ep->trb_pool +
1165 ROUND(sizeof(struct cdns3_trb) *
1166 priv_ep->num_trbs,
1167 CONFIG_SYS_CACHELINE_SIZE));
1168
Vignesh Raghavendra7e91f6c2019-10-01 17:26:33 +05301169 if (!cdns3_request_handled(priv_ep, priv_req))
1170 goto prepare_next_td;
1171
1172 trb = priv_ep->trb_pool + priv_ep->dequeue;
1173 trace_cdns3_complete_trb(priv_ep, trb);
1174
1175 if (trb != priv_req->trb)
1176 dev_warn(priv_dev->dev,
1177 "request_trb=0x%p, queue_trb=0x%p\n",
1178 priv_req->trb, trb);
1179
1180 request->actual = TRB_LEN(le32_to_cpu(trb->length));
1181 cdns3_move_deq_to_next_trb(priv_req);
1182 cdns3_gadget_giveback(priv_ep, priv_req, 0);
1183
1184 if (priv_ep->type != USB_ENDPOINT_XFER_ISOC &&
1185 TRBS_PER_SEGMENT == 2)
1186 break;
1187 }
1188 priv_ep->flags &= ~EP_PENDING_REQUEST;
1189
1190prepare_next_td:
1191 if (!(priv_ep->flags & EP_STALLED) &&
1192 !(priv_ep->flags & EP_STALL_PENDING))
1193 cdns3_start_all_request(priv_dev, priv_ep);
1194}
1195
1196void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm)
1197{
1198 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
1199
1200 cdns3_wa1_restore_cycle_bit(priv_ep);
1201
1202 if (rearm) {
1203 trace_cdns3_ring(priv_ep);
1204
1205 /* Cycle Bit must be updated before arming DMA. */
1206 dmb();
1207 writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd);
1208
1209 __cdns3_gadget_wakeup(priv_dev);
1210
1211 trace_cdns3_doorbell_epx(priv_ep->name,
1212 readl(&priv_dev->regs->ep_traddr));
1213 }
1214}
1215
1216/**
1217 * cdns3_check_ep_interrupt_proceed - Processes interrupt related to endpoint
1218 * @priv_ep: endpoint object
1219 *
1220 * Returns 0
1221 */
1222static int cdns3_check_ep_interrupt_proceed(struct cdns3_endpoint *priv_ep)
1223{
1224 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
1225 u32 ep_sts_reg;
1226
1227#ifndef __UBOOT__
1228 cdns3_select_ep(priv_dev, priv_ep->endpoint.address);
1229#else
1230 cdns3_select_ep(priv_dev, priv_ep->endpoint.desc->bEndpointAddress);
1231#endif
1232
1233 trace_cdns3_epx_irq(priv_dev, priv_ep);
1234
1235 ep_sts_reg = readl(&priv_dev->regs->ep_sts);
1236 writel(ep_sts_reg, &priv_dev->regs->ep_sts);
1237
1238 if (ep_sts_reg & EP_STS_TRBERR) {
1239 if (priv_ep->flags & EP_STALL_PENDING &&
1240 !(ep_sts_reg & EP_STS_DESCMIS &&
1241 priv_dev->dev_ver < DEV_VER_V2)) {
1242 cdns3_ep_stall_flush(priv_ep);
1243 }
1244
1245 /*
1246 * For isochronous transfer driver completes request on
1247 * IOC or on TRBERR. IOC appears only when device receive
1248 * OUT data packet. If host disable stream or lost some packet
1249 * then the only way to finish all queued transfer is to do it
1250 * on TRBERR event.
1251 */
1252 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC &&
1253 !priv_ep->wa1_set) {
1254 if (!priv_ep->dir) {
1255 u32 ep_cfg = readl(&priv_dev->regs->ep_cfg);
1256
1257 ep_cfg &= ~EP_CFG_ENABLE;
1258 writel(ep_cfg, &priv_dev->regs->ep_cfg);
1259 priv_ep->flags &= ~EP_QUIRK_ISO_OUT_EN;
1260 }
1261 cdns3_transfer_completed(priv_dev, priv_ep);
1262 } else if (!(priv_ep->flags & EP_STALLED) &&
1263 !(priv_ep->flags & EP_STALL_PENDING)) {
1264 if (priv_ep->flags & EP_DEFERRED_DRDY) {
1265 priv_ep->flags &= ~EP_DEFERRED_DRDY;
1266 cdns3_start_all_request(priv_dev, priv_ep);
1267 } else {
1268 cdns3_rearm_transfer(priv_ep,
1269 priv_ep->wa1_set);
1270 }
1271 }
1272 }
1273
1274 if ((ep_sts_reg & EP_STS_IOC) || (ep_sts_reg & EP_STS_ISP)) {
1275 if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN) {
1276 if (ep_sts_reg & EP_STS_ISP)
1277 priv_ep->flags |= EP_QUIRK_END_TRANSFER;
1278 else
1279 priv_ep->flags &= ~EP_QUIRK_END_TRANSFER;
1280 }
1281
1282 cdns3_transfer_completed(priv_dev, priv_ep);
1283 }
1284
1285 /*
1286 * WA2: this condition should only be meet when
1287 * priv_ep->flags & EP_QUIRK_EXTRA_BUF_DET or
1288 * priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN.
1289 * In other cases this interrupt will be disabled/
1290 */
1291 if (ep_sts_reg & EP_STS_DESCMIS && priv_dev->dev_ver < DEV_VER_V2 &&
1292 !(priv_ep->flags & EP_STALLED))
1293 cdns3_wa2_descmissing_packet(priv_ep);
1294
1295 return 0;
1296}
1297
1298static void cdns3_disconnect_gadget(struct cdns3_device *priv_dev)
1299{
1300 if (priv_dev->gadget_driver && priv_dev->gadget_driver->disconnect) {
1301 spin_unlock(&priv_dev->lock);
1302 priv_dev->gadget_driver->disconnect(&priv_dev->gadget);
1303 spin_lock(&priv_dev->lock);
1304 }
1305}
1306
1307/**
1308 * cdns3_check_usb_interrupt_proceed - Processes interrupt related to device
1309 * @priv_dev: extended gadget object
1310 * @usb_ists: bitmap representation of device's reported interrupts
1311 * (usb_ists register value)
1312 */
1313static void cdns3_check_usb_interrupt_proceed(struct cdns3_device *priv_dev,
1314 u32 usb_ists)
1315{
1316 int speed = 0;
1317
1318 trace_cdns3_usb_irq(priv_dev, usb_ists);
1319 if (usb_ists & USB_ISTS_L1ENTI) {
1320 /*
1321 * WORKAROUND: CDNS3 controller has issue with hardware resuming
1322 * from L1. To fix it, if any DMA transfer is pending driver
1323 * must starts driving resume signal immediately.
1324 */
1325 if (readl(&priv_dev->regs->drbl))
1326 __cdns3_gadget_wakeup(priv_dev);
1327 }
1328
1329 /* Connection detected */
1330 if (usb_ists & (USB_ISTS_CON2I | USB_ISTS_CONI)) {
1331 speed = cdns3_get_speed(priv_dev);
1332 priv_dev->gadget.speed = speed;
1333 usb_gadget_set_state(&priv_dev->gadget, USB_STATE_POWERED);
1334 cdns3_ep0_config(priv_dev);
1335 }
1336
1337 /* Disconnection detected */
1338 if (usb_ists & (USB_ISTS_DIS2I | USB_ISTS_DISI)) {
1339 cdns3_disconnect_gadget(priv_dev);
1340 priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
1341 usb_gadget_set_state(&priv_dev->gadget, USB_STATE_NOTATTACHED);
1342 cdns3_hw_reset_eps_config(priv_dev);
1343 }
1344
1345 if (usb_ists & (USB_ISTS_L2ENTI | USB_ISTS_U3ENTI)) {
1346 if (priv_dev->gadget_driver &&
1347 priv_dev->gadget_driver->suspend) {
1348 spin_unlock(&priv_dev->lock);
1349 priv_dev->gadget_driver->suspend(&priv_dev->gadget);
1350 spin_lock(&priv_dev->lock);
1351 }
1352 }
1353
1354 if (usb_ists & (USB_ISTS_L2EXTI | USB_ISTS_U3EXTI)) {
1355 if (priv_dev->gadget_driver &&
1356 priv_dev->gadget_driver->resume) {
1357 spin_unlock(&priv_dev->lock);
1358 priv_dev->gadget_driver->resume(&priv_dev->gadget);
1359 spin_lock(&priv_dev->lock);
1360 }
1361 }
1362
1363 /* reset*/
1364 if (usb_ists & (USB_ISTS_UWRESI | USB_ISTS_UHRESI | USB_ISTS_U2RESI)) {
1365 if (priv_dev->gadget_driver) {
1366 spin_unlock(&priv_dev->lock);
1367 usb_gadget_udc_reset(&priv_dev->gadget,
1368 priv_dev->gadget_driver);
1369 spin_lock(&priv_dev->lock);
1370
1371 /*read again to check the actual speed*/
1372 speed = cdns3_get_speed(priv_dev);
1373 priv_dev->gadget.speed = speed;
1374 cdns3_hw_reset_eps_config(priv_dev);
1375 cdns3_ep0_config(priv_dev);
1376 }
1377 }
1378}
1379
1380/**
1381 * cdns3_device_irq_handler- interrupt handler for device part of controller
1382 *
1383 * @irq: irq number for cdns3 core device
1384 * @data: structure of cdns3
1385 *
1386 * Returns IRQ_HANDLED or IRQ_NONE
1387 */
1388static irqreturn_t cdns3_device_irq_handler(int irq, void *data)
1389{
1390 struct cdns3_device *priv_dev;
1391 struct cdns3 *cdns = data;
1392 irqreturn_t ret = IRQ_NONE;
1393 u32 reg;
1394
1395 priv_dev = cdns->gadget_dev;
1396
1397 /* check USB device interrupt */
1398 reg = readl(&priv_dev->regs->usb_ists);
1399 if (reg) {
1400 /* After masking interrupts the new interrupts won't be
1401 * reported in usb_ists/ep_ists. In order to not lose some
1402 * of them driver disables only detected interrupts.
1403 * They will be enabled ASAP after clearing source of
1404 * interrupt. This an unusual behavior only applies to
1405 * usb_ists register.
1406 */
1407 reg = ~reg & readl(&priv_dev->regs->usb_ien);
1408 /* mask deferred interrupt. */
1409 writel(reg, &priv_dev->regs->usb_ien);
1410 ret = IRQ_WAKE_THREAD;
1411 }
1412
1413 /* check endpoint interrupt */
1414 reg = readl(&priv_dev->regs->ep_ists);
1415 if (reg) {
1416 writel(0, &priv_dev->regs->ep_ien);
1417 ret = IRQ_WAKE_THREAD;
1418 }
1419
1420 return ret;
1421}
1422
1423/**
1424 * cdns3_device_thread_irq_handler- interrupt handler for device part
1425 * of controller
1426 *
1427 * @irq: irq number for cdns3 core device
1428 * @data: structure of cdns3
1429 *
1430 * Returns IRQ_HANDLED or IRQ_NONE
1431 */
1432static irqreturn_t cdns3_device_thread_irq_handler(int irq, void *data)
1433{
1434 struct cdns3_device *priv_dev;
1435 struct cdns3 *cdns = data;
1436 irqreturn_t ret = IRQ_NONE;
1437 unsigned long flags;
1438 int bit;
1439 u32 reg;
1440
1441 priv_dev = cdns->gadget_dev;
1442 spin_lock_irqsave(&priv_dev->lock, flags);
1443
1444 reg = readl(&priv_dev->regs->usb_ists);
1445 if (reg) {
1446 writel(reg, &priv_dev->regs->usb_ists);
1447 writel(USB_IEN_INIT, &priv_dev->regs->usb_ien);
1448 cdns3_check_usb_interrupt_proceed(priv_dev, reg);
1449 ret = IRQ_HANDLED;
1450 }
1451
1452 reg = readl(&priv_dev->regs->ep_ists);
1453
1454 /* handle default endpoint OUT */
1455 if (reg & EP_ISTS_EP_OUT0) {
1456 cdns3_check_ep0_interrupt_proceed(priv_dev, USB_DIR_OUT);
1457 ret = IRQ_HANDLED;
1458 }
1459
1460 /* handle default endpoint IN */
1461 if (reg & EP_ISTS_EP_IN0) {
1462 cdns3_check_ep0_interrupt_proceed(priv_dev, USB_DIR_IN);
1463 ret = IRQ_HANDLED;
1464 }
1465
1466 /* check if interrupt from non default endpoint, if no exit */
1467 reg &= ~(EP_ISTS_EP_OUT0 | EP_ISTS_EP_IN0);
1468 if (!reg)
1469 goto irqend;
1470
1471 for_each_set_bit(bit, (unsigned long *)&reg,
1472 sizeof(u32) * BITS_PER_BYTE) {
1473 cdns3_check_ep_interrupt_proceed(priv_dev->eps[bit]);
1474 ret = IRQ_HANDLED;
1475 }
1476
1477irqend:
1478 writel(~0, &priv_dev->regs->ep_ien);
1479 spin_unlock_irqrestore(&priv_dev->lock, flags);
1480
1481 return ret;
1482}
1483
1484/**
1485 * cdns3_ep_onchip_buffer_reserve - Try to reserve onchip buf for EP
1486 *
1487 * The real reservation will occur during write to EP_CFG register,
1488 * this function is used to check if the 'size' reservation is allowed.
1489 *
1490 * @priv_dev: extended gadget object
1491 * @size: the size (KB) for EP would like to allocate
1492 * @is_in: endpoint direction
1493 *
1494 * Return 0 if the required size can met or negative value on failure
1495 */
1496static int cdns3_ep_onchip_buffer_reserve(struct cdns3_device *priv_dev,
1497 int size, int is_in)
1498{
1499 int remained;
1500
1501 /* 2KB are reserved for EP0*/
1502 remained = priv_dev->onchip_buffers - priv_dev->onchip_used_size - 2;
1503
1504 if (is_in) {
1505 if (remained < size)
1506 return -EPERM;
1507
1508 priv_dev->onchip_used_size += size;
1509 } else {
1510 int required;
1511
1512 /**
1513 * ALL OUT EPs are shared the same chunk onchip memory, so
1514 * driver checks if it already has assigned enough buffers
1515 */
1516 if (priv_dev->out_mem_is_allocated >= size)
1517 return 0;
1518
1519 required = size - priv_dev->out_mem_is_allocated;
1520
1521 if (required > remained)
1522 return -EPERM;
1523
1524 priv_dev->out_mem_is_allocated += required;
1525 priv_dev->onchip_used_size += required;
1526 }
1527
1528 return 0;
1529}
1530
1531void cdns3_configure_dmult(struct cdns3_device *priv_dev,
1532 struct cdns3_endpoint *priv_ep)
1533{
1534 struct cdns3_usb_regs __iomem *regs = priv_dev->regs;
1535
1536 /* For dev_ver > DEV_VER_V2 DMULT is configured per endpoint */
1537 if (priv_dev->dev_ver <= DEV_VER_V2)
1538 writel(USB_CONF_DMULT, &regs->usb_conf);
1539
1540 if (priv_dev->dev_ver == DEV_VER_V2)
1541 writel(USB_CONF2_EN_TDL_TRB, &regs->usb_conf2);
1542
1543 if (priv_dev->dev_ver >= DEV_VER_V3 && priv_ep) {
1544 u32 mask;
1545
1546 if (priv_ep->dir)
1547 mask = BIT(priv_ep->num + 16);
1548 else
1549 mask = BIT(priv_ep->num);
1550
1551 if (priv_ep->type != USB_ENDPOINT_XFER_ISOC) {
1552 cdns3_set_register_bit(&regs->tdl_from_trb, mask);
1553 cdns3_set_register_bit(&regs->tdl_beh, mask);
1554 cdns3_set_register_bit(&regs->tdl_beh2, mask);
1555 cdns3_set_register_bit(&regs->dma_adv_td, mask);
1556 }
1557
1558 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir)
1559 cdns3_set_register_bit(&regs->tdl_from_trb, mask);
1560
1561 cdns3_set_register_bit(&regs->dtrans, mask);
1562 }
1563}
1564
1565/**
1566 * cdns3_ep_config Configure hardware endpoint
1567 * @priv_ep: extended endpoint object
1568 */
1569void cdns3_ep_config(struct cdns3_endpoint *priv_ep)
1570{
1571 bool is_iso_ep = (priv_ep->type == USB_ENDPOINT_XFER_ISOC);
1572 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
1573 u32 bEndpointAddress = priv_ep->num | priv_ep->dir;
1574 u32 max_packet_size = 0;
1575 u8 maxburst = 0;
1576 u32 ep_cfg = 0;
1577 u8 buffering;
1578 u8 mult = 0;
1579 int ret;
1580
1581 buffering = CDNS3_EP_BUF_SIZE - 1;
1582
1583 cdns3_configure_dmult(priv_dev, priv_ep);
1584
1585 switch (priv_ep->type) {
1586 case USB_ENDPOINT_XFER_INT:
1587 ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_INT);
1588
1589 if ((priv_dev->dev_ver == DEV_VER_V2 && !priv_ep->dir) ||
1590 priv_dev->dev_ver > DEV_VER_V2)
1591 ep_cfg |= EP_CFG_TDL_CHK;
1592 break;
1593 case USB_ENDPOINT_XFER_BULK:
1594 ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_BULK);
1595
1596 if ((priv_dev->dev_ver == DEV_VER_V2 && !priv_ep->dir) ||
1597 priv_dev->dev_ver > DEV_VER_V2)
1598 ep_cfg |= EP_CFG_TDL_CHK;
1599 break;
1600 default:
1601 ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_ISOC);
1602 mult = CDNS3_EP_ISO_HS_MULT - 1;
1603 buffering = mult + 1;
1604 }
1605
1606 switch (priv_dev->gadget.speed) {
1607 case USB_SPEED_FULL:
1608 max_packet_size = is_iso_ep ? 1023 : 64;
1609 break;
1610 case USB_SPEED_HIGH:
1611 max_packet_size = is_iso_ep ? 1024 : 512;
1612 break;
1613 case USB_SPEED_SUPER:
1614 /* It's limitation that driver assumes in driver. */
1615 mult = 0;
1616 max_packet_size = 1024;
1617 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC) {
1618 maxburst = CDNS3_EP_ISO_SS_BURST - 1;
1619 buffering = (mult + 1) *
1620 (maxburst + 1);
1621
1622 if (priv_ep->interval > 1)
1623 buffering++;
1624 } else {
1625 maxburst = CDNS3_EP_BUF_SIZE - 1;
1626 }
1627 break;
1628 default:
1629 /* all other speed are not supported */
1630 return;
1631 }
1632
1633 if (max_packet_size == 1024)
1634 priv_ep->trb_burst_size = 128;
1635 else if (max_packet_size >= 512)
1636 priv_ep->trb_burst_size = 64;
1637 else
1638 priv_ep->trb_burst_size = 16;
1639
1640 ret = cdns3_ep_onchip_buffer_reserve(priv_dev, buffering + 1,
1641 !!priv_ep->dir);
1642 if (ret) {
1643 dev_err(priv_dev->dev, "onchip mem is full, ep is invalid\n");
1644 return;
1645 }
1646
1647 ep_cfg |= EP_CFG_MAXPKTSIZE(max_packet_size) |
1648 EP_CFG_MULT(mult) |
1649 EP_CFG_BUFFERING(buffering) |
1650 EP_CFG_MAXBURST(maxburst);
1651
1652 cdns3_select_ep(priv_dev, bEndpointAddress);
1653 writel(ep_cfg, &priv_dev->regs->ep_cfg);
1654
1655 dev_dbg(priv_dev->dev, "Configure %s: with val %08x\n",
1656 priv_ep->name, ep_cfg);
1657}
1658
1659/* Find correct direction for HW endpoint according to description */
1660static int cdns3_ep_dir_is_correct(struct usb_endpoint_descriptor *desc,
1661 struct cdns3_endpoint *priv_ep)
1662{
1663 return (priv_ep->endpoint.caps.dir_in && usb_endpoint_dir_in(desc)) ||
1664 (priv_ep->endpoint.caps.dir_out && usb_endpoint_dir_out(desc));
1665}
1666
1667static struct
1668cdns3_endpoint *cdns3_find_available_ep(struct cdns3_device *priv_dev,
1669 struct usb_endpoint_descriptor *desc)
1670{
1671 struct usb_ep *ep;
1672 struct cdns3_endpoint *priv_ep;
1673
1674 list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) {
1675 unsigned long num;
1676 /* ep name pattern likes epXin or epXout */
1677 char c[2] = {ep->name[2], '\0'};
1678
Simon Glass0b1284e2021-07-24 09:03:30 -06001679 num = dectoul(c, NULL);
Vignesh Raghavendra7e91f6c2019-10-01 17:26:33 +05301680
1681 priv_ep = ep_to_cdns3_ep(ep);
1682 if (cdns3_ep_dir_is_correct(desc, priv_ep)) {
1683 if (!(priv_ep->flags & EP_CLAIMED)) {
1684 priv_ep->num = num;
1685 return priv_ep;
1686 }
1687 }
1688 }
1689
1690 return ERR_PTR(-ENOENT);
1691}
1692
1693/*
1694 * Cadence IP has one limitation that all endpoints must be configured
1695 * (Type & MaxPacketSize) before setting configuration through hardware
1696 * register, it means we can't change endpoints configuration after
1697 * set_configuration.
1698 *
1699 * This function set EP_CLAIMED flag which is added when the gadget driver
1700 * uses usb_ep_autoconfig to configure specific endpoint;
1701 * When the udc driver receives set_configurion request,
1702 * it goes through all claimed endpoints, and configure all endpoints
1703 * accordingly.
1704 *
1705 * At usb_ep_ops.enable/disable, we only enable and disable endpoint through
1706 * ep_cfg register which can be changed after set_configuration, and do
1707 * some software operation accordingly.
1708 */
1709static struct
1710usb_ep *cdns3_gadget_match_ep(struct usb_gadget *gadget,
1711 struct usb_endpoint_descriptor *desc,
1712 struct usb_ss_ep_comp_descriptor *comp_desc)
1713{
1714 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
1715 struct cdns3_endpoint *priv_ep;
1716 unsigned long flags;
1717
1718 priv_ep = cdns3_find_available_ep(priv_dev, desc);
1719 if (IS_ERR(priv_ep)) {
1720 dev_err(priv_dev->dev, "no available ep\n");
1721 return NULL;
1722 }
1723
1724 dev_dbg(priv_dev->dev, "match endpoint: %s\n", priv_ep->name);
1725
1726 spin_lock_irqsave(&priv_dev->lock, flags);
1727 priv_ep->endpoint.desc = desc;
1728 priv_ep->dir = usb_endpoint_dir_in(desc) ? USB_DIR_IN : USB_DIR_OUT;
1729 priv_ep->type = usb_endpoint_type(desc);
1730 priv_ep->flags |= EP_CLAIMED;
1731 priv_ep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0;
1732
1733 spin_unlock_irqrestore(&priv_dev->lock, flags);
1734 return &priv_ep->endpoint;
1735}
1736
1737/**
1738 * cdns3_gadget_ep_alloc_request Allocates request
1739 * @ep: endpoint object associated with request
1740 * @gfp_flags: gfp flags
1741 *
1742 * Returns allocated request address, NULL on allocation error
1743 */
1744struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep,
1745 gfp_t gfp_flags)
1746{
1747 struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
1748 struct cdns3_request *priv_req;
1749
1750 priv_req = kzalloc(sizeof(*priv_req), gfp_flags);
1751 if (!priv_req)
1752 return NULL;
1753
1754 priv_req->priv_ep = priv_ep;
1755
1756 trace_cdns3_alloc_request(priv_req);
1757 return &priv_req->request;
1758}
1759
1760/**
1761 * cdns3_gadget_ep_free_request Free memory occupied by request
1762 * @ep: endpoint object associated with request
1763 * @request: request to free memory
1764 */
1765void cdns3_gadget_ep_free_request(struct usb_ep *ep,
1766 struct usb_request *request)
1767{
1768 struct cdns3_request *priv_req = to_cdns3_request(request);
1769
1770 if (priv_req->aligned_buf)
1771 priv_req->aligned_buf->in_use = 0;
1772
1773 trace_cdns3_free_request(priv_req);
1774 kfree(priv_req);
1775}
1776
1777/**
1778 * cdns3_gadget_ep_enable Enable endpoint
1779 * @ep: endpoint object
1780 * @desc: endpoint descriptor
1781 *
1782 * Returns 0 on success, error code elsewhere
1783 */
1784static int cdns3_gadget_ep_enable(struct usb_ep *ep,
1785 const struct usb_endpoint_descriptor *desc)
1786{
1787 struct cdns3_endpoint *priv_ep;
1788 struct cdns3_device *priv_dev;
1789 u32 reg = EP_STS_EN_TRBERREN;
1790 u32 bEndpointAddress;
1791 unsigned long flags;
1792 int enable = 1;
1793 int ret;
1794 int val;
1795
1796 priv_ep = ep_to_cdns3_ep(ep);
1797 priv_dev = priv_ep->cdns3_dev;
1798
1799 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
1800 dev_dbg(priv_dev->dev, "usbss: invalid parameters\n");
1801 return -EINVAL;
1802 }
1803
1804 if (!desc->wMaxPacketSize) {
1805 dev_err(priv_dev->dev, "usbss: missing wMaxPacketSize\n");
1806 return -EINVAL;
1807 }
1808
1809 if (WARN_ON(priv_ep->flags & EP_ENABLED))
1810 return 0;
1811
1812 spin_lock_irqsave(&priv_dev->lock, flags);
1813
1814 priv_ep->endpoint.desc = desc;
1815 priv_ep->type = usb_endpoint_type(desc);
1816 priv_ep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0;
1817
1818 if (priv_ep->interval > ISO_MAX_INTERVAL &&
1819 priv_ep->type == USB_ENDPOINT_XFER_ISOC) {
1820 dev_err(priv_dev->dev, "Driver is limited to %d period\n",
1821 ISO_MAX_INTERVAL);
1822
1823 ret = -EINVAL;
1824 goto exit;
1825 }
1826
1827 ret = cdns3_allocate_trb_pool(priv_ep);
1828
1829 if (ret)
1830 goto exit;
1831
1832 bEndpointAddress = priv_ep->num | priv_ep->dir;
1833 cdns3_select_ep(priv_dev, bEndpointAddress);
1834
1835 trace_cdns3_gadget_ep_enable(priv_ep);
1836
1837 writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
1838
1839 ret = readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
1840 !(val & (EP_CMD_CSTALL | EP_CMD_EPRST)),
1841 1000);
1842
1843 if (unlikely(ret)) {
1844 cdns3_free_trb_pool(priv_ep);
1845 ret = -EINVAL;
1846 goto exit;
1847 }
1848
1849 /* enable interrupt for selected endpoint */
1850 cdns3_set_register_bit(&priv_dev->regs->ep_ien,
1851 BIT(cdns3_ep_addr_to_index(bEndpointAddress)));
1852
1853 if (priv_dev->dev_ver < DEV_VER_V2)
1854 cdns3_wa2_enable_detection(priv_dev, priv_ep, reg);
1855
1856 writel(reg, &priv_dev->regs->ep_sts_en);
1857
1858 /*
1859 * For some versions of controller at some point during ISO OUT traffic
1860 * DMA reads Transfer Ring for the EP which has never got doorbell.
1861 * This issue was detected only on simulation, but to avoid this issue
1862 * driver add protection against it. To fix it driver enable ISO OUT
1863 * endpoint before setting DRBL. This special treatment of ISO OUT
1864 * endpoints are recommended by controller specification.
1865 */
1866 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir)
1867 enable = 0;
1868
1869 if (enable)
1870 cdns3_set_register_bit(&priv_dev->regs->ep_cfg, EP_CFG_ENABLE);
1871
1872 ep->desc = desc;
1873 priv_ep->flags &= ~(EP_PENDING_REQUEST | EP_STALLED | EP_STALL_PENDING |
1874 EP_QUIRK_ISO_OUT_EN | EP_QUIRK_EXTRA_BUF_EN);
1875 priv_ep->flags |= EP_ENABLED | EP_UPDATE_EP_TRBADDR;
1876 priv_ep->wa1_set = 0;
1877 priv_ep->enqueue = 0;
1878 priv_ep->dequeue = 0;
1879 reg = readl(&priv_dev->regs->ep_sts);
1880 priv_ep->pcs = !!EP_STS_CCS(reg);
1881 priv_ep->ccs = !!EP_STS_CCS(reg);
1882 /* one TRB is reserved for link TRB used in DMULT mode*/
1883 priv_ep->free_trbs = priv_ep->num_trbs - 1;
1884exit:
1885 spin_unlock_irqrestore(&priv_dev->lock, flags);
1886
1887 return ret;
1888}
1889
1890/**
1891 * cdns3_gadget_ep_disable Disable endpoint
1892 * @ep: endpoint object
1893 *
1894 * Returns 0 on success, error code elsewhere
1895 */
1896static int cdns3_gadget_ep_disable(struct usb_ep *ep)
1897{
1898 struct cdns3_endpoint *priv_ep;
1899 struct cdns3_request *priv_req;
1900 struct cdns3_device *priv_dev;
1901 struct usb_request *request;
1902 unsigned long flags;
1903 int ret = 0;
1904 u32 ep_cfg;
1905 int val;
1906
1907 if (!ep) {
1908 pr_err("usbss: invalid parameters\n");
1909 return -EINVAL;
1910 }
1911
1912 priv_ep = ep_to_cdns3_ep(ep);
1913 priv_dev = priv_ep->cdns3_dev;
1914
1915 if (WARN_ON(!(priv_ep->flags & EP_ENABLED)))
1916 return 0;
1917
1918 spin_lock_irqsave(&priv_dev->lock, flags);
1919
1920 trace_cdns3_gadget_ep_disable(priv_ep);
1921
1922 cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress);
1923
1924 ep_cfg = readl(&priv_dev->regs->ep_cfg);
1925 ep_cfg &= ~EP_CFG_ENABLE;
1926 writel(ep_cfg, &priv_dev->regs->ep_cfg);
1927
1928 /**
1929 * Driver needs some time before resetting endpoint.
1930 * It need waits for clearing DBUSY bit or for timeout expired.
1931 * 10us is enough time for controller to stop transfer.
1932 */
1933 readl_poll_timeout_atomic(&priv_dev->regs->ep_sts, val,
1934 !(val & EP_STS_DBUSY), 10);
1935 writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
1936
1937 readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
1938 !(val & (EP_CMD_CSTALL | EP_CMD_EPRST)),
1939 1000);
1940 if (unlikely(ret))
1941 dev_err(priv_dev->dev, "Timeout: %s resetting failed.\n",
1942 priv_ep->name);
1943
1944 while (!list_empty(&priv_ep->pending_req_list)) {
1945 request = cdns3_next_request(&priv_ep->pending_req_list);
1946
1947 cdns3_gadget_giveback(priv_ep, to_cdns3_request(request),
1948 -ESHUTDOWN);
1949 }
1950
1951 while (!list_empty(&priv_ep->wa2_descmiss_req_list)) {
1952 priv_req = cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list);
1953
1954 kfree(priv_req->request.buf);
1955 cdns3_gadget_ep_free_request(&priv_ep->endpoint,
1956 &priv_req->request);
1957 list_del_init(&priv_req->list);
1958 --priv_ep->wa2_counter;
1959 }
1960
1961 while (!list_empty(&priv_ep->deferred_req_list)) {
1962 request = cdns3_next_request(&priv_ep->deferred_req_list);
1963
1964 cdns3_gadget_giveback(priv_ep, to_cdns3_request(request),
1965 -ESHUTDOWN);
1966 }
1967
1968 priv_ep->descmis_req = NULL;
1969
1970 ep->desc = NULL;
1971 priv_ep->flags &= ~EP_ENABLED;
1972
1973 spin_unlock_irqrestore(&priv_dev->lock, flags);
1974
1975 return ret;
1976}
1977
1978/**
1979 * cdns3_gadget_ep_queue Transfer data on endpoint
1980 * @ep: endpoint object
1981 * @request: request object
1982 * @gfp_flags: gfp flags
1983 *
1984 * Returns 0 on success, error code elsewhere
1985 */
1986static int __cdns3_gadget_ep_queue(struct usb_ep *ep,
1987 struct usb_request *request,
1988 gfp_t gfp_flags)
1989{
1990 struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
1991 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
1992 struct cdns3_request *priv_req;
1993 int ret = 0;
1994
1995 request->actual = 0;
1996 request->status = -EINPROGRESS;
1997 priv_req = to_cdns3_request(request);
1998 trace_cdns3_ep_queue(priv_req);
1999
2000 if (priv_dev->dev_ver < DEV_VER_V2) {
2001 ret = cdns3_wa2_gadget_ep_queue(priv_dev, priv_ep,
2002 priv_req);
2003
2004 if (ret == EINPROGRESS)
2005 return 0;
2006 }
2007
2008 ret = cdns3_prepare_aligned_request_buf(priv_req);
2009 if (ret < 0)
2010 return ret;
2011
2012 ret = usb_gadget_map_request(&priv_dev->gadget, request,
2013 usb_endpoint_dir_in(ep->desc));
2014 if (ret)
2015 return ret;
2016
2017 list_add_tail(&request->list, &priv_ep->deferred_req_list);
2018
2019 /*
2020 * If hardware endpoint configuration has not been set yet then
2021 * just queue request in deferred list. Transfer will be started in
2022 * cdns3_set_hw_configuration.
2023 */
2024 if (priv_dev->hw_configured_flag && !(priv_ep->flags & EP_STALLED) &&
2025 !(priv_ep->flags & EP_STALL_PENDING))
2026 cdns3_start_all_request(priv_dev, priv_ep);
2027
2028 return 0;
2029}
2030
2031static int cdns3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
2032 gfp_t gfp_flags)
2033{
2034 struct usb_request *zlp_request;
2035 struct cdns3_endpoint *priv_ep;
2036 struct cdns3_device *priv_dev;
2037 unsigned long flags;
2038 int ret;
2039
2040 if (!request || !ep)
2041 return -EINVAL;
2042
2043 priv_ep = ep_to_cdns3_ep(ep);
2044 priv_dev = priv_ep->cdns3_dev;
2045
2046 spin_lock_irqsave(&priv_dev->lock, flags);
2047
2048 ret = __cdns3_gadget_ep_queue(ep, request, gfp_flags);
2049
2050 if (ret == 0 && request->zero && request->length &&
2051 (request->length % ep->maxpacket == 0)) {
2052 struct cdns3_request *priv_req;
2053
2054 zlp_request = cdns3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
2055 zlp_request->buf = priv_dev->zlp_buf;
2056 zlp_request->length = 0;
2057
2058 priv_req = to_cdns3_request(zlp_request);
2059 priv_req->flags |= REQUEST_ZLP;
2060
2061 dev_dbg(priv_dev->dev, "Queuing ZLP for endpoint: %s\n",
2062 priv_ep->name);
2063 ret = __cdns3_gadget_ep_queue(ep, zlp_request, gfp_flags);
2064 }
2065
2066 spin_unlock_irqrestore(&priv_dev->lock, flags);
2067 return ret;
2068}
2069
2070/**
2071 * cdns3_gadget_ep_dequeue Remove request from transfer queue
2072 * @ep: endpoint object associated with request
2073 * @request: request object
2074 *
2075 * Returns 0 on success, error code elsewhere
2076 */
2077int cdns3_gadget_ep_dequeue(struct usb_ep *ep,
2078 struct usb_request *request)
2079{
2080 struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
2081 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
2082 struct usb_request *req, *req_temp;
2083 struct cdns3_request *priv_req;
2084 struct cdns3_trb *link_trb;
2085 unsigned long flags;
2086 int ret = 0;
2087
2088 if (!ep || !request || !ep->desc)
2089 return -EINVAL;
2090
2091 spin_lock_irqsave(&priv_dev->lock, flags);
2092
2093 priv_req = to_cdns3_request(request);
2094
2095 trace_cdns3_ep_dequeue(priv_req);
2096
2097 cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress);
2098
2099 list_for_each_entry_safe(req, req_temp, &priv_ep->pending_req_list,
2100 list) {
2101 if (request == req)
2102 goto found;
2103 }
2104
2105 list_for_each_entry_safe(req, req_temp, &priv_ep->deferred_req_list,
2106 list) {
2107 if (request == req)
2108 goto found;
2109 }
2110
2111 goto not_found;
2112
2113found:
2114
2115 if (priv_ep->wa1_trb == priv_req->trb)
2116 cdns3_wa1_restore_cycle_bit(priv_ep);
2117
2118 link_trb = priv_req->trb;
2119 cdns3_move_deq_to_next_trb(priv_req);
2120 cdns3_gadget_giveback(priv_ep, priv_req, -ECONNRESET);
2121
2122 /* Update ring */
2123 request = cdns3_next_request(&priv_ep->deferred_req_list);
2124 if (request) {
2125 priv_req = to_cdns3_request(request);
2126
2127 link_trb->buffer = TRB_BUFFER(priv_ep->trb_pool_dma +
2128 (priv_req->start_trb * TRB_SIZE));
2129 link_trb->control = (link_trb->control & TRB_CYCLE) |
2130 TRB_TYPE(TRB_LINK) | TRB_CHAIN | TRB_TOGGLE;
2131 } else {
2132 priv_ep->flags |= EP_UPDATE_EP_TRBADDR;
2133 }
2134
2135not_found:
2136 spin_unlock_irqrestore(&priv_dev->lock, flags);
2137 return ret;
2138}
2139
2140/**
2141 * __cdns3_gadget_ep_set_halt Sets stall on selected endpoint
2142 * Should be called after acquiring spin_lock and selecting ep
2143 * @ep: endpoint object to set stall on.
2144 */
2145void __cdns3_gadget_ep_set_halt(struct cdns3_endpoint *priv_ep)
2146{
2147 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
2148
2149 trace_cdns3_halt(priv_ep, 1, 0);
2150
2151 if (!(priv_ep->flags & EP_STALLED)) {
2152 u32 ep_sts_reg = readl(&priv_dev->regs->ep_sts);
2153
2154 if (!(ep_sts_reg & EP_STS_DBUSY))
2155 cdns3_ep_stall_flush(priv_ep);
2156 else
2157 priv_ep->flags |= EP_STALL_PENDING;
2158 }
2159}
2160
2161/**
2162 * __cdns3_gadget_ep_clear_halt Clears stall on selected endpoint
2163 * Should be called after acquiring spin_lock and selecting ep
2164 * @ep: endpoint object to clear stall on
2165 */
2166int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep)
2167{
2168 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
2169 struct usb_request *request;
2170 int ret = 0;
2171 int val;
2172
2173 trace_cdns3_halt(priv_ep, 0, 0);
2174
2175 writel(EP_CMD_CSTALL | EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
2176
2177 /* wait for EPRST cleared */
2178 readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
2179 !(val & EP_CMD_EPRST), 100);
2180 if (ret)
2181 return -EINVAL;
2182
2183 priv_ep->flags &= ~(EP_STALLED | EP_STALL_PENDING);
2184
2185 request = cdns3_next_request(&priv_ep->pending_req_list);
2186
2187 if (request)
2188 cdns3_rearm_transfer(priv_ep, 1);
2189
2190 cdns3_start_all_request(priv_dev, priv_ep);
2191 return ret;
2192}
2193
2194/**
2195 * cdns3_gadget_ep_set_halt Sets/clears stall on selected endpoint
2196 * @ep: endpoint object to set/clear stall on
2197 * @value: 1 for set stall, 0 for clear stall
2198 *
2199 * Returns 0 on success, error code elsewhere
2200 */
2201int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value)
2202{
2203 struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
2204 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
2205 unsigned long flags;
2206 int ret = 0;
2207
2208 if (!(priv_ep->flags & EP_ENABLED))
2209 return -EPERM;
2210
2211 spin_lock_irqsave(&priv_dev->lock, flags);
2212
2213 cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress);
2214
2215 if (!value) {
2216 priv_ep->flags &= ~EP_WEDGE;
2217 ret = __cdns3_gadget_ep_clear_halt(priv_ep);
2218 } else {
2219 __cdns3_gadget_ep_set_halt(priv_ep);
2220 }
2221
2222 spin_unlock_irqrestore(&priv_dev->lock, flags);
2223
2224 return ret;
2225}
2226
2227extern const struct usb_ep_ops cdns3_gadget_ep0_ops;
2228
2229static const struct usb_ep_ops cdns3_gadget_ep_ops = {
2230 .enable = cdns3_gadget_ep_enable,
2231 .disable = cdns3_gadget_ep_disable,
2232 .alloc_request = cdns3_gadget_ep_alloc_request,
2233 .free_request = cdns3_gadget_ep_free_request,
2234 .queue = cdns3_gadget_ep_queue,
2235 .dequeue = cdns3_gadget_ep_dequeue,
2236 .set_halt = cdns3_gadget_ep_set_halt,
2237 .set_wedge = cdns3_gadget_ep_set_wedge,
2238};
2239
2240/**
2241 * cdns3_gadget_get_frame Returns number of actual ITP frame
2242 * @gadget: gadget object
2243 *
2244 * Returns number of actual ITP frame
2245 */
2246static int cdns3_gadget_get_frame(struct usb_gadget *gadget)
2247{
2248 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
2249
2250 return readl(&priv_dev->regs->usb_itpn);
2251}
2252
2253int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev)
2254{
2255 enum usb_device_speed speed;
2256
2257 speed = cdns3_get_speed(priv_dev);
2258
2259 if (speed >= USB_SPEED_SUPER)
2260 return 0;
2261
2262 /* Start driving resume signaling to indicate remote wakeup. */
2263 writel(USB_CONF_LGO_L0, &priv_dev->regs->usb_conf);
2264
2265 return 0;
2266}
2267
2268static int cdns3_gadget_wakeup(struct usb_gadget *gadget)
2269{
2270 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
2271 unsigned long flags;
2272 int ret = 0;
2273
2274 spin_lock_irqsave(&priv_dev->lock, flags);
2275 ret = __cdns3_gadget_wakeup(priv_dev);
2276 spin_unlock_irqrestore(&priv_dev->lock, flags);
2277 return ret;
2278}
2279
2280static int cdns3_gadget_set_selfpowered(struct usb_gadget *gadget,
2281 int is_selfpowered)
2282{
2283 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
2284 unsigned long flags;
2285
2286 spin_lock_irqsave(&priv_dev->lock, flags);
2287 priv_dev->is_selfpowered = !!is_selfpowered;
2288 spin_unlock_irqrestore(&priv_dev->lock, flags);
2289 return 0;
2290}
2291
2292static int cdns3_gadget_pullup(struct usb_gadget *gadget, int is_on)
2293{
2294 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
2295
2296 if (is_on)
2297 writel(USB_CONF_DEVEN, &priv_dev->regs->usb_conf);
2298 else
2299 writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf);
2300
2301 return 0;
2302}
2303
2304static void cdns3_gadget_config(struct cdns3_device *priv_dev)
2305{
2306 struct cdns3_usb_regs __iomem *regs = priv_dev->regs;
2307 u32 reg;
2308
2309 cdns3_ep0_config(priv_dev);
2310
2311 /* enable interrupts for endpoint 0 (in and out) */
2312 writel(EP_IEN_EP_OUT0 | EP_IEN_EP_IN0, &regs->ep_ien);
2313
2314 /*
2315 * Driver needs to modify LFPS minimal U1 Exit time for DEV_VER_TI_V1
2316 * revision of controller.
2317 */
2318 if (priv_dev->dev_ver == DEV_VER_TI_V1) {
2319 reg = readl(&regs->dbg_link1);
2320
2321 reg &= ~DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK;
2322 reg |= DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(0x55) |
2323 DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET;
2324 writel(reg, &regs->dbg_link1);
2325 }
2326
2327 /*
2328 * By default some platforms has set protected access to memory.
2329 * This cause problem with cache, so driver restore non-secure
2330 * access to memory.
2331 */
2332 reg = readl(&regs->dma_axi_ctrl);
2333 reg |= DMA_AXI_CTRL_MARPROT(DMA_AXI_CTRL_NON_SECURE) |
2334 DMA_AXI_CTRL_MAWPROT(DMA_AXI_CTRL_NON_SECURE);
2335 writel(reg, &regs->dma_axi_ctrl);
2336
2337 /* enable generic interrupt*/
2338 writel(USB_IEN_INIT, &regs->usb_ien);
2339 writel(USB_CONF_CLK2OFFDS | USB_CONF_L1DS, &regs->usb_conf);
2340
Aswath Govindraju83eed2c2024-04-24 13:09:11 +05302341 /* Set the Fast access bit */
2342 writel(PUSB_PWR_FST_REG_ACCESS, &priv_dev->regs->usb_pwr);
2343
Vignesh Raghavendra7e91f6c2019-10-01 17:26:33 +05302344 cdns3_configure_dmult(priv_dev, NULL);
2345
2346 cdns3_gadget_pullup(&priv_dev->gadget, 1);
2347}
2348
2349/**
2350 * cdns3_gadget_udc_start Gadget start
2351 * @gadget: gadget object
2352 * @driver: driver which operates on this gadget
2353 *
2354 * Returns 0 on success, error code elsewhere
2355 */
2356static int cdns3_gadget_udc_start(struct usb_gadget *gadget,
2357 struct usb_gadget_driver *driver)
2358{
2359 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
2360 unsigned long flags;
2361
2362 spin_lock_irqsave(&priv_dev->lock, flags);
2363 priv_dev->gadget_driver = driver;
Ravi Gunasekaran15cba562023-07-19 14:29:08 +05302364 cdns3_gadget_udc_set_speed(gadget, gadget->max_speed);
Vignesh Raghavendra7e91f6c2019-10-01 17:26:33 +05302365 cdns3_gadget_config(priv_dev);
2366 spin_unlock_irqrestore(&priv_dev->lock, flags);
2367 return 0;
2368}
2369
2370/**
2371 * cdns3_gadget_udc_stop Stops gadget
2372 * @gadget: gadget object
2373 *
2374 * Returns 0
2375 */
2376static int cdns3_gadget_udc_stop(struct usb_gadget *gadget)
2377{
2378 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
2379 struct cdns3_endpoint *priv_ep;
2380 u32 bEndpointAddress;
2381 struct usb_ep *ep;
2382 int ret = 0;
2383 int val;
2384
2385 priv_dev->gadget_driver = NULL;
2386
2387 priv_dev->onchip_used_size = 0;
2388 priv_dev->out_mem_is_allocated = 0;
2389 priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
2390
2391 list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) {
2392 priv_ep = ep_to_cdns3_ep(ep);
2393 bEndpointAddress = priv_ep->num | priv_ep->dir;
2394 cdns3_select_ep(priv_dev, bEndpointAddress);
2395 writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
2396 readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
2397 !(val & EP_CMD_EPRST), 100);
2398 }
2399
2400 /* disable interrupt for device */
2401 writel(0, &priv_dev->regs->usb_ien);
Aswath Govindraju83eed2c2024-04-24 13:09:11 +05302402 writel(0, &priv_dev->regs->usb_pwr);
Vignesh Raghavendra7e91f6c2019-10-01 17:26:33 +05302403 writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf);
2404
2405 return ret;
2406}
2407
Vignesh Raghavendra927c22b2019-10-01 17:26:34 +05302408static void cdns3_gadget_udc_set_speed(struct usb_gadget *gadget,
2409 enum usb_device_speed speed)
2410{
2411 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
2412
2413 switch (speed) {
2414 case USB_SPEED_FULL:
2415 writel(USB_CONF_SFORCE_FS, &priv_dev->regs->usb_conf);
2416 writel(USB_CONF_USB3DIS, &priv_dev->regs->usb_conf);
2417 break;
2418 case USB_SPEED_HIGH:
2419 writel(USB_CONF_USB3DIS, &priv_dev->regs->usb_conf);
2420 break;
2421 case USB_SPEED_SUPER:
2422 break;
2423 default:
Sean Andersondf8395a2020-09-15 10:45:14 -04002424 dev_err(priv_dev->dev, "invalid speed parameter %d\n", speed);
Vignesh Raghavendra927c22b2019-10-01 17:26:34 +05302425 }
2426
2427 priv_dev->gadget.speed = speed;
2428}
2429
Vignesh Raghavendra7e91f6c2019-10-01 17:26:33 +05302430static const struct usb_gadget_ops cdns3_gadget_ops = {
2431 .get_frame = cdns3_gadget_get_frame,
2432 .wakeup = cdns3_gadget_wakeup,
2433 .set_selfpowered = cdns3_gadget_set_selfpowered,
2434 .pullup = cdns3_gadget_pullup,
2435 .udc_start = cdns3_gadget_udc_start,
2436 .udc_stop = cdns3_gadget_udc_stop,
2437 .match_ep = cdns3_gadget_match_ep,
Vignesh Raghavendra927c22b2019-10-01 17:26:34 +05302438 .udc_set_speed = cdns3_gadget_udc_set_speed,
Vignesh Raghavendra7e91f6c2019-10-01 17:26:33 +05302439};
2440
2441static void cdns3_free_all_eps(struct cdns3_device *priv_dev)
2442{
2443 int i;
2444
2445 /* ep0 OUT point to ep0 IN. */
2446 priv_dev->eps[16] = NULL;
2447
2448 for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++)
2449 if (priv_dev->eps[i]) {
2450 cdns3_free_trb_pool(priv_dev->eps[i]);
2451 devm_kfree(priv_dev->dev, priv_dev->eps[i]);
2452 }
2453}
2454
2455/**
2456 * cdns3_init_eps Initializes software endpoints of gadget
2457 * @cdns3: extended gadget object
2458 *
2459 * Returns 0 on success, error code elsewhere
2460 */
2461static int cdns3_init_eps(struct cdns3_device *priv_dev)
2462{
2463 u32 ep_enabled_reg, iso_ep_reg;
2464 struct cdns3_endpoint *priv_ep;
2465 int ep_dir, ep_number;
2466 u32 ep_mask;
2467 int ret = 0;
2468 int i;
2469
2470 /* Read it from USB_CAP3 to USB_CAP5 */
2471 ep_enabled_reg = readl(&priv_dev->regs->usb_cap3);
2472 iso_ep_reg = readl(&priv_dev->regs->usb_cap4);
2473
2474 dev_dbg(priv_dev->dev, "Initializing non-zero endpoints\n");
2475
2476 for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++) {
2477 ep_dir = i >> 4; /* i div 16 */
2478 ep_number = i & 0xF; /* i % 16 */
2479 ep_mask = BIT(i);
2480
2481 if (!(ep_enabled_reg & ep_mask))
2482 continue;
2483
2484 if (ep_dir && !ep_number) {
2485 priv_dev->eps[i] = priv_dev->eps[0];
2486 continue;
2487 }
2488
2489 priv_ep = devm_kzalloc(priv_dev->dev, sizeof(*priv_ep),
2490 GFP_KERNEL);
2491 if (!priv_ep) {
2492 ret = -ENOMEM;
2493 goto err;
2494 }
2495
2496 /* set parent of endpoint object */
2497 priv_ep->cdns3_dev = priv_dev;
2498 priv_dev->eps[i] = priv_ep;
2499 priv_ep->num = ep_number;
2500 priv_ep->dir = ep_dir ? USB_DIR_IN : USB_DIR_OUT;
2501
2502 if (!ep_number) {
2503 ret = cdns3_init_ep0(priv_dev, priv_ep);
2504 if (ret) {
2505 dev_err(priv_dev->dev, "Failed to init ep0\n");
2506 goto err;
2507 }
2508 } else {
2509 snprintf(priv_ep->name, sizeof(priv_ep->name), "ep%d%s",
2510 ep_number, !!ep_dir ? "in" : "out");
2511 priv_ep->endpoint.name = priv_ep->name;
2512
2513 usb_ep_set_maxpacket_limit(&priv_ep->endpoint,
2514 CDNS3_EP_MAX_PACKET_LIMIT);
2515 priv_ep->endpoint.max_streams = CDNS3_EP_MAX_STREAMS;
2516 priv_ep->endpoint.ops = &cdns3_gadget_ep_ops;
2517 if (ep_dir)
2518 priv_ep->endpoint.caps.dir_in = 1;
2519 else
2520 priv_ep->endpoint.caps.dir_out = 1;
2521
2522 if (iso_ep_reg & ep_mask)
2523 priv_ep->endpoint.caps.type_iso = 1;
2524
2525 priv_ep->endpoint.caps.type_bulk = 1;
2526 priv_ep->endpoint.caps.type_int = 1;
2527
2528 list_add_tail(&priv_ep->endpoint.ep_list,
2529 &priv_dev->gadget.ep_list);
2530 }
2531
2532 priv_ep->flags = 0;
2533
2534 dev_info(priv_dev->dev, "Initialized %s support: %s %s\n",
2535 priv_ep->name,
2536 priv_ep->endpoint.caps.type_bulk ? "BULK, INT" : "",
2537 priv_ep->endpoint.caps.type_iso ? "ISO" : "");
2538
2539 INIT_LIST_HEAD(&priv_ep->pending_req_list);
2540 INIT_LIST_HEAD(&priv_ep->deferred_req_list);
2541 INIT_LIST_HEAD(&priv_ep->wa2_descmiss_req_list);
2542 }
2543
2544 return 0;
2545err:
2546 cdns3_free_all_eps(priv_dev);
2547 return -ENOMEM;
2548}
2549
2550void cdns3_gadget_exit(struct cdns3 *cdns)
2551{
2552 struct cdns3_device *priv_dev;
2553
2554 priv_dev = cdns->gadget_dev;
2555
2556 usb_del_gadget_udc(&priv_dev->gadget);
2557
2558 cdns3_free_all_eps(priv_dev);
2559
2560 while (!list_empty(&priv_dev->aligned_buf_list)) {
2561 struct cdns3_aligned_buf *buf;
2562
2563 buf = cdns3_next_align_buf(&priv_dev->aligned_buf_list);
2564 dma_free_coherent(buf->buf);
2565
2566 list_del(&buf->list);
2567 kfree(buf);
2568 }
2569
2570 dma_free_coherent(priv_dev->setup_buf);
2571
2572 kfree(priv_dev->zlp_buf);
2573 kfree(priv_dev);
2574 cdns->gadget_dev = NULL;
2575 cdns3_drd_switch_gadget(cdns, 0);
2576}
2577
2578static int cdns3_gadget_start(struct cdns3 *cdns)
2579{
2580 struct cdns3_device *priv_dev;
2581 u32 max_speed;
2582 int ret;
2583
2584 priv_dev = kzalloc(sizeof(*priv_dev), GFP_KERNEL);
2585 if (!priv_dev)
2586 return -ENOMEM;
2587
2588 cdns->gadget_dev = priv_dev;
2589 priv_dev->sysdev = cdns->dev;
2590 priv_dev->dev = cdns->dev;
2591 priv_dev->regs = cdns->dev_regs;
2592
2593 dev_read_u32(priv_dev->dev, "cdns,on-chip-buff-size",
2594 &priv_dev->onchip_buffers);
2595
2596 if (priv_dev->onchip_buffers <= 0) {
2597 u32 reg = readl(&priv_dev->regs->usb_cap2);
2598
2599 priv_dev->onchip_buffers = USB_CAP2_ACTUAL_MEM_SIZE(reg);
2600 }
2601
2602 if (!priv_dev->onchip_buffers)
2603 priv_dev->onchip_buffers = 256;
2604
Kever Yangac28e592020-03-04 08:59:50 +08002605 max_speed = usb_get_maximum_speed(dev_ofnode(cdns->dev));
Vignesh Raghavendra7e91f6c2019-10-01 17:26:33 +05302606
2607 /* Check the maximum_speed parameter */
2608 switch (max_speed) {
2609 case USB_SPEED_FULL:
Vignesh Raghavendra927c22b2019-10-01 17:26:34 +05302610 /* fall through */
Vignesh Raghavendra7e91f6c2019-10-01 17:26:33 +05302611 case USB_SPEED_HIGH:
Vignesh Raghavendra927c22b2019-10-01 17:26:34 +05302612 /* fall through */
Vignesh Raghavendra7e91f6c2019-10-01 17:26:33 +05302613 case USB_SPEED_SUPER:
2614 break;
2615 default:
2616 dev_err(cdns->dev, "invalid maximum_speed parameter %d\n",
2617 max_speed);
2618 /* fall through */
2619 case USB_SPEED_UNKNOWN:
2620 /* default to superspeed */
2621 max_speed = USB_SPEED_SUPER;
2622 break;
2623 }
2624
2625 /* fill gadget fields */
2626 priv_dev->gadget.max_speed = max_speed;
2627 priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
2628 priv_dev->gadget.ops = &cdns3_gadget_ops;
2629 priv_dev->gadget.name = "cdns3-gadget";
2630#ifndef __UBOOT__
2631 priv_dev->gadget.name = "usb-ss-gadget";
2632 priv_dev->gadget.sg_supported = 1;
2633 priv_dev->gadget.quirk_avoids_skb_reserve = 1;
2634#endif
2635
2636 spin_lock_init(&priv_dev->lock);
2637 INIT_WORK(&priv_dev->pending_status_wq,
2638 cdns3_pending_setup_status_handler);
2639
2640 /* initialize endpoint container */
2641 INIT_LIST_HEAD(&priv_dev->gadget.ep_list);
2642 INIT_LIST_HEAD(&priv_dev->aligned_buf_list);
2643
2644 ret = cdns3_init_eps(priv_dev);
2645 if (ret) {
2646 dev_err(priv_dev->dev, "Failed to create endpoints\n");
2647 goto err1;
2648 }
2649
2650 /* allocate memory for setup packet buffer */
2651 priv_dev->setup_buf =
2652 dma_alloc_coherent(8, (unsigned long *)&priv_dev->setup_dma);
2653 if (!priv_dev->setup_buf) {
2654 ret = -ENOMEM;
2655 goto err2;
2656 }
2657
2658 priv_dev->dev_ver = readl(&priv_dev->regs->usb_cap6);
2659
2660 dev_dbg(priv_dev->dev, "Device Controller version: %08x\n",
2661 readl(&priv_dev->regs->usb_cap6));
2662 dev_dbg(priv_dev->dev, "USB Capabilities:: %08x\n",
2663 readl(&priv_dev->regs->usb_cap1));
2664 dev_dbg(priv_dev->dev, "On-Chip memory cnfiguration: %08x\n",
2665 readl(&priv_dev->regs->usb_cap2));
2666
2667 priv_dev->dev_ver = GET_DEV_BASE_VERSION(priv_dev->dev_ver);
2668
2669 priv_dev->zlp_buf = kzalloc(CDNS3_EP_ZLP_BUF_SIZE, GFP_KERNEL);
2670 if (!priv_dev->zlp_buf) {
2671 ret = -ENOMEM;
2672 goto err3;
2673 }
2674
2675 /* add USB gadget device */
2676 ret = usb_add_gadget_udc((struct device *)priv_dev->dev,
2677 &priv_dev->gadget);
2678 if (ret < 0) {
2679 dev_err(priv_dev->dev,
2680 "Failed to register USB device controller\n");
2681 goto err4;
2682 }
2683
2684 return 0;
2685err4:
2686 kfree(priv_dev->zlp_buf);
2687err3:
2688 dma_free_coherent(priv_dev->setup_buf);
2689err2:
2690 cdns3_free_all_eps(priv_dev);
2691err1:
2692 cdns->gadget_dev = NULL;
2693 return ret;
2694}
2695
2696static int __cdns3_gadget_init(struct cdns3 *cdns)
2697{
2698 int ret = 0;
2699
2700 cdns3_drd_switch_gadget(cdns, 1);
2701
2702 ret = cdns3_gadget_start(cdns);
2703 if (ret)
2704 return ret;
2705
2706 return 0;
2707}
2708
2709static int cdns3_gadget_suspend(struct cdns3 *cdns, bool do_wakeup)
2710{
2711 struct cdns3_device *priv_dev = cdns->gadget_dev;
2712
2713 cdns3_disconnect_gadget(priv_dev);
2714
2715 priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
2716 usb_gadget_set_state(&priv_dev->gadget, USB_STATE_NOTATTACHED);
2717 cdns3_hw_reset_eps_config(priv_dev);
2718
2719 /* disable interrupt for device */
2720 writel(0, &priv_dev->regs->usb_ien);
2721
2722 cdns3_gadget_pullup(&priv_dev->gadget, 0);
2723
2724 return 0;
2725}
2726
2727static int cdns3_gadget_resume(struct cdns3 *cdns, bool hibernated)
2728{
2729 struct cdns3_device *priv_dev = cdns->gadget_dev;
2730
2731 if (!priv_dev->gadget_driver)
2732 return 0;
2733
2734 cdns3_gadget_config(priv_dev);
2735
2736 return 0;
2737}
2738
2739/**
2740 * cdns3_gadget_init - initialize device structure
2741 *
2742 * cdns: cdns3 instance
2743 *
2744 * This function initializes the gadget.
2745 */
2746int cdns3_gadget_init(struct cdns3 *cdns)
2747{
2748 struct cdns3_role_driver *rdrv;
2749
2750 rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL);
2751 if (!rdrv)
2752 return -ENOMEM;
2753
2754 rdrv->start = __cdns3_gadget_init;
2755 rdrv->stop = cdns3_gadget_exit;
2756 rdrv->suspend = cdns3_gadget_suspend;
2757 rdrv->resume = cdns3_gadget_resume;
2758 rdrv->state = CDNS3_ROLE_STATE_INACTIVE;
2759 rdrv->name = "gadget";
2760 cdns->roles[USB_ROLE_DEVICE] = rdrv;
2761
2762 return 0;
2763}
2764
2765/**
2766 * cdns3_gadget_uboot_handle_interrupt - handle cdns3 gadget interrupt
2767 * @cdns: pointer to struct cdns3
2768 *
2769 * Handles ep0 and gadget interrupt
2770 */
Marek Vasut356542d2024-06-14 02:51:17 +02002771void cdns3_gadget_uboot_handle_interrupt(struct cdns3 *cdns)
Vignesh Raghavendra7e91f6c2019-10-01 17:26:33 +05302772{
2773 int ret = cdns3_device_irq_handler(0, cdns);
2774
2775 if (ret == IRQ_WAKE_THREAD)
2776 cdns3_device_thread_irq_handler(0, cdns);
2777}