blob: 187468e24e17fd102e169ee056b5534bce9c7f38 [file] [log] [blame]
Chandan Nath5289e832011-10-14 02:58:26 +00001/*
2 * mux.c
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
Tom Rinidb7dd812012-07-31 10:50:01 -070016#include <common.h>
17#include <asm/arch/sys_proto.h>
Chandan Nath5289e832011-10-14 02:58:26 +000018#include <asm/arch/hardware.h>
Peter Korsgaard7f26a5a2012-10-18 01:21:11 +000019#include <asm/arch/mux.h>
Chandan Nath5289e832011-10-14 02:58:26 +000020#include <asm/io.h>
Tom Rini036fd652012-08-08 09:03:07 -070021#include <i2c.h>
Peter Korsgaarde3634262012-10-18 01:21:09 +000022#include "board.h"
Chandan Nath5289e832011-10-14 02:58:26 +000023
Chandan Nath5289e832011-10-14 02:58:26 +000024static struct module_pin_mux uart0_pin_mux[] = {
25 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
27 {-1},
28};
29
Andrew Bradford6422b702012-10-25 08:21:30 -040030static struct module_pin_mux uart1_pin_mux[] = {
31 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
32 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
33 {-1},
34};
35
36static struct module_pin_mux uart2_pin_mux[] = {
37 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
38 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
39 {-1},
40};
41
42static struct module_pin_mux uart3_pin_mux[] = {
43 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
44 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
45 {-1},
46};
47
48static struct module_pin_mux uart4_pin_mux[] = {
49 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
50 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
51 {-1},
52};
53
54static struct module_pin_mux uart5_pin_mux[] = {
55 {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
56 {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
57 {-1},
58};
59
Chandan Nath876bdd62012-01-09 20:38:58 +000060static struct module_pin_mux mmc0_pin_mux[] = {
61 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
62 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
63 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
64 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
65 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
66 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
67 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
68 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
69 {-1},
70};
Tom Rinidb7dd812012-07-31 10:50:01 -070071
Matthias Fuchsa956bdc2012-11-02 03:35:59 +000072static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
73 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
74 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
75 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
76 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
77 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
78 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
79 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
80 {-1},
81};
82
Tom Rinidb7dd812012-07-31 10:50:01 -070083static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
84 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
85 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
86 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
87 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
88 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
89 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
90 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
91 {-1},
92};
Chandan Nath876bdd62012-01-09 20:38:58 +000093
Tom Rini6bfca502012-08-08 10:32:09 -070094static struct module_pin_mux mmc1_pin_mux[] = {
95 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
96 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
97 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
98 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
99 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
100 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
101 {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
102 {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */
103 {-1},
104};
105
Patil, Rachnab4116ed2012-01-22 23:47:01 +0000106static struct module_pin_mux i2c0_pin_mux[] = {
107 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
108 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
109 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
110 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
111 {-1},
112};
113
Steve Sakomand3decde2012-06-22 07:45:57 +0000114static struct module_pin_mux i2c1_pin_mux[] = {
115 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
116 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
117 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
118 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
119 {-1},
120};
121
Tom Rinia4a99ff2012-08-08 14:35:55 -0700122static struct module_pin_mux spi0_pin_mux[] = {
123 {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
124 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
125 PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
126 {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
127 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
128 PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
129 {-1},
130};
131
Tom Rini65d750b2012-07-31 08:55:01 -0700132static struct module_pin_mux gpio0_7_pin_mux[] = {
133 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
134 {-1},
135};
136
Chandan Nath89017e12012-07-24 12:22:18 +0000137static struct module_pin_mux rgmii1_pin_mux[] = {
138 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
139 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
140 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
141 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
142 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
143 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
144 {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
145 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
146 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
147 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
148 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
149 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
150 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
151 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
152 {-1},
153};
154
155static struct module_pin_mux mii1_pin_mux[] = {
156 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
157 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
158 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
159 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
160 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
161 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
162 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
163 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
164 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
165 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
166 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
167 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
168 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
169 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
170 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
171 {-1},
172};
173
Ilya Yanok70fb65b2012-11-06 13:06:29 +0000174static struct module_pin_mux nand_pin_mux[] = {
175 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
176 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
177 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
178 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
179 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
180 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
181 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
182 {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
183 {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
184 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
185 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
186 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
187 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
188 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
189 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
190 {-1},
191};
192
Steve Kipiszcd8845d2013-07-18 15:13:03 -0400193#if defined(CONFIG_NOR)
194static struct module_pin_mux bone_norcape_pin_mux[] = {
195 {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */
196 {OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A1 */
197 {OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A2 */
198 {OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A3 */
199 {OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A4 */
200 {OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A5 */
201 {OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A6 */
202 {OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A7 */
203 {OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A8 */
204 {OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A9 */
205 {OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A10 */
206 {OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */
207 {OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A12 */
208 {OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A13 */
209 {OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A14 */
210 {OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A15 */
211 {OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A16 */
212 {OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A17 */
213 {OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A18 */
214 {OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A19 */
215 {OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD0 */
216 {OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD1 */
217 {OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD2 */
218 {OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD3 */
219 {OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD4 */
220 {OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD5 */
221 {OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD6 */
222 {OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD7 */
223 {OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD8 */
224 {OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD9 */
225 {OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD10 */
226 {OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD11 */
227 {OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD12 */
228 {OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD13 */
229 {OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD14 */
230 {OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD15 */
231
232 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_CE */
233 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */
234 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */
235 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */
236 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)}, /* NOR_WEN */
237 {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */
238 {-1},
239};
240#endif
241
242
Chandan Nath5289e832011-10-14 02:58:26 +0000243void enable_uart0_pin_mux(void)
244{
245 configure_module_pin_mux(uart0_pin_mux);
246}
Chandan Nath876bdd62012-01-09 20:38:58 +0000247
Andrew Bradford6422b702012-10-25 08:21:30 -0400248void enable_uart1_pin_mux(void)
249{
250 configure_module_pin_mux(uart1_pin_mux);
251}
252
253void enable_uart2_pin_mux(void)
254{
255 configure_module_pin_mux(uart2_pin_mux);
256}
257
258void enable_uart3_pin_mux(void)
259{
260 configure_module_pin_mux(uart3_pin_mux);
261}
262
263void enable_uart4_pin_mux(void)
264{
265 configure_module_pin_mux(uart4_pin_mux);
266}
267
268void enable_uart5_pin_mux(void)
269{
270 configure_module_pin_mux(uart5_pin_mux);
271}
Patil, Rachnab4116ed2012-01-22 23:47:01 +0000272
273void enable_i2c0_pin_mux(void)
274{
275 configure_module_pin_mux(i2c0_pin_mux);
276}
Steve Sakomand3decde2012-06-22 07:45:57 +0000277
Tom Rini036fd652012-08-08 09:03:07 -0700278/*
279 * The AM335x GP EVM, if daughter card(s) are connected, can have 8
280 * different profiles. These profiles determine what peripherals are
281 * valid and need pinmux to be configured.
282 */
283#define PROFILE_NONE 0x0
284#define PROFILE_0 (1 << 0)
285#define PROFILE_1 (1 << 1)
286#define PROFILE_2 (1 << 2)
287#define PROFILE_3 (1 << 3)
288#define PROFILE_4 (1 << 4)
289#define PROFILE_5 (1 << 5)
290#define PROFILE_6 (1 << 6)
291#define PROFILE_7 (1 << 7)
292#define PROFILE_MASK 0x7
293#define PROFILE_ALL 0xFF
294
295/* CPLD registers */
296#define I2C_CPLD_ADDR 0x35
297#define CFG_REG 0x10
298
299static unsigned short detect_daughter_board_profile(void)
300{
301 unsigned short val;
302
303 if (i2c_probe(I2C_CPLD_ADDR))
304 return PROFILE_NONE;
305
306 if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
307 return PROFILE_NONE;
308
309 return (1 << (val & PROFILE_MASK));
310}
311
Tom Rinidb7dd812012-07-31 10:50:01 -0700312void enable_board_pin_mux(struct am335x_baseboard_id *header)
Steve Sakomand3decde2012-06-22 07:45:57 +0000313{
Tom Rini036fd652012-08-08 09:03:07 -0700314 /* Do board-specific muxes. */
Tom Riniace42752013-07-18 15:13:01 -0400315 if (board_is_bone(header)) {
Tom Rinidb7dd812012-07-31 10:50:01 -0700316 /* Beaglebone pinmux */
Tom Rini036fd652012-08-08 09:03:07 -0700317 configure_module_pin_mux(i2c1_pin_mux);
Tom Rinidb7dd812012-07-31 10:50:01 -0700318 configure_module_pin_mux(mii1_pin_mux);
319 configure_module_pin_mux(mmc0_pin_mux);
Tom Rini6bfca502012-08-08 10:32:09 -0700320 configure_module_pin_mux(mmc1_pin_mux);
Steve Kipiszcd8845d2013-07-18 15:13:03 -0400321#if defined(CONFIG_NOR)
322 configure_module_pin_mux(bone_norcape_pin_mux);
323#endif
Tom Riniace42752013-07-18 15:13:01 -0400324 } else if (board_is_gp_evm(header)) {
Tom Rinidb7dd812012-07-31 10:50:01 -0700325 /* General Purpose EVM */
Tom Rini036fd652012-08-08 09:03:07 -0700326 unsigned short profile = detect_daughter_board_profile();
Tom Rinidb7dd812012-07-31 10:50:01 -0700327 configure_module_pin_mux(rgmii1_pin_mux);
328 configure_module_pin_mux(mmc0_pin_mux);
Tom Rini036fd652012-08-08 09:03:07 -0700329 /* In profile #2 i2c1 and spi0 conflict. */
330 if (profile & ~PROFILE_2)
331 configure_module_pin_mux(i2c1_pin_mux);
Ilya Yanok70fb65b2012-11-06 13:06:29 +0000332 /* Profiles 2 & 3 don't have NAND */
333 if (profile & ~(PROFILE_2 | PROFILE_3))
334 configure_module_pin_mux(nand_pin_mux);
Tom Rini6bfca502012-08-08 10:32:09 -0700335 else if (profile == PROFILE_2) {
336 configure_module_pin_mux(mmc1_pin_mux);
Tom Rinia4a99ff2012-08-08 14:35:55 -0700337 configure_module_pin_mux(spi0_pin_mux);
Tom Rini6bfca502012-08-08 10:32:09 -0700338 }
Tom Riniace42752013-07-18 15:13:01 -0400339 } else if (board_is_idk(header)) {
Matthias Fuchsa956bdc2012-11-02 03:35:59 +0000340 /*
341 * Industrial Motor Control (IDK)
342 * note: IDK console is on UART3 by default.
343 * So u-boot mus be build with CONFIG_SERIAL4 and
344 * CONFIG_CONS_INDEX=4
345 */
346 configure_module_pin_mux(mii1_pin_mux);
347 configure_module_pin_mux(mmc0_no_cd_pin_mux);
Tom Riniace42752013-07-18 15:13:01 -0400348 } else if (board_is_evm_sk(header)) {
Tom Rinidb7dd812012-07-31 10:50:01 -0700349 /* Starter Kit EVM */
Tom Rini036fd652012-08-08 09:03:07 -0700350 configure_module_pin_mux(i2c1_pin_mux);
Tom Rinidb7dd812012-07-31 10:50:01 -0700351 configure_module_pin_mux(gpio0_7_pin_mux);
352 configure_module_pin_mux(rgmii1_pin_mux);
353 configure_module_pin_mux(mmc0_pin_mux_sk_evm);
Tom Riniace42752013-07-18 15:13:01 -0400354 } else if (board_is_bone_lt(header)) {
Koen Kooi9cd7b4c2012-10-23 01:56:40 +0000355 /* Beaglebone LT pinmux */
356 configure_module_pin_mux(i2c1_pin_mux);
357 configure_module_pin_mux(mii1_pin_mux);
358 configure_module_pin_mux(mmc0_pin_mux);
359 configure_module_pin_mux(mmc1_pin_mux);
Tom Rinidb7dd812012-07-31 10:50:01 -0700360 } else {
361 puts("Unknown board, cannot configure pinmux.");
362 hang();
363 }
Tom Rini65d750b2012-07-31 08:55:01 -0700364}