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Aubrey.Li3f0606a2007-03-09 13:38:44 +08001/*
2 * U-boot - Configuration file for BF533 STAMP board
3 */
4
Mike Frysingercf6f4692008-06-01 09:09:48 -04005#ifndef __CONFIG_BF533_STAMP_H__
6#define __CONFIG_BF533_STAMP_H__
Aubrey.Li3f0606a2007-03-09 13:38:44 +08007
Mike Frysingerf7ce12c2008-02-18 05:26:48 -05008#include <asm/blackfin-config-pre.h>
9
Aubrey.Li3f0606a2007-03-09 13:38:44 +080010
Aubrey.Li3f0606a2007-03-09 13:38:44 +080011/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040012 * Processor Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +080013 */
Mike Frysingercf6f4692008-06-01 09:09:48 -040014#define CONFIG_BFIN_CPU bf533-0.3
15#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 11059200
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
Mike Frysinger9f64ba22008-10-12 23:49:13 -040033#define CONFIG_VCO_MULT 45
Mike Frysingercf6f4692008-06-01 09:09:48 -040034/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 5
40
41
42/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_ADD_WDTH 11
46#define CONFIG_MEM_SIZE 128
47
48#define CONFIG_EBIU_SDRRC_VAL 0x268
49#define CONFIG_EBIU_SDGCTL_VAL 0x911109
50
51#define CONFIG_EBIU_AMGCTL_VAL 0xFF
52#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
53#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
54
55#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
56#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
57
58
59/*
60 * Network Settings
61 */
62#define ADI_CMDS_NETWORK 1
Aubrey Li8db13d62007-03-10 23:49:29 +080063#define CONFIG_DRIVER_SMC91111 1
64#define CONFIG_SMC91111_BASE 0x20300300
Mike Frysingercf6f4692008-06-01 09:09:48 -040065#define SMC91111_EEPROM_INIT() \
66 do { \
67 *pFIO_DIR |= PF1; \
68 *pFIO_FLAG_S = PF1; \
69 SSYNC(); \
70 } while (0)
71#define CONFIG_HOSTNAME bf533-stamp
72/* Uncomment next line to use fixed MAC address */
73/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
Aubrey.Li3f0606a2007-03-09 13:38:44 +080074
Aubrey.Li3f0606a2007-03-09 13:38:44 +080075
76/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040077 * Flash Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +080078 */
Mike Frysingercf6f4692008-06-01 09:09:48 -040079#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_FLASH_BASE 0x20000000
Mike Frysingercf6f4692008-06-01 09:09:48 -040081#define CONFIG_SYS_FLASH_CFI
82#define CONFIG_SYS_FLASH_CFI_AMD_RESET
83#define CONFIG_SYS_MAX_FLASH_BANKS 1
84#define CONFIG_SYS_MAX_FLASH_SECT 67
Aubrey.Li3f0606a2007-03-09 13:38:44 +080085
Mike Frysingercf6f4692008-06-01 09:09:48 -040086
87/*
88 * SPI Settings
89 */
90#define CONFIG_BFIN_SPI
91#define CONFIG_ENV_SPI_MAX_HZ 30000000
92#define CONFIG_SF_DEFAULT_HZ 30000000
93#define CONFIG_SPI_FLASH
94#define CONFIG_SPI_FLASH_ATMEL
95#define CONFIG_SPI_FLASH_SPANSION
96#define CONFIG_SPI_FLASH_STMICRO
97#define CONFIG_SPI_FLASH_WINBOND
98
99
100/*
101 * Env Storage Settings
102 */
Mike Frysinger9171fc82008-03-30 15:46:13 -0400103#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
Mike Frysingercf6f4692008-06-01 09:09:48 -0400104#define CONFIG_ENV_IS_IN_SPI_FLASH
105#define CONFIG_ENV_OFFSET 0x4000
106#define CONFIG_ENV_SIZE 0x2000
107#define CONFIG_ENV_SECT_SIZE 0x2000
Mike Frysinger9171fc82008-03-30 15:46:13 -0400108#else
Mike Frysingercf6f4692008-06-01 09:09:48 -0400109#define CONFIG_ENV_IS_IN_FLASH
110#define CONFIG_ENV_OFFSET 0x4000
111#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
112#define CONFIG_ENV_SIZE 0x2000
113#define CONFIG_ENV_SECT_SIZE 0x2000
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800114#endif
Mike Frysingercf6f4692008-06-01 09:09:48 -0400115#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
116#define ENV_IS_EMBEDDED
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800117#else
Mike Frysingercf6f4692008-06-01 09:09:48 -0400118#define ENV_IS_EMBEDDED_CUSTOM
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800119#endif
120
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800121
Jon Loeligerba2351f2007-07-04 22:31:49 -0500122/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400123 * I2C Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800124 * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
125 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400126#define CONFIG_SOFT_I2C
127#ifdef CONFIG_SOFT_I2C
128#define PF_SCL PF3
129#define PF_SDA PF2
130#define I2C_INIT \
131 do { \
132 *pFIO_DIR |= PF_SCL; \
133 SSYNC(); \
134 } while (0)
135#define I2C_ACTIVE \
136 do { \
137 *pFIO_DIR |= PF_SDA; \
138 *pFIO_INEN &= ~PF_SDA; \
139 SSYNC(); \
140 } while (0)
141#define I2C_TRISTATE \
142 do { \
143 *pFIO_DIR &= ~PF_SDA; \
144 *pFIO_INEN |= PF_SDA; \
145 SSYNC(); \
146 } while (0)
147#define I2C_READ ((*pFIO_FLAG_D & PF_SDA) != 0)
148#define I2C_SDA(bit) \
149 do { \
150 if (bit) \
151 *pFIO_FLAG_S = PF_SDA; \
152 else \
153 *pFIO_FLAG_C = PF_SDA; \
154 SSYNC(); \
155 } while (0)
156#define I2C_SCL(bit) \
157 do { \
158 if (bit) \
159 *pFIO_FLAG_S = PF_SCL; \
160 else \
161 *pFIO_FLAG_C = PF_SCL; \
162 SSYNC(); \
163 } while (0)
Aubrey Li8db13d62007-03-10 23:49:29 +0800164#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_I2C_SPEED 50000
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400167#define CONFIG_SYS_I2C_SLAVE 0
Mike Frysingercf6f4692008-06-01 09:09:48 -0400168#endif
169
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800170
171/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400172 * Compact Flash / IDE / ATA Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800173 */
174
175/* Enabled below option for CF support */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400176/* #define CONFIG_STAMP_CF */
177#if defined(CONFIG_STAMP_CF)
178#define CONFIG_MISC_INIT_R
Aubrey Li8db13d62007-03-10 23:49:29 +0800179#define CONFIG_DOS_PARTITION 1
Aubrey Li8db13d62007-03-10 23:49:29 +0800180#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
181#undef CONFIG_IDE_LED /* no led for ide supported */
182#undef CONFIG_IDE_RESET /* no reset for ide supported */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800183
Mike Frysingercf6f4692008-06-01 09:09:48 -0400184#define CONFIG_SYS_IDE_MAXBUS 1
185#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_ATA_BASE_ADDR 0x20200000
188#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800189
Mike Frysingercf6f4692008-06-01 09:09:48 -0400190#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
191#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
192#define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_ATA_STRIDE 2
Mike Frysingercf6f4692008-06-01 09:09:48 -0400195
196#undef CONFIG_EBIU_AMBCTL1_VAL
197#define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800198#endif
199
Mike Frysingercf6f4692008-06-01 09:09:48 -0400200
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800201/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400202 * Misc Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800203 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400204#define CONFIG_RTC_BFIN
205#define CONFIG_UART_CONSOLE 0
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800206
Mike Frysingercf6f4692008-06-01 09:09:48 -0400207/* FLASH/ETHERNET uses the same async bank */
208#define SHARED_RESOURCES 1
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800209
Mike Frysinger23fd9592008-10-11 22:40:22 -0400210/* define to enable boot progress via leds */
211/* #define CONFIG_SHOW_BOOT_PROGRESS */
212
213/* define to enable run status via led */
214/* #define CONFIG_STATUS_LED */
215#ifdef CONFIG_STATUS_LED
216#define CONFIG_BOARD_SPECIFIC_LED
217#ifndef __ASSEMBLY__
218typedef unsigned int led_id_t;
219void __led_init(led_id_t mask, int state);
220void __led_set(led_id_t mask, int state);
221void __led_toggle(led_id_t mask);
222#endif
223/* use LED1 to indicate booting/alive */
224#define STATUS_LED_BOOT 0
225#define STATUS_LED_BIT 1
226#define STATUS_LED_STATE STATUS_LED_ON
227#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
228/* use LED2 to indicate crash */
229#define STATUS_LED_CRASH 1
230#define STATUS_LED_BIT1 2
231#define STATUS_LED_STATE1 STATUS_LED_ON
232#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
233#endif
234
Mike Frysingercf6f4692008-06-01 09:09:48 -0400235/* define to enable splash screen support */
236/* #define CONFIG_VIDEO */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800237
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800238
239/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400240 * Pull in common ADI header for remaining command/environment setup
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800241 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400242#include <configs/bfin_adi_common.h>
Mike Frysinger9171fc82008-03-30 15:46:13 -0400243
244#include <asm/blackfin-config-post.h>
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800245
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800246#endif