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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Pavel Machek5095ee02014-09-08 14:08:45 +02002/*
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
Pavel Machek5095ee02014-09-08 14:08:45 +02004 */
Dinh Nguyen48275c92015-12-03 16:05:59 -06005#ifndef __CONFIG_SOCFPGA_COMMON_H__
6#define __CONFIG_SOCFPGA_COMMON_H__
Pavel Machek5095ee02014-09-08 14:08:45 +02007
Pavel Machek5095ee02014-09-08 14:08:45 +02008/*
9 * High level configuration
10 */
Pavel Machek5095ee02014-09-08 14:08:45 +020011#define CONFIG_CLOCKS
12
Pavel Machek5095ee02014-09-08 14:08:45 +020013#define CONFIG_TIMESTAMP /* Print image info with timestamp */
14
15/*
16 * Memory configurations
17 */
Pavel Machek5095ee02014-09-08 14:08:45 +020018#define PHYS_SDRAM_1 0x0
Marek Vasut0223a952014-11-04 04:25:09 +010019#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
Pavel Machek5095ee02014-09-08 14:08:45 +020020#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
21#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
Ley Foon Tan1b259402017-04-26 02:44:46 +080022#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
Pavel Machek5095ee02014-09-08 14:08:45 +020023#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
Marek Vasut7599b532015-07-12 15:23:28 +020024#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
Ley Foon Tan1b259402017-04-26 02:44:46 +080025#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
26#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
Simon Goldschmidt4399e482019-04-09 21:02:04 +020027/* SPL memory allocation configuration, this is for FAT implementation */
28#ifndef CONFIG_SYS_SPL_MALLOC_SIZE
29#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
30#endif
31#define CONFIG_SYS_INIT_RAM_SIZE (0x40000 - CONFIG_SYS_SPL_MALLOC_SIZE)
32#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
33 CONFIG_SYS_INIT_RAM_SIZE)
Ley Foon Tan1b259402017-04-26 02:44:46 +080034#endif
Stefan Roesef457c522018-10-30 10:00:22 +010035
36/*
37 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
38 * SRAM as bootcounter storage. Make sure to not put the stack directly
39 * at this address to not overwrite the bootcounter by checking, if the
40 * bootcounter address is located in the internal SRAM.
41 */
42#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
43 (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
44 CONFIG_SYS_INIT_RAM_SIZE)))
Simon Goldschmidt4399e482019-04-09 21:02:04 +020045#define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
Stefan Roesef457c522018-10-30 10:00:22 +010046#else
Simon Goldschmidt4399e482019-04-09 21:02:04 +020047#define CONFIG_SPL_STACK \
Marek Vasut768f23d2018-04-26 22:23:05 +020048 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
Stefan Roesef457c522018-10-30 10:00:22 +010049#endif
Pavel Machek5095ee02014-09-08 14:08:45 +020050
Simon Goldschmidt4399e482019-04-09 21:02:04 +020051/*
52 * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
53 * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
54 * in U-Boot pre-reloc is higher than in SPL.
55 */
56#if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
57#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
58#else
59#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
60#endif
61
Pavel Machek5095ee02014-09-08 14:08:45 +020062#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Pavel Machek5095ee02014-09-08 14:08:45 +020063
64/*
65 * U-Boot general configurations
66 */
Pavel Machek5095ee02014-09-08 14:08:45 +020067#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
Pavel Machek5095ee02014-09-08 14:08:45 +020068 /* Print buffer size */
69#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
70#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
71 /* Boot argument buffer size */
Pavel Machek5095ee02014-09-08 14:08:45 +020072
73/*
74 * Cache
75 */
Pavel Machek5095ee02014-09-08 14:08:45 +020076#define CONFIG_SYS_L2_PL310
77#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
78
79/*
80 * Ethernet on SoC (EMAC)
81 */
Marek Vasutf7917322018-04-23 01:26:10 +020082#ifdef CONFIG_CMD_NET
Pavel Machek5095ee02014-09-08 14:08:45 +020083#define CONFIG_DW_ALTDESCRIPTOR
Pavel Machek5095ee02014-09-08 14:08:45 +020084#endif
85
86/*
87 * FPGA Driver
88 */
89#ifdef CONFIG_CMD_FPGA
Pavel Machek5095ee02014-09-08 14:08:45 +020090#define CONFIG_FPGA_COUNT 1
91#endif
Tien Fong Chee9af91b72017-07-26 13:05:44 +080092
Pavel Machek5095ee02014-09-08 14:08:45 +020093/*
94 * L4 OSC1 Timer 0
95 */
Marek Vasut331c3722018-08-18 16:00:31 +020096#ifndef CONFIG_TIMER
Pavel Machek5095ee02014-09-08 14:08:45 +020097/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
98#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
99#define CONFIG_SYS_TIMER_COUNTS_DOWN
100#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
Pavel Machek5095ee02014-09-08 14:08:45 +0200101#define CONFIG_SYS_TIMER_RATE 25000000
Marek Vasut331c3722018-08-18 16:00:31 +0200102#endif
Pavel Machek5095ee02014-09-08 14:08:45 +0200103
104/*
105 * L4 Watchdog
106 */
Pavel Machek5095ee02014-09-08 14:08:45 +0200107#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
108#define CONFIG_DW_WDT_CLOCK_KHZ 25000
Pavel Machek5095ee02014-09-08 14:08:45 +0200109
110/*
111 * MMC Driver
112 */
113#ifdef CONFIG_CMD_MMC
Pavel Machek5095ee02014-09-08 14:08:45 +0200114/* FIXME */
115/* using smaller max blk cnt to avoid flooding the limited stack we have */
116#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
117#endif
118
Stefan Roese7fb0f592014-11-07 12:37:52 +0100119/*
Marek Vasutc339ea52015-12-20 04:00:46 +0100120 * NAND Support
121 */
122#ifdef CONFIG_NAND_DENALI
123#define CONFIG_SYS_MAX_NAND_DEVICE 1
Marek Vasutc339ea52015-12-20 04:00:46 +0100124#define CONFIG_SYS_NAND_ONFI_DETECTION
Marek Vasutc339ea52015-12-20 04:00:46 +0100125#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
126#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
Marek Vasutc339ea52015-12-20 04:00:46 +0100127#endif
128
129/*
Stefan Roese7fb0f592014-11-07 12:37:52 +0100130 * QSPI support
131 */
Stefan Roese7fb0f592014-11-07 12:37:52 +0100132/* QSPI reference clock */
133#ifndef __ASSEMBLY__
134unsigned int cm_get_qspi_controller_clk_hz(void);
135#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
136#endif
Stefan Roese7fb0f592014-11-07 12:37:52 +0100137
Marek Vasut0c745d02015-08-19 23:23:53 +0200138/*
Marek Vasut20cadbb2014-10-24 23:34:25 +0200139 * USB
140 */
Marek Vasut20cadbb2014-10-24 23:34:25 +0200141
142/*
Marek Vasut0223a952014-11-04 04:25:09 +0100143 * USB Gadget (DFU, UMS)
144 */
145#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
Marek Vasut55ce55f2016-10-29 21:15:56 +0200146#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
Marek Vasut0223a952014-11-04 04:25:09 +0100147#define DFU_DEFAULT_POLL_TIMEOUT 300
148
149/* USB IDs */
Sam Protsenkoe6c0bc02016-04-13 14:20:30 +0300150#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
151#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
Marek Vasut0223a952014-11-04 04:25:09 +0100152#endif
153
154/*
Pavel Machek5095ee02014-09-08 14:08:45 +0200155 * U-Boot environment
156 */
Pavel Machek5095ee02014-09-08 14:08:45 +0200157
Chin Liang See79cc48e2015-12-21 21:02:45 +0800158/* Environment for SDMMC boot */
Tom Rinia09fea12019-11-18 20:02:10 -0500159#if defined(CONFIG_ENV_IS_IN_MMC)
Dalon Westergreen451e8242017-04-13 07:30:29 -0700160#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
Chin Liang See79cc48e2015-12-21 21:02:45 +0800161#endif
162
Chin Liang Seeec8b7522016-02-24 16:50:22 +0800163/* Environment for QSPI boot */
Chin Liang Seeec8b7522016-02-24 16:50:22 +0800164
Pavel Machek5095ee02014-09-08 14:08:45 +0200165/*
166 * SPL
Marek Vasut34584d12014-10-16 12:25:40 +0200167 *
Tien Fong Chee421a21c2017-12-05 15:58:04 +0800168 * SRAM Memory layout for gen 5:
Marek Vasut34584d12014-10-16 12:25:40 +0200169 *
170 * 0xFFFF_0000 ...... Start of SRAM
171 * 0xFFFF_xxxx ...... Top of stack (grows down)
Simon Goldschmidt798baf72019-04-09 21:02:03 +0200172 * 0xFFFF_yyyy ...... Global Data
173 * 0xFFFF_zzzz ...... Malloc area
174 * 0xFFFF_FFFF ...... End of SRAM
Tien Fong Chee421a21c2017-12-05 15:58:04 +0800175 *
176 * SRAM Memory layout for Arria 10:
177 * 0xFFE0_0000 ...... Start of SRAM (bottom)
178 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
179 * 0xFFEy_yyyy ...... Global Data
180 * 0xFFEz_zzzz ...... Malloc area (grows up to top)
181 * 0xFFE3_FFFF ...... End of SRAM (top)
Pavel Machek5095ee02014-09-08 14:08:45 +0200182 */
Simon Goldschmidt92a47452019-03-15 20:44:32 +0100183#ifndef CONFIG_SPL_TEXT_BASE
Ley Foon Tan1b259402017-04-26 02:44:46 +0800184#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
Simon Goldschmidt92a47452019-03-15 20:44:32 +0100185#endif
Pavel Machek5095ee02014-09-08 14:08:45 +0200186
Marek Vasutd3f34e72015-07-10 00:04:23 +0200187/* SPL SDMMC boot support */
188#ifdef CONFIG_SPL_MMC_SUPPORT
Tien Fong Cheef4b40922019-01-23 14:20:05 +0800189#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
Dalon Westergreen998f7cb2019-08-07 10:37:36 -0700190#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Dalon Westergreen451e8242017-04-13 07:30:29 -0700191#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
192#endif
193#else
194#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
195#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
Marek Vasutd3f34e72015-07-10 00:04:23 +0200196#endif
197#endif
Pavel Machek5095ee02014-09-08 14:08:45 +0200198
Marek Vasut346d6f52015-07-21 07:50:03 +0200199/* SPL QSPI boot support */
Marek Vasut346d6f52015-07-21 07:50:03 +0200200
Marek Vasutc339ea52015-12-20 04:00:46 +0100201/* SPL NAND boot support */
202#ifdef CONFIG_SPL_NAND_SUPPORT
Marek Vasutbd6363a2018-05-08 18:44:43 +0200203#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
Marek Vasutc339ea52015-12-20 04:00:46 +0100204#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
Marek Vasutbd6363a2018-05-08 18:44:43 +0200205#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
206#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
207#endif
Marek Vasutc339ea52015-12-20 04:00:46 +0100208#endif
209
Dalon Westergreen451e8242017-04-13 07:30:29 -0700210/* Extra Environment */
211#ifndef CONFIG_SPL_BUILD
Dalon Westergreen451e8242017-04-13 07:30:29 -0700212
Simon Goldschmidt1c7fa792018-01-25 07:18:27 +0100213#ifdef CONFIG_CMD_DHCP
214#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
215#else
216#define BOOT_TARGET_DEVICES_DHCP(func)
217#endif
218
Joe Hershberger86271b32018-04-13 15:26:40 -0500219#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
Dalon Westergreen451e8242017-04-13 07:30:29 -0700220#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
221#else
222#define BOOT_TARGET_DEVICES_PXE(func)
223#endif
224
225#ifdef CONFIG_CMD_MMC
226#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
227#else
228#define BOOT_TARGET_DEVICES_MMC(func)
229#endif
230
231#define BOOT_TARGET_DEVICES(func) \
232 BOOT_TARGET_DEVICES_MMC(func) \
233 BOOT_TARGET_DEVICES_PXE(func) \
Simon Goldschmidt1c7fa792018-01-25 07:18:27 +0100234 BOOT_TARGET_DEVICES_DHCP(func)
Dalon Westergreen451e8242017-04-13 07:30:29 -0700235
236#include <config_distro_bootcmd.h>
237
238#ifndef CONFIG_EXTRA_ENV_SETTINGS
239#define CONFIG_EXTRA_ENV_SETTINGS \
240 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
241 "bootm_size=0xa000000\0" \
242 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
243 "fdt_addr_r=0x02000000\0" \
244 "scriptaddr=0x02100000\0" \
245 "pxefile_addr_r=0x02200000\0" \
246 "ramdisk_addr_r=0x02300000\0" \
Simon Goldschmidt4b2e32e2019-03-01 20:12:31 +0100247 "socfpga_legacy_reset_compat=1\0" \
Dalon Westergreen451e8242017-04-13 07:30:29 -0700248 BOOTENV
249
250#endif
251#endif
252
Dinh Nguyen48275c92015-12-03 16:05:59 -0600253#endif /* __CONFIG_SOCFPGA_COMMON_H__ */