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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / b0aef11c9f1f98d018adaa484f1e048fa626801e / . / include / ps2mult.h
blob: 8da20fc44214ce80b0e20ed325c33d0b9e9a6781 [file] [log] [blame]
wdenk1c437712004-01-16 00:30:56 +0000[diff] [blame]1#ifndef __LINUX_PS2MULT_H
2#define __LINUX_PS2MULT_H
3
4#define kbd_request_region() ps2mult_init()
5#define kbd_request_irq(handler) ps2mult_request_irq(handler)
6
7#define kbd_read_input() ps2mult_read_input()
8#define kbd_read_status() ps2mult_read_status()
9#define kbd_write_output(val) ps2mult_write_output(val)
10#define kbd_write_command(val) ps2mult_write_command(val)
11
12#define aux_request_irq(hand, dev_id) 0
13#define aux_free_irq(dev_id)
14
15#define PS2MULT_KB_SELECTOR 0xA0
16#define PS2MULT_MS_SELECTOR 0xA1
17#define PS2MULT_ESCAPE 0x7D
18#define PS2MULT_BSYNC 0x7E
19#define PS2MULT_SESSION_START 0x55
20#define PS2MULT_SESSION_END 0x56
21
22#define PS2BUF_SIZE 512 /* power of 2, please */
23
24 /* PS/2 controller interface (include/asm/keyboard.h)
25 */
26extern int ps2mult_init (void);
27extern int ps2mult_request_irq(void (*handler)(void *));
28extern u_char ps2mult_read_input(void);
29extern u_char ps2mult_read_status(void);
30extern void ps2mult_write_output(u_char val);
31extern void ps2mult_write_command(u_char val);
32
33extern void ps2mult_callback (int in_cnt);
34
35 /* Simple serial interface
36 */
37extern int ps2ser_init(void);
38extern void ps2ser_putc(int chr);
39extern int ps2ser_getc(void);
40extern int ps2ser_check(void);
41
42
43 /* Serial related stuff
44 */
45struct serial_state {
46 int baud_base;
47 int irq;
48 u8 *iomem_base;
49};
50
51#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
52#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
53#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
54
55#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
56#define UART_IER 1 /* Out: Interrupt Enable Register */
57
58#define UART_IIR 2 /* In: Interrupt ID Register */
59#define UART_FCR 2 /* Out: FIFO Control Register */
60
61#define UART_LCR 3 /* Out: Line Control Register */
62#define UART_MCR 4 /* Out: Modem Control Register */
63#define UART_LSR 5 /* In: Line Status Register */
64#define UART_MSR 6 /* In: Modem Status Register */
65#define UART_SCR 7 /* I/O: Scratch Register */
66
67/*
68 * These are the definitions for the FIFO Control Register
69 * (16650 only)
70 */
71#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
72#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
73#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
74#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
75#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
76#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
77#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
78#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
79#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
80
81/*
82 * These are the definitions for the Line Control Register
83 *
84 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
85 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
86 */
87#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
88#define UART_LCR_SBC 0x40 /* Set break control */
89#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
90#define UART_LCR_EPAR 0x10 /* Even parity select */
91#define UART_LCR_PARITY 0x08 /* Parity Enable */
92#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
93#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
94#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
95#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
96#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
97
98/*
99 * These are the definitions for the Line Status Register
100 */
101#define UART_LSR_TEMT 0x40 /* Transmitter empty */
102#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
103#define UART_LSR_BI 0x10 /* Break interrupt indicator */
104#define UART_LSR_FE 0x08 /* Frame error indicator */
105#define UART_LSR_PE 0x04 /* Parity error indicator */
106#define UART_LSR_OE 0x02 /* Overrun error indicator */
107#define UART_LSR_DR 0x01 /* Receiver data ready */
108
109/*
110 * These are the definitions for the Interrupt Identification Register
111 */
112#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
113#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
114
115#define UART_IIR_MSI 0x00 /* Modem status interrupt */
116#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
117#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
118#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
119
120/*
121 * These are the definitions for the Interrupt Enable Register
122 */
123#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
124#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
125#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
126#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
127
128/*
129 * These are the definitions for the Modem Control Register
130 */
131#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
132#define UART_MCR_OUT2 0x08 /* Out2 complement */
133#define UART_MCR_OUT1 0x04 /* Out1 complement */
134#define UART_MCR_RTS 0x02 /* RTS complement */
135#define UART_MCR_DTR 0x01 /* DTR complement */
136
137/*
138 * These are the definitions for the Modem Status Register
139 */
140#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
141#define UART_MSR_RI 0x40 /* Ring Indicator */
142#define UART_MSR_DSR 0x20 /* Data Set Ready */
143#define UART_MSR_CTS 0x10 /* Clear to Send */
144#define UART_MSR_DDCD 0x08 /* Delta DCD */
145#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
146#define UART_MSR_DDSR 0x02 /* Delta DSR */
147#define UART_MSR_DCTS 0x01 /* Delta CTS */
148#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
149
150#endif /* __LINUX_PS2MULT_H */