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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkfe8c2802002-11-03 00:38:21 +00002/*------------------------------------------------------------------------
3 . smc91111.c
4 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
5 .
6 . (C) Copyright 2002
7 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 . Rolf Offermanns <rof@sysgo.de>
9 .
10 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
wdenk42dfe7a2004-03-14 22:25:36 +000011 . Developed by Simple Network Magic Corporation (SNMC)
wdenkfe8c2802002-11-03 00:38:21 +000012 . Copyright (C) 1996 by Erik Stahlman (ES)
13 .
wdenkfe8c2802002-11-03 00:38:21 +000014 .
15 . Information contained in this file was obtained from the LAN91C111
16 . manual from SMC. To get a copy, if you really want one, you can find
17 . information under www.smsc.com.
18 .
19 .
20 . "Features" of the SMC chip:
21 . Integrated PHY/MAC for 10/100BaseT Operation
22 . Supports internal and external MII
23 . Integrated 8K packet memory
24 . EEPROM interface for configuration
25 .
26 . Arguments:
wdenk42dfe7a2004-03-14 22:25:36 +000027 . io = for the base address
wdenkfe8c2802002-11-03 00:38:21 +000028 . irq = for the IRQ
29 .
30 . author:
wdenk42dfe7a2004-03-14 22:25:36 +000031 . Erik Stahlman ( erik@vt.edu )
32 . Daris A Nevil ( dnevil@snmc.com )
wdenkfe8c2802002-11-03 00:38:21 +000033 .
34 .
35 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
36 .
37 . Sources:
wdenk42dfe7a2004-03-14 22:25:36 +000038 . o SMSC LAN91C111 databook (www.smsc.com)
39 . o smc9194.c by Erik Stahlman
40 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
wdenkfe8c2802002-11-03 00:38:21 +000041 .
42 . History:
wdenk42dfe7a2004-03-14 22:25:36 +000043 . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
wdenkfe8c2802002-11-03 00:38:21 +000044 . 10/17/01 Marco Hasewinkel Modify for DNP/1110
wdenk42dfe7a2004-03-14 22:25:36 +000045 . 07/25/01 Woojung Huh Modify for ADS Bitsy
46 . 04/25/01 Daris A Nevil Initial public release through SMSC
47 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
wdenkfe8c2802002-11-03 00:38:21 +000048 ----------------------------------------------------------------------------*/
49
50#include <common.h>
51#include <command.h>
wdenkf39748a2004-06-09 13:37:52 +000052#include <config.h>
Ben Warren7194ab82009-10-04 22:37:03 -070053#include <malloc.h>
wdenkfe8c2802002-11-03 00:38:21 +000054#include "smc91111.h"
55#include <net.h>
56
wdenkfe8c2802002-11-03 00:38:21 +000057/* Use power-down feature of the chip */
58#define POWER_DOWN 0
59
60#define NO_AUTOPROBE
61
Wolfgang Denk0be248f2006-03-07 00:22:36 +010062#define SMC_DEBUG 0
wdenk8bf3b002003-12-06 23:20:41 +000063
64#if SMC_DEBUG > 1
wdenkfe8c2802002-11-03 00:38:21 +000065static const char version[] =
66 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
wdenk8bf3b002003-12-06 23:20:41 +000067#endif
wdenkfe8c2802002-11-03 00:38:21 +000068
wdenkf39748a2004-06-09 13:37:52 +000069/* Autonegotiation timeout in seconds */
70#ifndef CONFIG_SMC_AUTONEG_TIMEOUT
71#define CONFIG_SMC_AUTONEG_TIMEOUT 10
72#endif
73
wdenkfe8c2802002-11-03 00:38:21 +000074/*------------------------------------------------------------------------
75 .
76 . Configuration options, for the experienced user to change.
77 .
78 -------------------------------------------------------------------------*/
79
80/*
81 . Wait time for memory to be free. This probably shouldn't be
82 . tuned that much, as waiting for this means nothing else happens
83 . in the system
84*/
85#define MEMORY_WAIT_TIME 16
86
87
88#if (SMC_DEBUG > 2 )
89#define PRINTK3(args...) printf(args)
90#else
91#define PRINTK3(args...)
92#endif
93
94#if SMC_DEBUG > 1
95#define PRINTK2(args...) printf(args)
96#else
97#define PRINTK2(args...)
98#endif
99
100#ifdef SMC_DEBUG
101#define PRINTK(args...) printf(args)
102#else
103#define PRINTK(args...)
104#endif
105
106
107/*------------------------------------------------------------------------
108 .
wdenk42dfe7a2004-03-14 22:25:36 +0000109 . The internal workings of the driver. If you are changing anything
wdenkfe8c2802002-11-03 00:38:21 +0000110 . here with the SMC stuff, you should have the datasheet and know
111 . what you are doing.
112 .
113 -------------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000114
115/* Memory sizing constant */
116#define LAN91C111_MEMORY_MULTIPLIER (1024*2)
117
118#ifndef CONFIG_SMC91111_BASE
Ben Warren7194ab82009-10-04 22:37:03 -0700119#error "SMC91111 Base address must be passed to initialization funciton"
120/* #define CONFIG_SMC91111_BASE 0x20000300 */
wdenkfe8c2802002-11-03 00:38:21 +0000121#endif
122
wdenkfe8c2802002-11-03 00:38:21 +0000123#define SMC_DEV_NAME "SMC91111"
124#define SMC_PHY_ADDR 0x0000
125#define SMC_ALLOC_MAX_TRY 5
126#define SMC_TX_TIMEOUT 30
127
128#define SMC_PHY_CLOCK_DELAY 1000
129
130#define ETH_ZLEN 60
131
wdenk42dfe7a2004-03-14 22:25:36 +0000132#ifdef CONFIG_SMC_USE_32_BIT
wdenkfe8c2802002-11-03 00:38:21 +0000133#define USE_32_BIT 1
134#else
135#undef USE_32_BIT
136#endif
wdenkfe8c2802002-11-03 00:38:21 +0000137
Wolfgang Denk0afe5192006-03-12 02:10:00 +0100138#ifdef SHARED_RESOURCES
Ben Warren7194ab82009-10-04 22:37:03 -0700139extern void swap_to(int device_id);
140#else
141# define swap_to(x)
Wolfgang Denk0afe5192006-03-12 02:10:00 +0100142#endif
wdenkfe8c2802002-11-03 00:38:21 +0000143
wdenkfe8c2802002-11-03 00:38:21 +0000144#ifndef CONFIG_SMC91111_EXT_PHY
Ben Warren7194ab82009-10-04 22:37:03 -0700145static void smc_phy_configure(struct eth_device *dev);
wdenkfe8c2802002-11-03 00:38:21 +0000146#endif /* !CONFIG_SMC91111_EXT_PHY */
147
148/*
wdenkfe8c2802002-11-03 00:38:21 +0000149 ------------------------------------------------------------
150 .
151 . Internal routines
152 .
153 ------------------------------------------------------------
154*/
155
wdenkc3c7f862004-06-09 14:47:54 +0000156#ifdef CONFIG_SMC_USE_IOFUNCS
157/*
158 * input and output functions
159 *
160 * Implemented due to inx,outx macros accessing the device improperly
161 * and putting the device into an unkown state.
162 *
163 * For instance, on Sharp LPD7A400 SDK, affects were chip memory
164 * could not be free'd (hence the alloc failures), duplicate packets,
165 * packets being corrupt (shifted) on the wire, etc. Switching to the
166 * inx,outx functions fixed this problem.
167 */
wdenkc3c7f862004-06-09 14:47:54 +0000168
Ben Warren7194ab82009-10-04 22:37:03 -0700169static inline word SMC_inw(struct eth_device *dev, dword offset)
wdenkc3c7f862004-06-09 14:47:54 +0000170{
171 word v;
Ben Warren7194ab82009-10-04 22:37:03 -0700172 v = *((volatile word*)(dev->iobase + offset));
wdenkc3c7f862004-06-09 14:47:54 +0000173 barrier(); *(volatile u32*)(0xc0000000);
174 return v;
175}
176
Ben Warren7194ab82009-10-04 22:37:03 -0700177static inline void SMC_outw(struct eth_device *dev, word value, dword offset)
wdenkc3c7f862004-06-09 14:47:54 +0000178{
Ben Warren7194ab82009-10-04 22:37:03 -0700179 *((volatile word*)(dev->iobase + offset)) = value;
wdenkc3c7f862004-06-09 14:47:54 +0000180 barrier(); *(volatile u32*)(0xc0000000);
181}
182
Ben Warren7194ab82009-10-04 22:37:03 -0700183static inline byte SMC_inb(struct eth_device *dev, dword offset)
wdenkc3c7f862004-06-09 14:47:54 +0000184{
185 word _w;
186
Ben Warren7194ab82009-10-04 22:37:03 -0700187 _w = SMC_inw(dev, offset & ~((dword)1));
wdenkc3c7f862004-06-09 14:47:54 +0000188 return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
189}
190
Ben Warren7194ab82009-10-04 22:37:03 -0700191static inline void SMC_outb(struct eth_device *dev, byte value, dword offset)
wdenkc3c7f862004-06-09 14:47:54 +0000192{
193 word _w;
194
Ben Warren7194ab82009-10-04 22:37:03 -0700195 _w = SMC_inw(dev, offset & ~((dword)1));
wdenkc3c7f862004-06-09 14:47:54 +0000196 if (offset & 1)
Ben Warren7194ab82009-10-04 22:37:03 -0700197 *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) =
198 (value<<8) | (_w & 0x00ff);
wdenkc3c7f862004-06-09 14:47:54 +0000199 else
Ben Warren7194ab82009-10-04 22:37:03 -0700200 *((volatile word*)(dev->iobase + offset)) =
201 value | (_w & 0xff00);
wdenkc3c7f862004-06-09 14:47:54 +0000202}
203
Ben Warren7194ab82009-10-04 22:37:03 -0700204static inline void SMC_insw(struct eth_device *dev, dword offset,
205 volatile uchar* buf, dword len)
wdenkc3c7f862004-06-09 14:47:54 +0000206{
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100207 volatile word *p = (volatile word *)buf;
208
wdenkc3c7f862004-06-09 14:47:54 +0000209 while (len-- > 0) {
Ben Warren7194ab82009-10-04 22:37:03 -0700210 *p++ = SMC_inw(dev, offset);
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100211 barrier();
212 *((volatile u32*)(0xc0000000));
wdenkc3c7f862004-06-09 14:47:54 +0000213 }
214}
215
Ben Warren7194ab82009-10-04 22:37:03 -0700216static inline void SMC_outsw(struct eth_device *dev, dword offset,
217 uchar* buf, dword len)
wdenkc3c7f862004-06-09 14:47:54 +0000218{
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100219 volatile word *p = (volatile word *)buf;
220
wdenkc3c7f862004-06-09 14:47:54 +0000221 while (len-- > 0) {
Ben Warren7194ab82009-10-04 22:37:03 -0700222 SMC_outw(dev, *p++, offset);
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100223 barrier();
224 *(volatile u32*)(0xc0000000);
wdenkc3c7f862004-06-09 14:47:54 +0000225 }
226}
227#endif /* CONFIG_SMC_USE_IOFUNCS */
228
wdenkfe8c2802002-11-03 00:38:21 +0000229/*
230 . A rather simple routine to print out a packet for debugging purposes.
231*/
232#if SMC_DEBUG > 2
233static void print_packet( byte *, int );
234#endif
235
236#define tx_done(dev) 1
237
Ben Warren7194ab82009-10-04 22:37:03 -0700238static int poll4int (struct eth_device *dev, byte mask, int timeout)
wdenkb56ddc62003-09-15 21:14:37 +0000239{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240 int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
wdenkb56ddc62003-09-15 21:14:37 +0000241 int is_timeout = 0;
Ben Warren7194ab82009-10-04 22:37:03 -0700242 word old_bank = SMC_inw (dev, BSR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000243
wdenkb56ddc62003-09-15 21:14:37 +0000244 PRINTK2 ("Polling...\n");
Ben Warren7194ab82009-10-04 22:37:03 -0700245 SMC_SELECT_BANK (dev, 2);
246 while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) {
wdenkb56ddc62003-09-15 21:14:37 +0000247 if (get_timer (0) >= tmo) {
248 is_timeout = 1;
249 break;
250 }
wdenkfe8c2802002-11-03 00:38:21 +0000251 }
wdenkfe8c2802002-11-03 00:38:21 +0000252
wdenkb56ddc62003-09-15 21:14:37 +0000253 /* restore old bank selection */
Ben Warren7194ab82009-10-04 22:37:03 -0700254 SMC_SELECT_BANK (dev, old_bank);
wdenkfe8c2802002-11-03 00:38:21 +0000255
wdenkb56ddc62003-09-15 21:14:37 +0000256 if (is_timeout)
257 return 1;
258 else
259 return 0;
wdenkfe8c2802002-11-03 00:38:21 +0000260}
261
wdenk487778b2003-06-06 11:20:01 +0000262/* Only one release command at a time, please */
Ben Warren7194ab82009-10-04 22:37:03 -0700263static inline void smc_wait_mmu_release_complete (struct eth_device *dev)
wdenk487778b2003-06-06 11:20:01 +0000264{
265 int count = 0;
wdenkb56ddc62003-09-15 21:14:37 +0000266
wdenk487778b2003-06-06 11:20:01 +0000267 /* assume bank 2 selected */
Ben Warren7194ab82009-10-04 22:37:03 -0700268 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
wdenkb56ddc62003-09-15 21:14:37 +0000269 udelay (1); /* Wait until not busy */
270 if (++count > 200)
271 break;
wdenk487778b2003-06-06 11:20:01 +0000272 }
273}
274
wdenkfe8c2802002-11-03 00:38:21 +0000275/*
276 . Function: smc_reset( void )
277 . Purpose:
wdenk42dfe7a2004-03-14 22:25:36 +0000278 . This sets the SMC91111 chip to its normal state, hopefully from whatever
279 . mess that any other DOS driver has put it in.
wdenkfe8c2802002-11-03 00:38:21 +0000280 .
281 . Maybe I should reset more registers to defaults in here? SOFTRST should
282 . do that for me.
283 .
284 . Method:
285 . 1. send a SOFT RESET
286 . 2. wait for it to finish
287 . 3. enable autorelease mode
288 . 4. reset the memory management unit
289 . 5. clear all interrupts
290 .
291*/
Ben Warren7194ab82009-10-04 22:37:03 -0700292static void smc_reset (struct eth_device *dev)
wdenkfe8c2802002-11-03 00:38:21 +0000293{
wdenkf39748a2004-06-09 13:37:52 +0000294 PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000295
296 /* This resets the registers mostly to defaults, but doesn't
297 affect EEPROM. That seems unnecessary */
Ben Warren7194ab82009-10-04 22:37:03 -0700298 SMC_SELECT_BANK (dev, 0);
299 SMC_outw (dev, RCR_SOFTRST, RCR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000300
301 /* Setup the Configuration Register */
302 /* This is necessary because the CONFIG_REG is not affected */
303 /* by a soft reset */
304
Ben Warren7194ab82009-10-04 22:37:03 -0700305 SMC_SELECT_BANK (dev, 1);
wdenkfe8c2802002-11-03 00:38:21 +0000306#if defined(CONFIG_SMC91111_EXT_PHY)
Ben Warren7194ab82009-10-04 22:37:03 -0700307 SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000308#else
Ben Warren7194ab82009-10-04 22:37:03 -0700309 SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000310#endif
311
312
313 /* Release from possible power-down state */
314 /* Configuration register is not affected by Soft Reset */
Ben Warren7194ab82009-10-04 22:37:03 -0700315 SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN,
316 CONFIG_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000317
Ben Warren7194ab82009-10-04 22:37:03 -0700318 SMC_SELECT_BANK (dev, 0);
wdenkfe8c2802002-11-03 00:38:21 +0000319
320 /* this should pause enough for the chip to be happy */
wdenkb56ddc62003-09-15 21:14:37 +0000321 udelay (10);
wdenkfe8c2802002-11-03 00:38:21 +0000322
323 /* Disable transmit and receive functionality */
Ben Warren7194ab82009-10-04 22:37:03 -0700324 SMC_outw (dev, RCR_CLEAR, RCR_REG);
325 SMC_outw (dev, TCR_CLEAR, TCR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000326
327 /* set the control register */
Ben Warren7194ab82009-10-04 22:37:03 -0700328 SMC_SELECT_BANK (dev, 1);
329 SMC_outw (dev, CTL_DEFAULT, CTL_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000330
331 /* Reset the MMU */
Ben Warren7194ab82009-10-04 22:37:03 -0700332 SMC_SELECT_BANK (dev, 2);
333 smc_wait_mmu_release_complete (dev);
334 SMC_outw (dev, MC_RESET, MMU_CMD_REG);
335 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY)
wdenkb56ddc62003-09-15 21:14:37 +0000336 udelay (1); /* Wait until not busy */
wdenkfe8c2802002-11-03 00:38:21 +0000337
338 /* Note: It doesn't seem that waiting for the MMU busy is needed here,
339 but this is a place where future chipsets _COULD_ break. Be wary
wdenk8bde7f72003-06-27 21:31:46 +0000340 of issuing another MMU command right after this */
wdenkfe8c2802002-11-03 00:38:21 +0000341
342 /* Disable all interrupts */
Ben Warren7194ab82009-10-04 22:37:03 -0700343 SMC_outb (dev, 0, IM_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000344}
345
346/*
347 . Function: smc_enable
348 . Purpose: let the chip talk to the outside work
349 . Method:
350 . 1. Enable the transmitter
351 . 2. Enable the receiver
352 . 3. Enable interrupts
353*/
Ben Warren7194ab82009-10-04 22:37:03 -0700354static void smc_enable(struct eth_device *dev)
wdenkfe8c2802002-11-03 00:38:21 +0000355{
wdenkf39748a2004-06-09 13:37:52 +0000356 PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
Ben Warren7194ab82009-10-04 22:37:03 -0700357 SMC_SELECT_BANK( dev, 0 );
wdenkfe8c2802002-11-03 00:38:21 +0000358 /* see the header file for options in TCR/RCR DEFAULT*/
Ben Warren7194ab82009-10-04 22:37:03 -0700359 SMC_outw( dev, TCR_DEFAULT, TCR_REG );
360 SMC_outw( dev, RCR_DEFAULT, RCR_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000361
362 /* clear MII_DIS */
363/* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
364}
365
366/*
Ben Warren7194ab82009-10-04 22:37:03 -0700367 . Function: smc_halt
wdenkfe8c2802002-11-03 00:38:21 +0000368 . Purpose: closes down the SMC91xxx chip.
369 . Method:
370 . 1. zero the interrupt mask
371 . 2. clear the enable receive flag
372 . 3. clear the enable xmit flags
373 .
374 . TODO:
375 . (1) maybe utilize power down mode.
376 . Why not yet? Because while the chip will go into power down mode,
377 . the manual says that it will wake up in response to any I/O requests
wdenk42dfe7a2004-03-14 22:25:36 +0000378 . in the register space. Empirical results do not show this working.
wdenkfe8c2802002-11-03 00:38:21 +0000379*/
Ben Warren7194ab82009-10-04 22:37:03 -0700380static void smc_halt(struct eth_device *dev)
wdenkfe8c2802002-11-03 00:38:21 +0000381{
Ben Warren7194ab82009-10-04 22:37:03 -0700382 PRINTK2("%s: smc_halt\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000383
384 /* no more interrupts for me */
Ben Warren7194ab82009-10-04 22:37:03 -0700385 SMC_SELECT_BANK( dev, 2 );
386 SMC_outb( dev, 0, IM_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000387
388 /* and tell the card to stay away from that nasty outside world */
Ben Warren7194ab82009-10-04 22:37:03 -0700389 SMC_SELECT_BANK( dev, 0 );
390 SMC_outb( dev, RCR_CLEAR, RCR_REG );
391 SMC_outb( dev, TCR_CLEAR, TCR_REG );
392
Wolfgang Denk0afe5192006-03-12 02:10:00 +0100393 swap_to(FLASH);
wdenkfe8c2802002-11-03 00:38:21 +0000394}
395
396
397/*
Ben Warren7194ab82009-10-04 22:37:03 -0700398 . Function: smc_send(struct net_device * )
wdenkfe8c2802002-11-03 00:38:21 +0000399 . Purpose:
400 . This sends the actual packet to the SMC9xxx chip.
401 .
402 . Algorithm:
wdenk42dfe7a2004-03-14 22:25:36 +0000403 . First, see if a saved_skb is available.
wdenkfe8c2802002-11-03 00:38:21 +0000404 . ( this should NOT be called if there is no 'saved_skb'
405 . Now, find the packet number that the chip allocated
406 . Point the data pointers at it in memory
407 . Set the length word in the chip's memory
408 . Dump the packet to chip memory
409 . Check if a last byte is needed ( odd length packet )
410 . if so, set the control flag right
wdenk42dfe7a2004-03-14 22:25:36 +0000411 . Tell the card to send it
wdenkfe8c2802002-11-03 00:38:21 +0000412 . Enable the transmit interrupt, so I know if it failed
wdenk42dfe7a2004-03-14 22:25:36 +0000413 . Free the kernel data if I actually sent it.
wdenkfe8c2802002-11-03 00:38:21 +0000414*/
Joe Hershberger9f098642012-05-21 14:45:32 +0000415static int smc_send(struct eth_device *dev, void *packet, int packet_length)
wdenkfe8c2802002-11-03 00:38:21 +0000416{
wdenkb56ddc62003-09-15 21:14:37 +0000417 byte packet_no;
wdenkb56ddc62003-09-15 21:14:37 +0000418 byte *buf;
419 int length;
420 int numPages;
421 int try = 0;
422 int time_out;
423 byte status;
wdenk518e2e12004-03-25 14:59:05 +0000424 byte saved_pnr;
425 word saved_ptr;
wdenkfe8c2802002-11-03 00:38:21 +0000426
wdenk518e2e12004-03-25 14:59:05 +0000427 /* save PTR and PNR registers before manipulation */
Ben Warren7194ab82009-10-04 22:37:03 -0700428 SMC_SELECT_BANK (dev, 2);
429 saved_pnr = SMC_inb( dev, PN_REG );
430 saved_ptr = SMC_inw( dev, PTR_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000431
wdenkf39748a2004-06-09 13:37:52 +0000432 PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000433
434 length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
435
436 /* allocate memory
wdenkb56ddc62003-09-15 21:14:37 +0000437 ** The MMU wants the number of pages to be the number of 256 bytes
438 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
439 **
440 ** The 91C111 ignores the size bits, but the code is left intact
441 ** for backwards and future compatibility.
442 **
443 ** Pkt size for allocating is data length +6 (for additional status
444 ** words, length and ctl!)
445 **
446 ** If odd size then last byte is included in this header.
447 */
448 numPages = ((length & 0xfffe) + 6);
449 numPages >>= 8; /* Divide by 256 */
wdenkfe8c2802002-11-03 00:38:21 +0000450
wdenkb56ddc62003-09-15 21:14:37 +0000451 if (numPages > 7) {
452 printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000453 return 0;
454 }
455
456 /* now, try to allocate the memory */
Ben Warren7194ab82009-10-04 22:37:03 -0700457 SMC_SELECT_BANK (dev, 2);
458 SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000459
wdenkdc7c9a12003-03-26 06:55:25 +0000460 /* FIXME: the ALLOC_INT bit never gets set *
wdenk42dfe7a2004-03-14 22:25:36 +0000461 * so the following will always give a *
462 * memory allocation error. *
463 * same code works in armboot though *
wdenkdc7c9a12003-03-26 06:55:25 +0000464 * -ro
465 */
466
wdenkfe8c2802002-11-03 00:38:21 +0000467again:
468 try++;
469 time_out = MEMORY_WAIT_TIME;
470 do {
Ben Warren7194ab82009-10-04 22:37:03 -0700471 status = SMC_inb (dev, SMC91111_INT_REG);
wdenkb56ddc62003-09-15 21:14:37 +0000472 if (status & IM_ALLOC_INT) {
wdenkfe8c2802002-11-03 00:38:21 +0000473 /* acknowledge the interrupt */
Ben Warren7194ab82009-10-04 22:37:03 -0700474 SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG);
wdenk8bde7f72003-06-27 21:31:46 +0000475 break;
wdenkfe8c2802002-11-03 00:38:21 +0000476 }
wdenkb56ddc62003-09-15 21:14:37 +0000477 } while (--time_out);
wdenkfe8c2802002-11-03 00:38:21 +0000478
wdenkb56ddc62003-09-15 21:14:37 +0000479 if (!time_out) {
480 PRINTK2 ("%s: memory allocation, try %d failed ...\n",
481 SMC_DEV_NAME, try);
482 if (try < SMC_ALLOC_MAX_TRY)
483 goto again;
484 else
485 return 0;
wdenkfe8c2802002-11-03 00:38:21 +0000486 }
487
wdenkb56ddc62003-09-15 21:14:37 +0000488 PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
489 SMC_DEV_NAME, try);
wdenkfe8c2802002-11-03 00:38:21 +0000490
wdenkb56ddc62003-09-15 21:14:37 +0000491 buf = (byte *) packet;
wdenkfe8c2802002-11-03 00:38:21 +0000492
493 /* If I get here, I _know_ there is a packet slot waiting for me */
Ben Warren7194ab82009-10-04 22:37:03 -0700494 packet_no = SMC_inb (dev, AR_REG);
wdenkb56ddc62003-09-15 21:14:37 +0000495 if (packet_no & AR_FAILED) {
wdenkfe8c2802002-11-03 00:38:21 +0000496 /* or isn't there? BAD CHIP! */
wdenkb56ddc62003-09-15 21:14:37 +0000497 printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000498 return 0;
499 }
500
501 /* we have a packet address, so tell the card to use it */
Ben Warren7194ab82009-10-04 22:37:03 -0700502 SMC_outb (dev, packet_no, PN_REG);
Simon Glass1c87dd72015-08-30 19:19:34 -0600503
wdenkb79a11c2004-03-25 15:14:43 +0000504 /* do not write new ptr value if Write data fifo not empty */
505 while ( saved_ptr & PTR_NOTEMPTY )
wdenk518e2e12004-03-25 14:59:05 +0000506 printf ("Write data fifo not empty!\n");
507
wdenkfe8c2802002-11-03 00:38:21 +0000508 /* point to the beginning of the packet */
Ben Warren7194ab82009-10-04 22:37:03 -0700509 SMC_outw (dev, PTR_AUTOINC, PTR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000510
wdenkb56ddc62003-09-15 21:14:37 +0000511 PRINTK3 ("%s: Trying to xmit packet of length %x\n",
512 SMC_DEV_NAME, length);
wdenkfe8c2802002-11-03 00:38:21 +0000513
514#if SMC_DEBUG > 2
wdenkb56ddc62003-09-15 21:14:37 +0000515 printf ("Transmitting Packet\n");
516 print_packet (buf, length);
wdenkfe8c2802002-11-03 00:38:21 +0000517#endif
518
519 /* send the packet length ( +6 for status, length and ctl byte )
wdenk8bde7f72003-06-27 21:31:46 +0000520 and the status word ( set to zeros ) */
wdenkfe8c2802002-11-03 00:38:21 +0000521#ifdef USE_32_BIT
Ben Warren7194ab82009-10-04 22:37:03 -0700522 SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000523#else
Ben Warren7194ab82009-10-04 22:37:03 -0700524 SMC_outw (dev, 0, SMC91111_DATA_REG);
wdenkb56ddc62003-09-15 21:14:37 +0000525 /* send the packet length ( +6 for status words, length, and ctl */
Ben Warren7194ab82009-10-04 22:37:03 -0700526 SMC_outw (dev, (length + 6), SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000527#endif
528
529 /* send the actual data
wdenkb56ddc62003-09-15 21:14:37 +0000530 . I _think_ it's faster to send the longs first, and then
531 . mop up by sending the last word. It depends heavily
wdenk42dfe7a2004-03-14 22:25:36 +0000532 . on alignment, at least on the 486. Maybe it would be
wdenkb56ddc62003-09-15 21:14:37 +0000533 . a good idea to check which is optimal? But that could take
534 . almost as much time as is saved?
535 */
wdenkfe8c2802002-11-03 00:38:21 +0000536#ifdef USE_32_BIT
Ben Warren7194ab82009-10-04 22:37:03 -0700537 SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2);
wdenkb56ddc62003-09-15 21:14:37 +0000538 if (length & 0x2)
Ben Warren7194ab82009-10-04 22:37:03 -0700539 SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))),
wdenkb56ddc62003-09-15 21:14:37 +0000540 SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000541#else
Ben Warren7194ab82009-10-04 22:37:03 -0700542 SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1);
wdenkfe8c2802002-11-03 00:38:21 +0000543#endif /* USE_32_BIT */
544
wdenk42dfe7a2004-03-14 22:25:36 +0000545 /* Send the last byte, if there is one. */
wdenkb56ddc62003-09-15 21:14:37 +0000546 if ((length & 1) == 0) {
Ben Warren7194ab82009-10-04 22:37:03 -0700547 SMC_outw (dev, 0, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000548 } else {
Ben Warren7194ab82009-10-04 22:37:03 -0700549 SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000550 }
551
552 /* and let the chipset deal with it */
Ben Warren7194ab82009-10-04 22:37:03 -0700553 SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000554
555 /* poll for TX INT */
Ben Warren7194ab82009-10-04 22:37:03 -0700556 /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */
wdenk518e2e12004-03-25 14:59:05 +0000557 /* poll for TX_EMPTY INT - autorelease enabled */
Ben Warren7194ab82009-10-04 22:37:03 -0700558 if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
wdenkfe8c2802002-11-03 00:38:21 +0000559 /* sending failed */
wdenkb56ddc62003-09-15 21:14:37 +0000560 PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000561
562 /* release packet */
wdenk518e2e12004-03-25 14:59:05 +0000563 /* no need to release, MMU does that now */
wdenkfe8c2802002-11-03 00:38:21 +0000564
wdenk8bde7f72003-06-27 21:31:46 +0000565 /* wait for MMU getting ready (low) */
Ben Warren7194ab82009-10-04 22:37:03 -0700566 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
wdenkb56ddc62003-09-15 21:14:37 +0000567 udelay (10);
wdenk8bde7f72003-06-27 21:31:46 +0000568 }
wdenkfe8c2802002-11-03 00:38:21 +0000569
wdenkb56ddc62003-09-15 21:14:37 +0000570 PRINTK2 ("MMU ready\n");
wdenkfe8c2802002-11-03 00:38:21 +0000571
572
573 return 0;
574 } else {
575 /* ack. int */
Ben Warren7194ab82009-10-04 22:37:03 -0700576 SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG);
wdenk518e2e12004-03-25 14:59:05 +0000577 /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
wdenkb56ddc62003-09-15 21:14:37 +0000578 PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
579 length);
wdenkfe8c2802002-11-03 00:38:21 +0000580
581 /* release packet */
wdenk518e2e12004-03-25 14:59:05 +0000582 /* no need to release, MMU does that now */
wdenkfe8c2802002-11-03 00:38:21 +0000583
wdenk8bde7f72003-06-27 21:31:46 +0000584 /* wait for MMU getting ready (low) */
Ben Warren7194ab82009-10-04 22:37:03 -0700585 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
wdenkb56ddc62003-09-15 21:14:37 +0000586 udelay (10);
wdenk8bde7f72003-06-27 21:31:46 +0000587 }
wdenkfe8c2802002-11-03 00:38:21 +0000588
wdenkb56ddc62003-09-15 21:14:37 +0000589 PRINTK2 ("MMU ready\n");
wdenkfe8c2802002-11-03 00:38:21 +0000590
591
592 }
593
wdenk518e2e12004-03-25 14:59:05 +0000594 /* restore previously saved registers */
Ben Warren7194ab82009-10-04 22:37:03 -0700595 SMC_outb( dev, saved_pnr, PN_REG );
Ben Warren7194ab82009-10-04 22:37:03 -0700596 SMC_outw( dev, saved_ptr, PTR_REG );
wdenk518e2e12004-03-25 14:59:05 +0000597
wdenkfe8c2802002-11-03 00:38:21 +0000598 return length;
599}
600
Thomas Chou1ca6d0d2010-10-06 09:16:10 +0800601static int smc_write_hwaddr(struct eth_device *dev)
602{
603 int i;
604
605 swap_to(ETHERNET);
606 SMC_SELECT_BANK (dev, 1);
607#ifdef USE_32_BIT
608 for (i = 0; i < 6; i += 2) {
609 word address;
610
611 address = dev->enetaddr[i + 1] << 8;
612 address |= dev->enetaddr[i];
613 SMC_outw(dev, address, (ADDR0_REG + i));
614 }
615#else
616 for (i = 0; i < 6; i++)
617 SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
618#endif
619 swap_to(FLASH);
620 return 0;
621}
622
wdenkfe8c2802002-11-03 00:38:21 +0000623/*
624 * Open and Initialize the board
625 *
626 * Set up everything, reset the card, etc ..
627 *
628 */
Ben Warren7194ab82009-10-04 22:37:03 -0700629static int smc_init(struct eth_device *dev, bd_t *bd)
wdenkfe8c2802002-11-03 00:38:21 +0000630{
Ben Warren7194ab82009-10-04 22:37:03 -0700631 swap_to(ETHERNET);
632
633 PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000634
635 /* reset the hardware */
Ben Warren7194ab82009-10-04 22:37:03 -0700636 smc_reset (dev);
637 smc_enable (dev);
wdenkfe8c2802002-11-03 00:38:21 +0000638
639 /* Configure the PHY */
640#ifndef CONFIG_SMC91111_EXT_PHY
Ben Warren7194ab82009-10-04 22:37:03 -0700641 smc_phy_configure (dev);
wdenkfe8c2802002-11-03 00:38:21 +0000642#endif
643
wdenkfe8c2802002-11-03 00:38:21 +0000644 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
Ben Warren7194ab82009-10-04 22:37:03 -0700645/* SMC_SELECT_BANK(dev, 0); */
646/* SMC_outw(dev, 0, RPC_REG); */
wdenkfe8c2802002-11-03 00:38:21 +0000647
Ben Warren7194ab82009-10-04 22:37:03 -0700648 printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
649
wdenkfe8c2802002-11-03 00:38:21 +0000650 return 0;
651}
652
wdenkfe8c2802002-11-03 00:38:21 +0000653/*-------------------------------------------------------------
654 .
655 . smc_rcv - receive a packet from the card
656 .
657 . There is ( at least ) a packet waiting to be read from
658 . chip-memory.
659 .
660 . o Read the status
661 . o If an error, record it
662 . o otherwise, read in the packet
663 --------------------------------------------------------------
664*/
Ben Warren7194ab82009-10-04 22:37:03 -0700665static int smc_rcv(struct eth_device *dev)
wdenkfe8c2802002-11-03 00:38:21 +0000666{
wdenk42dfe7a2004-03-14 22:25:36 +0000667 int packet_number;
wdenkfe8c2802002-11-03 00:38:21 +0000668 word status;
669 word packet_length;
wdenk42dfe7a2004-03-14 22:25:36 +0000670 int is_error = 0;
wdenkfe8c2802002-11-03 00:38:21 +0000671#ifdef USE_32_BIT
672 dword stat_len;
673#endif
wdenk518e2e12004-03-25 14:59:05 +0000674 byte saved_pnr;
675 word saved_ptr;
wdenkfe8c2802002-11-03 00:38:21 +0000676
Ben Warren7194ab82009-10-04 22:37:03 -0700677 SMC_SELECT_BANK(dev, 2);
wdenk518e2e12004-03-25 14:59:05 +0000678 /* save PTR and PTR registers */
Ben Warren7194ab82009-10-04 22:37:03 -0700679 saved_pnr = SMC_inb( dev, PN_REG );
680 saved_ptr = SMC_inw( dev, PTR_REG );
wdenk518e2e12004-03-25 14:59:05 +0000681
Ben Warren7194ab82009-10-04 22:37:03 -0700682 packet_number = SMC_inw( dev, RXFIFO_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000683
684 if ( packet_number & RXFIFO_REMPTY ) {
685
686 return 0;
687 }
688
wdenkf39748a2004-06-09 13:37:52 +0000689 PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000690 /* start reading from the start of the packet */
Ben Warren7194ab82009-10-04 22:37:03 -0700691 SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000692
693 /* First two words are status and packet_length */
694#ifdef USE_32_BIT
Ben Warren7194ab82009-10-04 22:37:03 -0700695 stat_len = SMC_inl(dev, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000696 status = stat_len & 0xffff;
697 packet_length = stat_len >> 16;
698#else
Ben Warren7194ab82009-10-04 22:37:03 -0700699 status = SMC_inw( dev, SMC91111_DATA_REG );
700 packet_length = SMC_inw( dev, SMC91111_DATA_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000701#endif
702
703 packet_length &= 0x07ff; /* mask off top bits */
704
705 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
706
707 if ( !(status & RS_ERRORS ) ){
708 /* Adjust for having already read the first two words */
709 packet_length -= 4; /*4; */
710
711
wdenkfe8c2802002-11-03 00:38:21 +0000712 /* set odd length for bug in LAN91C111, */
713 /* which never sets RS_ODDFRAME */
714 /* TODO ? */
715
716
717#ifdef USE_32_BIT
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500718 PRINTK3(" Reading %d dwords (and %d bytes)\n",
wdenkfe8c2802002-11-03 00:38:21 +0000719 packet_length >> 2, packet_length & 3 );
720 /* QUESTION: Like in the TX routine, do I want
721 to send the DWORDs or the bytes first, or some
722 mixture. A mixture might improve already slow PIO
wdenk42dfe7a2004-03-14 22:25:36 +0000723 performance */
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500724 SMC_insl(dev, SMC91111_DATA_REG, net_rx_packets[0],
725 packet_length >> 2);
wdenkfe8c2802002-11-03 00:38:21 +0000726 /* read the left over bytes */
727 if (packet_length & 3) {
728 int i;
729
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500730 byte *tail = (byte *)(net_rx_packets[0] +
Ben Warren7194ab82009-10-04 22:37:03 -0700731 (packet_length & ~3));
732 dword leftover = SMC_inl(dev, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000733 for (i=0; i<(packet_length & 3); i++)
734 *tail++ = (byte) (leftover >> (8*i)) & 0xff;
735 }
736#else
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500737 PRINTK3(" Reading %d words and %d byte(s)\n",
wdenkfe8c2802002-11-03 00:38:21 +0000738 (packet_length >> 1 ), packet_length & 1 );
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500739 SMC_insw(dev, SMC91111_DATA_REG , net_rx_packets[0],
740 packet_length >> 1);
wdenkfe8c2802002-11-03 00:38:21 +0000741
742#endif /* USE_32_BIT */
743
744#if SMC_DEBUG > 2
745 printf("Receiving Packet\n");
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500746 print_packet(net_rx_packets[0], packet_length);
wdenkfe8c2802002-11-03 00:38:21 +0000747#endif
748 } else {
749 /* error ... */
750 /* TODO ? */
751 is_error = 1;
752 }
753
Ben Warren7194ab82009-10-04 22:37:03 -0700754 while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
wdenkfe8c2802002-11-03 00:38:21 +0000755 udelay(1); /* Wait until not busy */
756
757 /* error or good, tell the card to get rid of this packet */
Ben Warren7194ab82009-10-04 22:37:03 -0700758 SMC_outw( dev, MC_RELEASE, MMU_CMD_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000759
Ben Warren7194ab82009-10-04 22:37:03 -0700760 while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
wdenkfe8c2802002-11-03 00:38:21 +0000761 udelay(1); /* Wait until not busy */
762
wdenk518e2e12004-03-25 14:59:05 +0000763 /* restore saved registers */
Ben Warren7194ab82009-10-04 22:37:03 -0700764 SMC_outb( dev, saved_pnr, PN_REG );
Ben Warren7194ab82009-10-04 22:37:03 -0700765 SMC_outw( dev, saved_ptr, PTR_REG );
wdenk518e2e12004-03-25 14:59:05 +0000766
wdenkfe8c2802002-11-03 00:38:21 +0000767 if (!is_error) {
768 /* Pass the packet up to the protocol layers. */
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500769 net_process_received_packet(net_rx_packets[0], packet_length);
wdenkfe8c2802002-11-03 00:38:21 +0000770 return packet_length;
771 } else {
772 return 0;
773 }
774
775}
776
777
wdenkfe8c2802002-11-03 00:38:21 +0000778#if 0
779/*------------------------------------------------------------
780 . Modify a bit in the LAN91C111 register set
781 .-------------------------------------------------------------*/
Ben Warren7194ab82009-10-04 22:37:03 -0700782static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg,
wdenkfe8c2802002-11-03 00:38:21 +0000783 unsigned int bit, int val)
784{
785 word regval;
786
Ben Warren7194ab82009-10-04 22:37:03 -0700787 SMC_SELECT_BANK( dev, bank );
wdenkfe8c2802002-11-03 00:38:21 +0000788
Ben Warren7194ab82009-10-04 22:37:03 -0700789 regval = SMC_inw( dev, reg );
wdenkfe8c2802002-11-03 00:38:21 +0000790 if (val)
791 regval |= bit;
792 else
793 regval &= ~bit;
794
Ben Warren7194ab82009-10-04 22:37:03 -0700795 SMC_outw( dev, regval, 0 );
wdenkfe8c2802002-11-03 00:38:21 +0000796 return(regval);
797}
798
799
800/*------------------------------------------------------------
801 . Retrieve a bit in the LAN91C111 register set
802 .-------------------------------------------------------------*/
Ben Warren7194ab82009-10-04 22:37:03 -0700803static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit)
wdenkfe8c2802002-11-03 00:38:21 +0000804{
Ben Warren7194ab82009-10-04 22:37:03 -0700805 SMC_SELECT_BANK( dev, bank );
806 if ( SMC_inw( dev, reg ) & bit)
wdenkfe8c2802002-11-03 00:38:21 +0000807 return(1);
808 else
809 return(0);
810}
811
812
813/*------------------------------------------------------------
814 . Modify a LAN91C111 register (word access only)
815 .-------------------------------------------------------------*/
Ben Warren7194ab82009-10-04 22:37:03 -0700816static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val)
wdenkfe8c2802002-11-03 00:38:21 +0000817{
Ben Warren7194ab82009-10-04 22:37:03 -0700818 SMC_SELECT_BANK( dev, bank );
819 SMC_outw( dev, val, reg );
wdenkfe8c2802002-11-03 00:38:21 +0000820}
821
822
823/*------------------------------------------------------------
824 . Retrieve a LAN91C111 register (word access only)
825 .-------------------------------------------------------------*/
Ben Warren7194ab82009-10-04 22:37:03 -0700826static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg)
wdenkfe8c2802002-11-03 00:38:21 +0000827{
Ben Warren7194ab82009-10-04 22:37:03 -0700828 SMC_SELECT_BANK( dev, bank );
829 return(SMC_inw( dev, reg ));
wdenkfe8c2802002-11-03 00:38:21 +0000830}
831
832#endif /* 0 */
833
834/*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
835
836#if (SMC_DEBUG > 2 )
837
838/*------------------------------------------------------------
839 . Debugging function for viewing MII Management serial bitstream
840 .-------------------------------------------------------------*/
wdenkb56ddc62003-09-15 21:14:37 +0000841static void smc_dump_mii_stream (byte * bits, int size)
wdenkfe8c2802002-11-03 00:38:21 +0000842{
843 int i;
844
wdenkb56ddc62003-09-15 21:14:37 +0000845 printf ("BIT#:");
846 for (i = 0; i < size; ++i) {
847 printf ("%d", i % 10);
848 }
wdenkfe8c2802002-11-03 00:38:21 +0000849
wdenkb56ddc62003-09-15 21:14:37 +0000850 printf ("\nMDOE:");
851 for (i = 0; i < size; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000852 if (bits[i] & MII_MDOE)
wdenkb56ddc62003-09-15 21:14:37 +0000853 printf ("1");
wdenkfe8c2802002-11-03 00:38:21 +0000854 else
wdenkb56ddc62003-09-15 21:14:37 +0000855 printf ("0");
856 }
wdenkfe8c2802002-11-03 00:38:21 +0000857
wdenkb56ddc62003-09-15 21:14:37 +0000858 printf ("\nMDO :");
859 for (i = 0; i < size; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000860 if (bits[i] & MII_MDO)
wdenkb56ddc62003-09-15 21:14:37 +0000861 printf ("1");
wdenkfe8c2802002-11-03 00:38:21 +0000862 else
wdenkb56ddc62003-09-15 21:14:37 +0000863 printf ("0");
864 }
wdenkfe8c2802002-11-03 00:38:21 +0000865
wdenkb56ddc62003-09-15 21:14:37 +0000866 printf ("\nMDI :");
867 for (i = 0; i < size; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000868 if (bits[i] & MII_MDI)
wdenkb56ddc62003-09-15 21:14:37 +0000869 printf ("1");
wdenkfe8c2802002-11-03 00:38:21 +0000870 else
wdenkb56ddc62003-09-15 21:14:37 +0000871 printf ("0");
872 }
wdenkfe8c2802002-11-03 00:38:21 +0000873
wdenkb56ddc62003-09-15 21:14:37 +0000874 printf ("\n");
wdenkfe8c2802002-11-03 00:38:21 +0000875}
876#endif
877
878/*------------------------------------------------------------
879 . Reads a register from the MII Management serial interface
880 .-------------------------------------------------------------*/
881#ifndef CONFIG_SMC91111_EXT_PHY
Ben Warren7194ab82009-10-04 22:37:03 -0700882static word smc_read_phy_register (struct eth_device *dev, byte phyreg)
wdenkfe8c2802002-11-03 00:38:21 +0000883{
884 int oldBank;
885 int i;
886 byte mask;
887 word mii_reg;
888 byte bits[64];
889 int clk_idx = 0;
890 int input_idx;
891 word phydata;
892 byte phyaddr = SMC_PHY_ADDR;
893
894 /* 32 consecutive ones on MDO to establish sync */
895 for (i = 0; i < 32; ++i)
896 bits[clk_idx++] = MII_MDOE | MII_MDO;
897
898 /* Start code <01> */
899 bits[clk_idx++] = MII_MDOE;
900 bits[clk_idx++] = MII_MDOE | MII_MDO;
901
902 /* Read command <10> */
903 bits[clk_idx++] = MII_MDOE | MII_MDO;
904 bits[clk_idx++] = MII_MDOE;
905
906 /* Output the PHY address, msb first */
wdenkb56ddc62003-09-15 21:14:37 +0000907 mask = (byte) 0x10;
908 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000909 if (phyaddr & mask)
910 bits[clk_idx++] = MII_MDOE | MII_MDO;
911 else
912 bits[clk_idx++] = MII_MDOE;
913
914 /* Shift to next lowest bit */
915 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +0000916 }
wdenkfe8c2802002-11-03 00:38:21 +0000917
918 /* Output the phy register number, msb first */
wdenkb56ddc62003-09-15 21:14:37 +0000919 mask = (byte) 0x10;
920 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000921 if (phyreg & mask)
922 bits[clk_idx++] = MII_MDOE | MII_MDO;
923 else
924 bits[clk_idx++] = MII_MDOE;
925
926 /* Shift to next lowest bit */
927 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +0000928 }
wdenkfe8c2802002-11-03 00:38:21 +0000929
930 /* Tristate and turnaround (2 bit times) */
931 bits[clk_idx++] = 0;
932 /*bits[clk_idx++] = 0; */
933
934 /* Input starts at this bit time */
935 input_idx = clk_idx;
936
937 /* Will input 16 bits */
938 for (i = 0; i < 16; ++i)
939 bits[clk_idx++] = 0;
940
941 /* Final clock bit */
942 bits[clk_idx++] = 0;
943
944 /* Save the current bank */
Ben Warren7194ab82009-10-04 22:37:03 -0700945 oldBank = SMC_inw (dev, BANK_SELECT);
wdenkfe8c2802002-11-03 00:38:21 +0000946
947 /* Select bank 3 */
Ben Warren7194ab82009-10-04 22:37:03 -0700948 SMC_SELECT_BANK (dev, 3);
wdenkfe8c2802002-11-03 00:38:21 +0000949
950 /* Get the current MII register value */
Ben Warren7194ab82009-10-04 22:37:03 -0700951 mii_reg = SMC_inw (dev, MII_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000952
953 /* Turn off all MII Interface bits */
wdenkb56ddc62003-09-15 21:14:37 +0000954 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
wdenkfe8c2802002-11-03 00:38:21 +0000955
956 /* Clock all 64 cycles */
wdenkb56ddc62003-09-15 21:14:37 +0000957 for (i = 0; i < sizeof bits; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000958 /* Clock Low - output data */
Ben Warren7194ab82009-10-04 22:37:03 -0700959 SMC_outw (dev, mii_reg | bits[i], MII_REG);
wdenkb56ddc62003-09-15 21:14:37 +0000960 udelay (SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +0000961
962
963 /* Clock Hi - input data */
Ben Warren7194ab82009-10-04 22:37:03 -0700964 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
wdenkb56ddc62003-09-15 21:14:37 +0000965 udelay (SMC_PHY_CLOCK_DELAY);
Ben Warren7194ab82009-10-04 22:37:03 -0700966 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
wdenkb56ddc62003-09-15 21:14:37 +0000967 }
wdenkfe8c2802002-11-03 00:38:21 +0000968
969 /* Return to idle state */
970 /* Set clock to low, data to low, and output tristated */
Ben Warren7194ab82009-10-04 22:37:03 -0700971 SMC_outw (dev, mii_reg, MII_REG);
wdenkb56ddc62003-09-15 21:14:37 +0000972 udelay (SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +0000973
974 /* Restore original bank select */
Ben Warren7194ab82009-10-04 22:37:03 -0700975 SMC_SELECT_BANK (dev, oldBank);
wdenkfe8c2802002-11-03 00:38:21 +0000976
977 /* Recover input data */
978 phydata = 0;
wdenkb56ddc62003-09-15 21:14:37 +0000979 for (i = 0; i < 16; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000980 phydata <<= 1;
981
982 if (bits[input_idx++] & MII_MDI)
983 phydata |= 0x0001;
wdenkb56ddc62003-09-15 21:14:37 +0000984 }
wdenkfe8c2802002-11-03 00:38:21 +0000985
986#if (SMC_DEBUG > 2 )
wdenkb56ddc62003-09-15 21:14:37 +0000987 printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
wdenkfe8c2802002-11-03 00:38:21 +0000988 phyaddr, phyreg, phydata);
wdenkb56ddc62003-09-15 21:14:37 +0000989 smc_dump_mii_stream (bits, sizeof bits);
wdenkfe8c2802002-11-03 00:38:21 +0000990#endif
991
wdenkb56ddc62003-09-15 21:14:37 +0000992 return (phydata);
wdenkfe8c2802002-11-03 00:38:21 +0000993}
994
995
996/*------------------------------------------------------------
997 . Writes a register to the MII Management serial interface
998 .-------------------------------------------------------------*/
Ben Warren7194ab82009-10-04 22:37:03 -0700999static void smc_write_phy_register (struct eth_device *dev, byte phyreg,
1000 word phydata)
wdenkfe8c2802002-11-03 00:38:21 +00001001{
1002 int oldBank;
1003 int i;
1004 word mask;
1005 word mii_reg;
1006 byte bits[65];
1007 int clk_idx = 0;
1008 byte phyaddr = SMC_PHY_ADDR;
1009
1010 /* 32 consecutive ones on MDO to establish sync */
1011 for (i = 0; i < 32; ++i)
1012 bits[clk_idx++] = MII_MDOE | MII_MDO;
1013
1014 /* Start code <01> */
1015 bits[clk_idx++] = MII_MDOE;
1016 bits[clk_idx++] = MII_MDOE | MII_MDO;
1017
1018 /* Write command <01> */
1019 bits[clk_idx++] = MII_MDOE;
1020 bits[clk_idx++] = MII_MDOE | MII_MDO;
1021
1022 /* Output the PHY address, msb first */
wdenkb56ddc62003-09-15 21:14:37 +00001023 mask = (byte) 0x10;
1024 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001025 if (phyaddr & mask)
1026 bits[clk_idx++] = MII_MDOE | MII_MDO;
1027 else
1028 bits[clk_idx++] = MII_MDOE;
1029
1030 /* Shift to next lowest bit */
1031 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +00001032 }
wdenkfe8c2802002-11-03 00:38:21 +00001033
1034 /* Output the phy register number, msb first */
wdenkb56ddc62003-09-15 21:14:37 +00001035 mask = (byte) 0x10;
1036 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001037 if (phyreg & mask)
1038 bits[clk_idx++] = MII_MDOE | MII_MDO;
1039 else
1040 bits[clk_idx++] = MII_MDOE;
1041
1042 /* Shift to next lowest bit */
1043 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +00001044 }
wdenkfe8c2802002-11-03 00:38:21 +00001045
1046 /* Tristate and turnaround (2 bit times) */
1047 bits[clk_idx++] = 0;
1048 bits[clk_idx++] = 0;
1049
1050 /* Write out 16 bits of data, msb first */
1051 mask = 0x8000;
wdenkb56ddc62003-09-15 21:14:37 +00001052 for (i = 0; i < 16; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001053 if (phydata & mask)
1054 bits[clk_idx++] = MII_MDOE | MII_MDO;
1055 else
1056 bits[clk_idx++] = MII_MDOE;
1057
1058 /* Shift to next lowest bit */
1059 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +00001060 }
wdenkfe8c2802002-11-03 00:38:21 +00001061
1062 /* Final clock bit (tristate) */
1063 bits[clk_idx++] = 0;
1064
1065 /* Save the current bank */
Ben Warren7194ab82009-10-04 22:37:03 -07001066 oldBank = SMC_inw (dev, BANK_SELECT);
wdenkfe8c2802002-11-03 00:38:21 +00001067
1068 /* Select bank 3 */
Ben Warren7194ab82009-10-04 22:37:03 -07001069 SMC_SELECT_BANK (dev, 3);
wdenkfe8c2802002-11-03 00:38:21 +00001070
1071 /* Get the current MII register value */
Ben Warren7194ab82009-10-04 22:37:03 -07001072 mii_reg = SMC_inw (dev, MII_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001073
1074 /* Turn off all MII Interface bits */
wdenkb56ddc62003-09-15 21:14:37 +00001075 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
wdenkfe8c2802002-11-03 00:38:21 +00001076
1077 /* Clock all cycles */
wdenkb56ddc62003-09-15 21:14:37 +00001078 for (i = 0; i < sizeof bits; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001079 /* Clock Low - output data */
Ben Warren7194ab82009-10-04 22:37:03 -07001080 SMC_outw (dev, mii_reg | bits[i], MII_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001081 udelay (SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +00001082
1083
1084 /* Clock Hi - input data */
Ben Warren7194ab82009-10-04 22:37:03 -07001085 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001086 udelay (SMC_PHY_CLOCK_DELAY);
Ben Warren7194ab82009-10-04 22:37:03 -07001087 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
wdenkb56ddc62003-09-15 21:14:37 +00001088 }
wdenkfe8c2802002-11-03 00:38:21 +00001089
1090 /* Return to idle state */
1091 /* Set clock to low, data to low, and output tristated */
Ben Warren7194ab82009-10-04 22:37:03 -07001092 SMC_outw (dev, mii_reg, MII_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001093 udelay (SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +00001094
1095 /* Restore original bank select */
Ben Warren7194ab82009-10-04 22:37:03 -07001096 SMC_SELECT_BANK (dev, oldBank);
wdenkfe8c2802002-11-03 00:38:21 +00001097
1098#if (SMC_DEBUG > 2 )
wdenkb56ddc62003-09-15 21:14:37 +00001099 printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
wdenkfe8c2802002-11-03 00:38:21 +00001100 phyaddr, phyreg, phydata);
wdenkb56ddc62003-09-15 21:14:37 +00001101 smc_dump_mii_stream (bits, sizeof bits);
wdenkfe8c2802002-11-03 00:38:21 +00001102#endif
1103}
1104#endif /* !CONFIG_SMC91111_EXT_PHY */
1105
1106
wdenkfe8c2802002-11-03 00:38:21 +00001107/*------------------------------------------------------------
wdenkfe8c2802002-11-03 00:38:21 +00001108 . Configures the specified PHY using Autonegotiation. Calls
1109 . smc_phy_fixed() if the user has requested a certain config.
1110 .-------------------------------------------------------------*/
1111#ifndef CONFIG_SMC91111_EXT_PHY
Ben Warren7194ab82009-10-04 22:37:03 -07001112static void smc_phy_configure (struct eth_device *dev)
wdenkfe8c2802002-11-03 00:38:21 +00001113{
1114 int timeout;
wdenkb56ddc62003-09-15 21:14:37 +00001115 word my_phy_caps; /* My PHY capabilities */
1116 word my_ad_caps; /* My Advertised capabilities */
1117 word status = 0; /*;my status = 0 */
wdenkfe8c2802002-11-03 00:38:21 +00001118
wdenkf39748a2004-06-09 13:37:52 +00001119 PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001120
wdenkfe8c2802002-11-03 00:38:21 +00001121 /* Reset the PHY, setting all other bits to zero */
Ben Warren7194ab82009-10-04 22:37:03 -07001122 smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST);
wdenkfe8c2802002-11-03 00:38:21 +00001123
1124 /* Wait for the reset to complete, or time out */
wdenkb56ddc62003-09-15 21:14:37 +00001125 timeout = 6; /* Wait up to 3 seconds */
1126 while (timeout--) {
Ben Warren7194ab82009-10-04 22:37:03 -07001127 if (!(smc_read_phy_register (dev, PHY_CNTL_REG)
wdenkb56ddc62003-09-15 21:14:37 +00001128 & PHY_CNTL_RST)) {
wdenkfe8c2802002-11-03 00:38:21 +00001129 /* reset complete */
1130 break;
wdenkfe8c2802002-11-03 00:38:21 +00001131 }
1132
Mike Frysinger65029492012-03-05 13:46:51 +00001133 mdelay(500); /* wait 500 millisecs */
wdenkb56ddc62003-09-15 21:14:37 +00001134 }
1135
1136 if (timeout < 1) {
1137 printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001138 goto smc_phy_configure_exit;
wdenkb56ddc62003-09-15 21:14:37 +00001139 }
wdenkfe8c2802002-11-03 00:38:21 +00001140
1141 /* Read PHY Register 18, Status Output */
1142 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
1143
1144 /* Enable PHY Interrupts (for register 18) */
1145 /* Interrupts listed here are disabled */
Ben Warren7194ab82009-10-04 22:37:03 -07001146 smc_write_phy_register (dev, PHY_MASK_REG, 0xffff);
wdenkfe8c2802002-11-03 00:38:21 +00001147
1148 /* Configure the Receive/Phy Control register */
Ben Warren7194ab82009-10-04 22:37:03 -07001149 SMC_SELECT_BANK (dev, 0);
1150 SMC_outw (dev, RPC_DEFAULT, RPC_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001151
1152 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
Ben Warren7194ab82009-10-04 22:37:03 -07001153 my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001154 my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
wdenkfe8c2802002-11-03 00:38:21 +00001155
1156 if (my_phy_caps & PHY_STAT_CAP_T4)
1157 my_ad_caps |= PHY_AD_T4;
1158
1159 if (my_phy_caps & PHY_STAT_CAP_TXF)
1160 my_ad_caps |= PHY_AD_TX_FDX;
1161
1162 if (my_phy_caps & PHY_STAT_CAP_TXH)
1163 my_ad_caps |= PHY_AD_TX_HDX;
1164
1165 if (my_phy_caps & PHY_STAT_CAP_TF)
1166 my_ad_caps |= PHY_AD_10_FDX;
1167
1168 if (my_phy_caps & PHY_STAT_CAP_TH)
1169 my_ad_caps |= PHY_AD_10_HDX;
1170
1171 /* Update our Auto-Neg Advertisement Register */
Ben Warren7194ab82009-10-04 22:37:03 -07001172 smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps);
wdenkfe8c2802002-11-03 00:38:21 +00001173
wdenk518e2e12004-03-25 14:59:05 +00001174 /* Read the register back. Without this, it appears that when */
1175 /* auto-negotiation is restarted, sometimes it isn't ready and */
1176 /* the link does not come up. */
Ben Warren7194ab82009-10-04 22:37:03 -07001177 smc_read_phy_register(dev, PHY_AD_REG);
wdenk518e2e12004-03-25 14:59:05 +00001178
wdenkf39748a2004-06-09 13:37:52 +00001179 PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
1180 PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
wdenkfe8c2802002-11-03 00:38:21 +00001181
1182 /* Restart auto-negotiation process in order to advertise my caps */
Ben Warren7194ab82009-10-04 22:37:03 -07001183 smc_write_phy_register (dev, PHY_CNTL_REG,
wdenkb56ddc62003-09-15 21:14:37 +00001184 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
wdenkfe8c2802002-11-03 00:38:21 +00001185
1186 /* Wait for the auto-negotiation to complete. This may take from */
1187 /* 2 to 3 seconds. */
1188 /* Wait for the reset to complete, or time out */
wdenkf39748a2004-06-09 13:37:52 +00001189 timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
wdenkb56ddc62003-09-15 21:14:37 +00001190 while (timeout--) {
wdenkf39748a2004-06-09 13:37:52 +00001191
Ben Warren7194ab82009-10-04 22:37:03 -07001192 status = smc_read_phy_register (dev, PHY_STAT_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001193 if (status & PHY_STAT_ANEG_ACK) {
wdenkfe8c2802002-11-03 00:38:21 +00001194 /* auto-negotiate complete */
1195 break;
wdenkb56ddc62003-09-15 21:14:37 +00001196 }
wdenkfe8c2802002-11-03 00:38:21 +00001197
Mike Frysinger65029492012-03-05 13:46:51 +00001198 mdelay(500); /* wait 500 millisecs */
wdenkfe8c2802002-11-03 00:38:21 +00001199
1200 /* Restart auto-negotiation if remote fault */
wdenkb56ddc62003-09-15 21:14:37 +00001201 if (status & PHY_STAT_REM_FLT) {
wdenkf39748a2004-06-09 13:37:52 +00001202 printf ("%s: PHY remote fault detected\n",
wdenkb56ddc62003-09-15 21:14:37 +00001203 SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001204
1205 /* Restart auto-negotiation */
wdenkf39748a2004-06-09 13:37:52 +00001206 printf ("%s: PHY restarting auto-negotiation\n",
wdenkfe8c2802002-11-03 00:38:21 +00001207 SMC_DEV_NAME);
Ben Warren7194ab82009-10-04 22:37:03 -07001208 smc_write_phy_register (dev, PHY_CNTL_REG,
wdenkb56ddc62003-09-15 21:14:37 +00001209 PHY_CNTL_ANEG_EN |
1210 PHY_CNTL_ANEG_RST |
1211 PHY_CNTL_SPEED |
1212 PHY_CNTL_DPLX);
wdenkfe8c2802002-11-03 00:38:21 +00001213 }
wdenkb56ddc62003-09-15 21:14:37 +00001214 }
wdenkfe8c2802002-11-03 00:38:21 +00001215
wdenkb56ddc62003-09-15 21:14:37 +00001216 if (timeout < 1) {
wdenkf39748a2004-06-09 13:37:52 +00001217 printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME);
wdenkb56ddc62003-09-15 21:14:37 +00001218 }
wdenkfe8c2802002-11-03 00:38:21 +00001219
1220 /* Fail if we detected an auto-negotiate remote fault */
wdenkb56ddc62003-09-15 21:14:37 +00001221 if (status & PHY_STAT_REM_FLT) {
wdenkf39748a2004-06-09 13:37:52 +00001222 printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME);
wdenkb56ddc62003-09-15 21:14:37 +00001223 }
wdenkfe8c2802002-11-03 00:38:21 +00001224
1225 /* Re-Configure the Receive/Phy Control register */
Ben Warren7194ab82009-10-04 22:37:03 -07001226 SMC_outw (dev, RPC_DEFAULT, RPC_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001227
wdenk26238132004-07-09 22:51:01 +00001228smc_phy_configure_exit: ;
wdenkfe8c2802002-11-03 00:38:21 +00001229
1230}
1231#endif /* !CONFIG_SMC91111_EXT_PHY */
1232
1233
1234#if SMC_DEBUG > 2
1235static void print_packet( byte * buf, int length )
1236{
wdenk8bde7f72003-06-27 21:31:46 +00001237 int i;
1238 int remainder;
1239 int lines;
wdenkfe8c2802002-11-03 00:38:21 +00001240
wdenk8bde7f72003-06-27 21:31:46 +00001241 printf("Packet of length %d \n", length );
wdenkfe8c2802002-11-03 00:38:21 +00001242
1243#if SMC_DEBUG > 3
wdenk8bde7f72003-06-27 21:31:46 +00001244 lines = length / 16;
1245 remainder = length % 16;
wdenkfe8c2802002-11-03 00:38:21 +00001246
wdenk8bde7f72003-06-27 21:31:46 +00001247 for ( i = 0; i < lines ; i ++ ) {
1248 int cur;
wdenkfe8c2802002-11-03 00:38:21 +00001249
wdenk8bde7f72003-06-27 21:31:46 +00001250 for ( cur = 0; cur < 8; cur ++ ) {
1251 byte a, b;
wdenkfe8c2802002-11-03 00:38:21 +00001252
wdenk8bde7f72003-06-27 21:31:46 +00001253 a = *(buf ++ );
1254 b = *(buf ++ );
1255 printf("%02x%02x ", a, b );
1256 }
1257 printf("\n");
1258 }
1259 for ( i = 0; i < remainder/2 ; i++ ) {
1260 byte a, b;
wdenkfe8c2802002-11-03 00:38:21 +00001261
wdenk8bde7f72003-06-27 21:31:46 +00001262 a = *(buf ++ );
1263 b = *(buf ++ );
1264 printf("%02x%02x ", a, b );
1265 }
1266 printf("\n");
wdenkfe8c2802002-11-03 00:38:21 +00001267#endif
wdenkfe8c2802002-11-03 00:38:21 +00001268}
1269#endif
1270
Ben Warren7194ab82009-10-04 22:37:03 -07001271int smc91111_initialize(u8 dev_num, int base_addr)
wdenk0b97ab12003-06-19 23:58:30 +00001272{
Ben Warren7194ab82009-10-04 22:37:03 -07001273 struct smc91111_priv *priv;
1274 struct eth_device *dev;
wdenk3d3befa2004-03-14 15:06:13 +00001275 int i;
wdenkf39748a2004-06-09 13:37:52 +00001276
Ben Warren7194ab82009-10-04 22:37:03 -07001277 priv = malloc(sizeof(*priv));
1278 if (!priv)
1279 return 0;
1280 dev = malloc(sizeof(*dev));
1281 if (!dev) {
1282 free(priv);
1283 return 0;
wdenkb56ddc62003-09-15 21:14:37 +00001284 }
wdenkf39748a2004-06-09 13:37:52 +00001285
Thomas Chou1ca6d0d2010-10-06 09:16:10 +08001286 memset(dev, 0, sizeof(*dev));
Ben Warren7194ab82009-10-04 22:37:03 -07001287 priv->dev_num = dev_num;
1288 dev->priv = priv;
1289 dev->iobase = base_addr;
1290
1291 swap_to(ETHERNET);
1292 SMC_SELECT_BANK(dev, 1);
1293 for (i = 0; i < 6; ++i)
1294 dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i));
1295 swap_to(FLASH);
1296
1297 dev->init = smc_init;
1298 dev->halt = smc_halt;
1299 dev->send = smc_send;
1300 dev->recv = smc_rcv;
Thomas Chou1ca6d0d2010-10-06 09:16:10 +08001301 dev->write_hwaddr = smc_write_hwaddr;
Ben Warren7194ab82009-10-04 22:37:03 -07001302 sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);
1303
1304 eth_register(dev);
1305 return 0;
wdenk0b97ab12003-06-19 23:58:30 +00001306}