Simon Glass | 3a1a18f | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <mmc.h> |
| 9 | #include <pci_ids.h> |
Bin Meng | fe3fbd3 | 2015-07-30 03:49:18 -0700 | [diff] [blame] | 10 | #include <asm/irq.h> |
Simon Glass | 3a1a18f | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 11 | #include <asm/post.h> |
Simon Glass | 46f8efe | 2015-08-10 07:05:10 -0600 | [diff] [blame^] | 12 | #include <asm/fsp/fsp_support.h> |
Simon Glass | 3a1a18f | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 13 | |
| 14 | static struct pci_device_id mmc_supported[] = { |
| 15 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO }, |
| 16 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD }, |
| 17 | }; |
| 18 | |
| 19 | int cpu_mmc_init(bd_t *bis) |
| 20 | { |
Simon Glass | 3a1a18f | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 21 | return pci_mmc_init("ValleyView SDHCI", mmc_supported, |
| 22 | ARRAY_SIZE(mmc_supported)); |
| 23 | } |
| 24 | |
Simon Glass | b430258 | 2015-08-04 12:34:02 -0600 | [diff] [blame] | 25 | #ifndef CONFIG_EFI_APP |
Simon Glass | 3a1a18f | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 26 | int arch_cpu_init(void) |
| 27 | { |
| 28 | int ret; |
| 29 | |
| 30 | post_code(POST_CPU_INIT); |
| 31 | #ifdef CONFIG_SYS_X86_TSC_TIMER |
| 32 | timer_set_base(rdtsc()); |
| 33 | #endif |
| 34 | |
| 35 | ret = x86_cpu_init_f(); |
| 36 | if (ret) |
| 37 | return ret; |
| 38 | |
| 39 | return 0; |
| 40 | } |
Bin Meng | fe3fbd3 | 2015-07-30 03:49:18 -0700 | [diff] [blame] | 41 | |
| 42 | int arch_misc_init(void) |
| 43 | { |
Simon Glass | 46f8efe | 2015-08-10 07:05:10 -0600 | [diff] [blame^] | 44 | int ret; |
| 45 | |
| 46 | ret = pirq_init(); |
| 47 | if (ret) |
| 48 | return ret; |
| 49 | |
| 50 | return fsp_init_phase_pci(); |
Bin Meng | fe3fbd3 | 2015-07-30 03:49:18 -0700 | [diff] [blame] | 51 | } |
Simon Glass | b430258 | 2015-08-04 12:34:02 -0600 | [diff] [blame] | 52 | #endif |