blob: 2b3949cd7b368802dae7328ef2c91e5630cc80ae [file] [log] [blame]
wdenk7abf0c52004-04-18 21:45:42 +00001/*
2 * (C) Copyright 2003, Embedded Edge, LLC
3 * Dan Malek, <dan@embeddededge.com>
4 * Copied from ADS85xx.
5 * Updates for Silicon Tx GP3 8560
6 *
7 * (C) Copyright 2003,Motorola Inc.
8 * Xianghua Xiao, (X.Xiao@motorola.com)
9 *
10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31
32extern long int spd_sdram (void);
33
34#include <common.h>
wdenk9aea9532004-08-01 23:02:45 +000035#include <pci.h>
wdenk7abf0c52004-04-18 21:45:42 +000036#include <asm/processor.h>
37#include <asm/immap_85xx.h>
38#include <ioports.h>
39#include <asm/io.h>
40#include <spd.h>
41#include <miiphy.h>
42
43long int fixed_sdram (void);
44
45/*
46 * I/O Port configuration table
47 *
48 * if conf is 1, then that port pin will be configured at boot time
49 * according to the five values podr/pdir/ppar/psor/pdat for that entry
50 */
51
52const iop_conf_t iop_conf_tab[4][32] = {
53
54 /* Port A configuration */
55 { /* conf ppar psor pdir podr pdat */
56 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
57 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
58 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
59 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
60 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
61 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
62 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
63 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
64 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
65 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
66 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
67 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
68 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
69 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
70 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
71 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
72 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
73 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
74 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
75 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
76 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
77 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
78 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
79 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
80 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
81 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
82 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
83 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
84 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
85 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
86 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
87 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
88 },
89
90 /* Port B configuration */
91 { /* conf ppar psor pdir podr pdat */
92 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
93 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
94 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
95 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
96 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
97 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
98 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
99 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
100 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
101 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
102 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
103 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
104 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
105 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
106 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
107 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
108 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
109 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
110 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
111 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
112 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
113 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
114 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
115 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
116 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
117 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
118 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
119 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
120 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
121 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
122 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
123 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
124 },
125
126 /* Port C */
127 { /* conf ppar psor pdir podr pdat */
128 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
129 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
130 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
131 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
132 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
133 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
134 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
135 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
136 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
137 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
138 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
139 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
140 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
141 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
142 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
143 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
144 /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
145 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
146 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
147 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
148 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
149 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
150 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
151 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
152 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
153 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
154 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
155 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
156 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
157 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
158 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
159 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
160 },
161
162 /* Port D */
163 { /* conf ppar psor pdir podr pdat */
164 /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
165 /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
166 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
167 /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
168 /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
169 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
170 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
171 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
172 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
173 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
174 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
175 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
176 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
177 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
178 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
179 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
180 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
181 /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
182 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
183 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
184 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
185 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
186 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
187 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
188 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
189 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
190 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
191 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
192 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
193 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
194 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
195 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
196 }
197};
198
wdenk7abf0c52004-04-18 21:45:42 +0000199static uint64_t next_led_update;
200static uint led_bit;
201
wdenk9aea9532004-08-01 23:02:45 +0000202int
203board_early_init_f(void)
wdenk7abf0c52004-04-18 21:45:42 +0000204{
205#if defined(CONFIG_PCI)
206 volatile immap_t *immr = (immap_t *)CFG_IMMR;
207 volatile ccsr_pcix_t *pci = &immr->im_pcix;
208
209 pci->peer &= 0xfffffffdf; /* disable master abort */
210#endif
211 return 0;
212}
213
wdenk9aea9532004-08-01 23:02:45 +0000214void
215reset_phy(void)
wdenk7abf0c52004-04-18 21:45:42 +0000216{
217 volatile uint *blatch;
218
219 blatch = (volatile uint *)CFG_LBC_LCLDEVS_BASE;
220
221 /* reset Giga bit Ethernet port if needed here */
222
223 *blatch &= ~0x000000c0;
224 udelay(100);
225 *blatch = 0x000000c1; /* Light one led, too */
226 udelay(1000);
227
228#if 0 /* This is the port we really want to use for debugging. */
229 /* reset the CPM FEC port */
230#if (CONFIG_ETHER_INDEX == 2)
231 bcsr->bcsr2 &= ~FETH2_RST;
232 udelay(2);
233 bcsr->bcsr2 |= FETH2_RST;
234 udelay(1000);
235#elif (CONFIG_ETHER_INDEX == 3)
236 bcsr->bcsr3 &= ~FETH3_RST;
237 udelay(2);
238 bcsr->bcsr3 |= FETH3_RST;
239 udelay(1000);
240#endif
241#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200242 /* reset PHY */
243 miiphy_reset("FCC1 ETHERNET", 0x0);
244
245 /* change PHY address to 0x02 */
246 bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
247
248 bb_miiphy_write(NULL, 0x02, PHY_BMCR,
249 PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
wdenk7abf0c52004-04-18 21:45:42 +0000250#endif /* CONFIG_MII */
251#endif
252}
253
wdenk9aea9532004-08-01 23:02:45 +0000254int
255checkboard(void)
wdenk7abf0c52004-04-18 21:45:42 +0000256{
wdenk7abf0c52004-04-18 21:45:42 +0000257 printf ("Board: Silicon Tx GPPP 8560 Board\n");
wdenk7abf0c52004-04-18 21:45:42 +0000258 return (0);
259}
260
261/* Blinkin' LEDS for Robert.
262*/
263void
264show_activity(int flag)
265{
266 volatile uint *blatch;
267
268 if (next_led_update > get_ticks())
269 return;
270
271 blatch = (volatile uint *)CFG_LBC_LCLDEVS_BASE;
272
273 led_bit >>= 1;
274 if (led_bit == 0)
275 led_bit = 0x08;
276 *blatch = (0xc0 | led_bit);
277 eieio();
278 next_led_update += (get_tbclk() / 4);
279}
280
wdenk9aea9532004-08-01 23:02:45 +0000281long int
282initdram (int board_type)
wdenk7abf0c52004-04-18 21:45:42 +0000283{
284 long dram_size = 0;
285 extern long spd_sdram (void);
286 volatile immap_t *immap = (immap_t *)CFG_IMMR;
287
288#if defined(CONFIG_DDR_DLL)
wdenk9aea9532004-08-01 23:02:45 +0000289 {
290 volatile ccsr_gur_t *gur= &immap->im_gur;
291 uint temp_ddrdll = 0;
wdenk7abf0c52004-04-18 21:45:42 +0000292
wdenk9aea9532004-08-01 23:02:45 +0000293 /* Work around to stabilize DDR DLL */
294 temp_ddrdll = gur->ddrdllcr;
295 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
296 asm("sync;isync;msync");
297 }
wdenk7abf0c52004-04-18 21:45:42 +0000298#endif
299
300 dram_size = spd_sdram ();
301
302#if defined(CONFIG_DDR_ECC)
wdenk9aea9532004-08-01 23:02:45 +0000303 /* Initialize and enable DDR ECC.
304 */
305 ddr_enable_ecc(dram_size);
wdenk7abf0c52004-04-18 21:45:42 +0000306#endif
307
308 return dram_size;
309}
310
311
312#if defined(CFG_DRAM_TEST)
313int testdram (void)
314{
315 uint *pstart = (uint *) CFG_MEMTEST_START;
316 uint *pend = (uint *) CFG_MEMTEST_END;
317 uint *p;
318
319 printf("SDRAM test phase 1:\n");
320 for (p = pstart; p < pend; p++)
321 *p = 0xaaaaaaaa;
322
323 for (p = pstart; p < pend; p++) {
324 if (*p != 0xaaaaaaaa) {
325 printf ("SDRAM test fails at: %08x\n", (uint) p);
326 return 1;
327 }
328 }
329
330 printf("SDRAM test phase 2:\n");
331 for (p = pstart; p < pend; p++)
332 *p = 0x55555555;
333
334 for (p = pstart; p < pend; p++) {
335 if (*p != 0x55555555) {
336 printf ("SDRAM test fails at: %08x\n", (uint) p);
337 return 1;
338 }
339 }
340
341 printf("SDRAM test passed.\n");
342 return 0;
343}
344#endif
345
wdenk9aea9532004-08-01 23:02:45 +0000346#if defined(CONFIG_PCI)
wdenk7abf0c52004-04-18 21:45:42 +0000347
wdenk9aea9532004-08-01 23:02:45 +0000348/*
349 * Initialize PCI Devices, report devices found.
350 */
351
352#ifndef CONFIG_PCI_PNP
353static struct pci_config_table pci_stxgp3_config_table[] = {
354 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
355 PCI_IDSEL_NUMBER, PCI_ANY_ID,
356 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
357 PCI_ENET0_MEMADDR,
358 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
359 } },
360 { }
361};
362#endif
363
364
365static struct pci_controller hose = {
366#ifndef CONFIG_PCI_PNP
367 config_table: pci_stxgp3_config_table,
368#endif
369};
370
371#endif /* CONFIG_PCI */
372
373
374void
375pci_init_board(void)
376{
377#ifdef CONFIG_PCI
378 extern void pci_mpc85xx_init(struct pci_controller *hose);
379
380 pci_mpc85xx_init(&hose);
381#endif /* CONFIG_PCI */
wdenk7abf0c52004-04-18 21:45:42 +0000382}