blob: de3ece81bc4cd9fe2653c637d656d38d905a1e37 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002/*
3 * Copyright (c) 2016, NVIDIA CORPORATION.
4 *
Stephen Warrenba4dfef2016-10-21 14:46:47 -06005 * Portions based on U-Boot's rtl8169.c.
6 */
7
8/*
9 * This driver supports the Synopsys Designware Ethernet QOS (Quality Of
10 * Service) IP block. The IP supports multiple options for bus type, clocking/
11 * reset structure, and feature list.
12 *
13 * The driver is written such that generic core logic is kept separate from
14 * configuration-specific logic. Code that interacts with configuration-
15 * specific resources is split out into separate functions to avoid polluting
16 * common code. If/when this driver is enhanced to support multiple
17 * configurations, the core code should be adapted to call all configuration-
18 * specific functions through function pointers, with the definition of those
19 * function pointers being supplied by struct udevice_id eqos_ids[]'s .data
20 * field.
21 *
22 * The following configurations are currently supported:
23 * tegra186:
24 * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an
25 * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and
26 * supports a single RGMII PHY. This configuration also has SW control over
27 * all clock and reset signals to the HW block.
28 */
Patrick Delaunaycafaa302020-09-09 18:30:06 +020029
Stephen Warrenba4dfef2016-10-21 14:46:47 -060030#include <common.h>
31#include <clk.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070032#include <cpu_func.h>
Stephen Warrenba4dfef2016-10-21 14:46:47 -060033#include <dm.h>
34#include <errno.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060035#include <log.h>
Simon Glass336d4612020-02-03 07:36:16 -070036#include <malloc.h>
Stephen Warrenba4dfef2016-10-21 14:46:47 -060037#include <memalign.h>
38#include <miiphy.h>
39#include <net.h>
40#include <netdev.h>
41#include <phy.h>
42#include <reset.h>
43#include <wait_bit.h>
Simon Glass90526e92020-05-10 11:39:56 -060044#include <asm/cache.h>
Stephen Warrenba4dfef2016-10-21 14:46:47 -060045#include <asm/gpio.h>
46#include <asm/io.h>
Ye Li6a895d02020-05-03 22:41:15 +080047#include <eth_phy.h>
Fugang Duan0e9d2392020-05-03 22:41:18 +080048#ifdef CONFIG_ARCH_IMX8M
49#include <asm/arch/clock.h>
50#include <asm/mach-imx/sys_proto.h>
51#endif
Simon Glasscd93d622020-05-10 11:40:13 -060052#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060053#include <linux/delay.h>
Stephen Warrenba4dfef2016-10-21 14:46:47 -060054
55/* Core registers */
56
57#define EQOS_MAC_REGS_BASE 0x000
58struct eqos_mac_regs {
59 uint32_t configuration; /* 0x000 */
60 uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
61 uint32_t q0_tx_flow_ctrl; /* 0x070 */
62 uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
63 uint32_t rx_flow_ctrl; /* 0x090 */
64 uint32_t unused_094; /* 0x094 */
65 uint32_t txq_prty_map0; /* 0x098 */
66 uint32_t unused_09c; /* 0x09c */
67 uint32_t rxq_ctrl0; /* 0x0a0 */
68 uint32_t unused_0a4; /* 0x0a4 */
69 uint32_t rxq_ctrl2; /* 0x0a8 */
70 uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
71 uint32_t us_tic_counter; /* 0x0dc */
72 uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
73 uint32_t hw_feature0; /* 0x11c */
74 uint32_t hw_feature1; /* 0x120 */
75 uint32_t hw_feature2; /* 0x124 */
76 uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
77 uint32_t mdio_address; /* 0x200 */
78 uint32_t mdio_data; /* 0x204 */
79 uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
80 uint32_t address0_high; /* 0x300 */
81 uint32_t address0_low; /* 0x304 */
82};
83
84#define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
85#define EQOS_MAC_CONFIGURATION_CST BIT(21)
86#define EQOS_MAC_CONFIGURATION_ACS BIT(20)
87#define EQOS_MAC_CONFIGURATION_WD BIT(19)
88#define EQOS_MAC_CONFIGURATION_JD BIT(17)
89#define EQOS_MAC_CONFIGURATION_JE BIT(16)
90#define EQOS_MAC_CONFIGURATION_PS BIT(15)
91#define EQOS_MAC_CONFIGURATION_FES BIT(14)
92#define EQOS_MAC_CONFIGURATION_DM BIT(13)
Fugang Duan3a97da12020-05-03 22:41:17 +080093#define EQOS_MAC_CONFIGURATION_LM BIT(12)
Stephen Warrenba4dfef2016-10-21 14:46:47 -060094#define EQOS_MAC_CONFIGURATION_TE BIT(1)
95#define EQOS_MAC_CONFIGURATION_RE BIT(0)
96
97#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
98#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
99#define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
100
101#define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
102
103#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
104#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
105
106#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
107#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
108#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
109#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200110#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600111
112#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
113#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
114
Fugang Duan3a97da12020-05-03 22:41:17 +0800115#define EQOS_MAC_HW_FEATURE0_MMCSEL_SHIFT 8
116#define EQOS_MAC_HW_FEATURE0_HDSEL_SHIFT 2
117#define EQOS_MAC_HW_FEATURE0_GMIISEL_SHIFT 1
118#define EQOS_MAC_HW_FEATURE0_MIISEL_SHIFT 0
119
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600120#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
121#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
122#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
123#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
124
Fugang Duan3a97da12020-05-03 22:41:17 +0800125#define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28
126#define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3
127
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600128#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
129#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
130#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
131#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200132#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600133#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
134#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
135#define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
136#define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
137#define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
138#define EQOS_MAC_MDIO_ADDRESS_GB BIT(0)
139
140#define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
141
142#define EQOS_MTL_REGS_BASE 0xd00
143struct eqos_mtl_regs {
144 uint32_t txq0_operation_mode; /* 0xd00 */
145 uint32_t unused_d04; /* 0xd04 */
146 uint32_t txq0_debug; /* 0xd08 */
147 uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
148 uint32_t txq0_quantum_weight; /* 0xd18 */
149 uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
150 uint32_t rxq0_operation_mode; /* 0xd30 */
151 uint32_t unused_d34; /* 0xd34 */
152 uint32_t rxq0_debug; /* 0xd38 */
153};
154
155#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
156#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
157#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
158#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
159#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
160#define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
161#define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
162
163#define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
164#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
165#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
166
167#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
168#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
169#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
170#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
171#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
172#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
173#define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
174#define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
Fugang Duan3a97da12020-05-03 22:41:17 +0800175#define EQOS_MTL_RXQ0_OPERATION_MODE_FEP BIT(4)
176#define EQOS_MTL_RXQ0_OPERATION_MODE_FUP BIT(3)
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600177
178#define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
179#define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
180#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
181#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
182
183#define EQOS_DMA_REGS_BASE 0x1000
184struct eqos_dma_regs {
185 uint32_t mode; /* 0x1000 */
186 uint32_t sysbus_mode; /* 0x1004 */
187 uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
188 uint32_t ch0_control; /* 0x1100 */
189 uint32_t ch0_tx_control; /* 0x1104 */
190 uint32_t ch0_rx_control; /* 0x1108 */
191 uint32_t unused_110c; /* 0x110c */
192 uint32_t ch0_txdesc_list_haddress; /* 0x1110 */
193 uint32_t ch0_txdesc_list_address; /* 0x1114 */
194 uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */
195 uint32_t ch0_rxdesc_list_address; /* 0x111c */
196 uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */
197 uint32_t unused_1124; /* 0x1124 */
198 uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */
199 uint32_t ch0_txdesc_ring_length; /* 0x112c */
200 uint32_t ch0_rxdesc_ring_length; /* 0x1130 */
201};
202
203#define EQOS_DMA_MODE_SWR BIT(0)
204
205#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
206#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
207#define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
208#define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
209#define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
210#define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
211
212#define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
213
214#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
215#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
216#define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
217#define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
218
219#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
220#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
221#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
222#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
223#define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
224
225/* These registers are Tegra186-specific */
226#define EQOS_TEGRA186_REGS_BASE 0x8800
227struct eqos_tegra186_regs {
228 uint32_t sdmemcomppadctrl; /* 0x8800 */
229 uint32_t auto_cal_config; /* 0x8804 */
230 uint32_t unused_8808; /* 0x8808 */
231 uint32_t auto_cal_status; /* 0x880c */
232};
233
234#define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
235
236#define EQOS_AUTO_CAL_CONFIG_START BIT(31)
237#define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29)
238
239#define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
240
241/* Descriptors */
242
243#define EQOS_DESCRIPTOR_WORDS 4
244#define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4)
245/* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */
246#define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN
247#define EQOS_DESCRIPTORS_TX 4
248#define EQOS_DESCRIPTORS_RX 4
249#define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
250#define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \
251 EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
252#define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
253#define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
254#define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
255
256/*
257 * Warn if the cache-line size is larger than the descriptor size. In such
258 * cases the driver will likely fail because the CPU needs to flush the cache
259 * when requeuing RX buffers, therefore descriptors written by the hardware
260 * may be discarded. Architectures with full IO coherence, such as x86, do not
261 * experience this issue, and hence are excluded from this condition.
262 *
263 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
264 * the driver to allocate descriptors from a pool of non-cached memory.
265 */
266#if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
267#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
Trevor Woerner10015022019-05-03 09:41:00 -0400268 !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600269#warning Cache line size is larger than descriptor size
270#endif
271#endif
272
273struct eqos_desc {
274 u32 des0;
275 u32 des1;
276 u32 des2;
277 u32 des3;
278};
279
280#define EQOS_DESC3_OWN BIT(31)
281#define EQOS_DESC3_FD BIT(29)
282#define EQOS_DESC3_LD BIT(28)
283#define EQOS_DESC3_BUF1V BIT(24)
284
285struct eqos_config {
286 bool reg_access_always_ok;
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200287 int mdio_wait;
288 int swr_wait;
289 int config_mac;
290 int config_mac_mdio;
291 phy_interface_t (*interface)(struct udevice *dev);
292 struct eqos_ops *ops;
293};
294
295struct eqos_ops {
296 void (*eqos_inval_desc)(void *desc);
297 void (*eqos_flush_desc)(void *desc);
298 void (*eqos_inval_buffer)(void *buf, size_t size);
299 void (*eqos_flush_buffer)(void *buf, size_t size);
300 int (*eqos_probe_resources)(struct udevice *dev);
301 int (*eqos_remove_resources)(struct udevice *dev);
302 int (*eqos_stop_resets)(struct udevice *dev);
303 int (*eqos_start_resets)(struct udevice *dev);
304 void (*eqos_stop_clks)(struct udevice *dev);
305 int (*eqos_start_clks)(struct udevice *dev);
306 int (*eqos_calibrate_pads)(struct udevice *dev);
307 int (*eqos_disable_calibration)(struct udevice *dev);
308 int (*eqos_set_tx_clk_speed)(struct udevice *dev);
309 ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600310};
311
312struct eqos_priv {
313 struct udevice *dev;
314 const struct eqos_config *config;
315 fdt_addr_t regs;
316 struct eqos_mac_regs *mac_regs;
317 struct eqos_mtl_regs *mtl_regs;
318 struct eqos_dma_regs *dma_regs;
319 struct eqos_tegra186_regs *tegra186_regs;
320 struct reset_ctl reset_ctl;
321 struct gpio_desc phy_reset_gpio;
322 struct clk clk_master_bus;
323 struct clk clk_rx;
324 struct clk clk_ptp_ref;
325 struct clk clk_tx;
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200326 struct clk clk_ck;
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600327 struct clk clk_slave_bus;
328 struct mii_dev *mii;
329 struct phy_device *phy;
Patrick Delaunay4f60a512020-03-18 10:50:16 +0100330 int phyaddr;
331 u32 max_speed;
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600332 void *descs;
333 struct eqos_desc *tx_descs;
334 struct eqos_desc *rx_descs;
335 int tx_desc_idx, rx_desc_idx;
336 void *tx_dma_buf;
337 void *rx_dma_buf;
338 void *rx_pkt;
339 bool started;
340 bool reg_access_ok;
341};
342
343/*
344 * TX and RX descriptors are 16 bytes. This causes problems with the cache
345 * maintenance on CPUs where the cache-line size exceeds the size of these
346 * descriptors. What will happen is that when the driver receives a packet
347 * it will be immediately requeued for the hardware to reuse. The CPU will
348 * therefore need to flush the cache-line containing the descriptor, which
349 * will cause all other descriptors in the same cache-line to be flushed
350 * along with it. If one of those descriptors had been written to by the
351 * device those changes (and the associated packet) will be lost.
352 *
353 * To work around this, we make use of non-cached memory if available. If
354 * descriptors are mapped uncached there's no need to manually flush them
355 * or invalidate them.
356 *
357 * Note that this only applies to descriptors. The packet data buffers do
358 * not have the same constraints since they are 1536 bytes large, so they
359 * are unlikely to share cache-lines.
360 */
361static void *eqos_alloc_descs(unsigned int num)
362{
363#ifdef CONFIG_SYS_NONCACHED_MEMORY
364 return (void *)noncached_alloc(EQOS_DESCRIPTORS_SIZE,
365 EQOS_DESCRIPTOR_ALIGN);
366#else
367 return memalign(EQOS_DESCRIPTOR_ALIGN, EQOS_DESCRIPTORS_SIZE);
368#endif
369}
370
371static void eqos_free_descs(void *descs)
372{
373#ifdef CONFIG_SYS_NONCACHED_MEMORY
374 /* FIXME: noncached_alloc() has no opposite */
375#else
376 free(descs);
377#endif
378}
379
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200380static void eqos_inval_desc_tegra186(void *desc)
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600381{
382#ifndef CONFIG_SYS_NONCACHED_MEMORY
383 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
384 unsigned long end = ALIGN(start + EQOS_DESCRIPTOR_SIZE,
385 ARCH_DMA_MINALIGN);
386
387 invalidate_dcache_range(start, end);
388#endif
389}
390
Fugang Duan3a97da12020-05-03 22:41:17 +0800391static void eqos_inval_desc_generic(void *desc)
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200392{
393#ifndef CONFIG_SYS_NONCACHED_MEMORY
394 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
395 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
396 ARCH_DMA_MINALIGN);
397
398 invalidate_dcache_range(start, end);
399#endif
400}
401
402static void eqos_flush_desc_tegra186(void *desc)
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600403{
404#ifndef CONFIG_SYS_NONCACHED_MEMORY
405 flush_cache((unsigned long)desc, EQOS_DESCRIPTOR_SIZE);
406#endif
407}
408
Fugang Duan3a97da12020-05-03 22:41:17 +0800409static void eqos_flush_desc_generic(void *desc)
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200410{
411#ifndef CONFIG_SYS_NONCACHED_MEMORY
412 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
413 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
414 ARCH_DMA_MINALIGN);
415
416 flush_dcache_range(start, end);
417#endif
418}
419
420static void eqos_inval_buffer_tegra186(void *buf, size_t size)
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600421{
422 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
423 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
424
425 invalidate_dcache_range(start, end);
426}
427
Fugang Duan3a97da12020-05-03 22:41:17 +0800428static void eqos_inval_buffer_generic(void *buf, size_t size)
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200429{
430 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
431 unsigned long end = roundup((unsigned long)buf + size,
432 ARCH_DMA_MINALIGN);
433
434 invalidate_dcache_range(start, end);
435}
436
437static void eqos_flush_buffer_tegra186(void *buf, size_t size)
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600438{
439 flush_cache((unsigned long)buf, size);
440}
441
Fugang Duan3a97da12020-05-03 22:41:17 +0800442static void eqos_flush_buffer_generic(void *buf, size_t size)
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200443{
444 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
445 unsigned long end = roundup((unsigned long)buf + size,
446 ARCH_DMA_MINALIGN);
447
448 flush_dcache_range(start, end);
449}
450
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600451static int eqos_mdio_wait_idle(struct eqos_priv *eqos)
452{
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100453 return wait_for_bit_le32(&eqos->mac_regs->mdio_address,
454 EQOS_MAC_MDIO_ADDRESS_GB, false,
455 1000000, true);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600456}
457
458static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
459 int mdio_reg)
460{
461 struct eqos_priv *eqos = bus->priv;
462 u32 val;
463 int ret;
464
465 debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr,
466 mdio_reg);
467
468 ret = eqos_mdio_wait_idle(eqos);
469 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900470 pr_err("MDIO not idle at entry");
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600471 return ret;
472 }
473
474 val = readl(&eqos->mac_regs->mdio_address);
475 val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
476 EQOS_MAC_MDIO_ADDRESS_C45E;
477 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
478 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200479 (eqos->config->config_mac_mdio <<
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600480 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
481 (EQOS_MAC_MDIO_ADDRESS_GOC_READ <<
482 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
483 EQOS_MAC_MDIO_ADDRESS_GB;
484 writel(val, &eqos->mac_regs->mdio_address);
485
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200486 udelay(eqos->config->mdio_wait);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600487
488 ret = eqos_mdio_wait_idle(eqos);
489 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900490 pr_err("MDIO read didn't complete");
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600491 return ret;
492 }
493
494 val = readl(&eqos->mac_regs->mdio_data);
495 val &= EQOS_MAC_MDIO_DATA_GD_MASK;
496
497 debug("%s: val=%x\n", __func__, val);
498
499 return val;
500}
501
502static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad,
503 int mdio_reg, u16 mdio_val)
504{
505 struct eqos_priv *eqos = bus->priv;
506 u32 val;
507 int ret;
508
509 debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev,
510 mdio_addr, mdio_reg, mdio_val);
511
512 ret = eqos_mdio_wait_idle(eqos);
513 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900514 pr_err("MDIO not idle at entry");
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600515 return ret;
516 }
517
518 writel(mdio_val, &eqos->mac_regs->mdio_data);
519
520 val = readl(&eqos->mac_regs->mdio_address);
521 val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
522 EQOS_MAC_MDIO_ADDRESS_C45E;
523 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
524 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200525 (eqos->config->config_mac_mdio <<
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600526 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
527 (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE <<
528 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
529 EQOS_MAC_MDIO_ADDRESS_GB;
530 writel(val, &eqos->mac_regs->mdio_address);
531
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200532 udelay(eqos->config->mdio_wait);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600533
534 ret = eqos_mdio_wait_idle(eqos);
535 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900536 pr_err("MDIO read didn't complete");
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600537 return ret;
538 }
539
540 return 0;
541}
542
543static int eqos_start_clks_tegra186(struct udevice *dev)
544{
Fugang Duan3a97da12020-05-03 22:41:17 +0800545#ifdef CONFIG_CLK
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600546 struct eqos_priv *eqos = dev_get_priv(dev);
547 int ret;
548
549 debug("%s(dev=%p):\n", __func__, dev);
550
551 ret = clk_enable(&eqos->clk_slave_bus);
552 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900553 pr_err("clk_enable(clk_slave_bus) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600554 goto err;
555 }
556
557 ret = clk_enable(&eqos->clk_master_bus);
558 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900559 pr_err("clk_enable(clk_master_bus) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600560 goto err_disable_clk_slave_bus;
561 }
562
563 ret = clk_enable(&eqos->clk_rx);
564 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900565 pr_err("clk_enable(clk_rx) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600566 goto err_disable_clk_master_bus;
567 }
568
569 ret = clk_enable(&eqos->clk_ptp_ref);
570 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900571 pr_err("clk_enable(clk_ptp_ref) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600572 goto err_disable_clk_rx;
573 }
574
575 ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000);
576 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900577 pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600578 goto err_disable_clk_ptp_ref;
579 }
580
581 ret = clk_enable(&eqos->clk_tx);
582 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900583 pr_err("clk_enable(clk_tx) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600584 goto err_disable_clk_ptp_ref;
585 }
Fugang Duan3a97da12020-05-03 22:41:17 +0800586#endif
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600587
588 debug("%s: OK\n", __func__);
589 return 0;
590
Fugang Duan3a97da12020-05-03 22:41:17 +0800591#ifdef CONFIG_CLK
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600592err_disable_clk_ptp_ref:
593 clk_disable(&eqos->clk_ptp_ref);
594err_disable_clk_rx:
595 clk_disable(&eqos->clk_rx);
596err_disable_clk_master_bus:
597 clk_disable(&eqos->clk_master_bus);
598err_disable_clk_slave_bus:
599 clk_disable(&eqos->clk_slave_bus);
600err:
601 debug("%s: FAILED: %d\n", __func__, ret);
602 return ret;
Fugang Duan3a97da12020-05-03 22:41:17 +0800603#endif
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600604}
605
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200606static int eqos_start_clks_stm32(struct udevice *dev)
607{
Fugang Duan3a97da12020-05-03 22:41:17 +0800608#ifdef CONFIG_CLK
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200609 struct eqos_priv *eqos = dev_get_priv(dev);
610 int ret;
611
612 debug("%s(dev=%p):\n", __func__, dev);
613
614 ret = clk_enable(&eqos->clk_master_bus);
615 if (ret < 0) {
616 pr_err("clk_enable(clk_master_bus) failed: %d", ret);
617 goto err;
618 }
619
620 ret = clk_enable(&eqos->clk_rx);
621 if (ret < 0) {
622 pr_err("clk_enable(clk_rx) failed: %d", ret);
623 goto err_disable_clk_master_bus;
624 }
625
626 ret = clk_enable(&eqos->clk_tx);
627 if (ret < 0) {
628 pr_err("clk_enable(clk_tx) failed: %d", ret);
629 goto err_disable_clk_rx;
630 }
631
632 if (clk_valid(&eqos->clk_ck)) {
633 ret = clk_enable(&eqos->clk_ck);
634 if (ret < 0) {
635 pr_err("clk_enable(clk_ck) failed: %d", ret);
636 goto err_disable_clk_tx;
637 }
638 }
Fugang Duan3a97da12020-05-03 22:41:17 +0800639#endif
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200640
641 debug("%s: OK\n", __func__);
642 return 0;
643
Fugang Duan3a97da12020-05-03 22:41:17 +0800644#ifdef CONFIG_CLK
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200645err_disable_clk_tx:
646 clk_disable(&eqos->clk_tx);
647err_disable_clk_rx:
648 clk_disable(&eqos->clk_rx);
649err_disable_clk_master_bus:
650 clk_disable(&eqos->clk_master_bus);
651err:
652 debug("%s: FAILED: %d\n", __func__, ret);
653 return ret;
Fugang Duan3a97da12020-05-03 22:41:17 +0800654#endif
655}
656
657static int eqos_start_clks_imx(struct udevice *dev)
658{
659 return 0;
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200660}
661
Patrick Delaunay50d86e52019-08-01 11:29:02 +0200662static void eqos_stop_clks_tegra186(struct udevice *dev)
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600663{
Fugang Duan3a97da12020-05-03 22:41:17 +0800664#ifdef CONFIG_CLK
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600665 struct eqos_priv *eqos = dev_get_priv(dev);
666
667 debug("%s(dev=%p):\n", __func__, dev);
668
669 clk_disable(&eqos->clk_tx);
670 clk_disable(&eqos->clk_ptp_ref);
671 clk_disable(&eqos->clk_rx);
672 clk_disable(&eqos->clk_master_bus);
673 clk_disable(&eqos->clk_slave_bus);
Fugang Duan3a97da12020-05-03 22:41:17 +0800674#endif
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600675
676 debug("%s: OK\n", __func__);
677}
678
Patrick Delaunay50d86e52019-08-01 11:29:02 +0200679static void eqos_stop_clks_stm32(struct udevice *dev)
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200680{
Fugang Duan3a97da12020-05-03 22:41:17 +0800681#ifdef CONFIG_CLK
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200682 struct eqos_priv *eqos = dev_get_priv(dev);
683
684 debug("%s(dev=%p):\n", __func__, dev);
685
686 clk_disable(&eqos->clk_tx);
687 clk_disable(&eqos->clk_rx);
688 clk_disable(&eqos->clk_master_bus);
689 if (clk_valid(&eqos->clk_ck))
690 clk_disable(&eqos->clk_ck);
Fugang Duan3a97da12020-05-03 22:41:17 +0800691#endif
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200692
693 debug("%s: OK\n", __func__);
694}
695
Fugang Duan3a97da12020-05-03 22:41:17 +0800696static void eqos_stop_clks_imx(struct udevice *dev)
697{
698 /* empty */
699}
700
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600701static int eqos_start_resets_tegra186(struct udevice *dev)
702{
703 struct eqos_priv *eqos = dev_get_priv(dev);
704 int ret;
705
706 debug("%s(dev=%p):\n", __func__, dev);
707
708 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
709 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900710 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600711 return ret;
712 }
713
714 udelay(2);
715
716 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
717 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900718 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600719 return ret;
720 }
721
722 ret = reset_assert(&eqos->reset_ctl);
723 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900724 pr_err("reset_assert() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600725 return ret;
726 }
727
728 udelay(2);
729
730 ret = reset_deassert(&eqos->reset_ctl);
731 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900732 pr_err("reset_deassert() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600733 return ret;
734 }
735
736 debug("%s: OK\n", __func__);
737 return 0;
738}
739
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200740static int eqos_start_resets_stm32(struct udevice *dev)
741{
Christophe Roullier5177b312020-03-18 10:50:15 +0100742 struct eqos_priv *eqos = dev_get_priv(dev);
743 int ret;
744
745 debug("%s(dev=%p):\n", __func__, dev);
746 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
747 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
748 if (ret < 0) {
749 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d",
750 ret);
751 return ret;
752 }
753
754 udelay(2);
755
756 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
757 if (ret < 0) {
758 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d",
759 ret);
760 return ret;
761 }
762 }
763 debug("%s: OK\n", __func__);
764
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200765 return 0;
766}
767
Fugang Duan3a97da12020-05-03 22:41:17 +0800768static int eqos_start_resets_imx(struct udevice *dev)
769{
770 return 0;
771}
772
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600773static int eqos_stop_resets_tegra186(struct udevice *dev)
774{
775 struct eqos_priv *eqos = dev_get_priv(dev);
776
777 reset_assert(&eqos->reset_ctl);
778 dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
779
780 return 0;
781}
782
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200783static int eqos_stop_resets_stm32(struct udevice *dev)
784{
Christophe Roullier5177b312020-03-18 10:50:15 +0100785 struct eqos_priv *eqos = dev_get_priv(dev);
786 int ret;
787
788 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
789 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
790 if (ret < 0) {
791 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d",
792 ret);
793 return ret;
794 }
795 }
796
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200797 return 0;
798}
799
Fugang Duan3a97da12020-05-03 22:41:17 +0800800static int eqos_stop_resets_imx(struct udevice *dev)
801{
802 return 0;
803}
804
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600805static int eqos_calibrate_pads_tegra186(struct udevice *dev)
806{
807 struct eqos_priv *eqos = dev_get_priv(dev);
808 int ret;
809
810 debug("%s(dev=%p):\n", __func__, dev);
811
812 setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
813 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
814
815 udelay(1);
816
817 setbits_le32(&eqos->tegra186_regs->auto_cal_config,
818 EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE);
819
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100820 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
821 EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600822 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900823 pr_err("calibrate didn't start");
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600824 goto failed;
825 }
826
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100827 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
828 EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600829 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900830 pr_err("calibrate didn't finish");
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600831 goto failed;
832 }
833
834 ret = 0;
835
836failed:
837 clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
838 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
839
840 debug("%s: returns %d\n", __func__, ret);
841
842 return ret;
843}
844
845static int eqos_disable_calibration_tegra186(struct udevice *dev)
846{
847 struct eqos_priv *eqos = dev_get_priv(dev);
848
849 debug("%s(dev=%p):\n", __func__, dev);
850
851 clrbits_le32(&eqos->tegra186_regs->auto_cal_config,
852 EQOS_AUTO_CAL_CONFIG_ENABLE);
853
854 return 0;
855}
856
857static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev)
858{
Fugang Duan3a97da12020-05-03 22:41:17 +0800859#ifdef CONFIG_CLK
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600860 struct eqos_priv *eqos = dev_get_priv(dev);
861
862 return clk_get_rate(&eqos->clk_slave_bus);
Fugang Duan3a97da12020-05-03 22:41:17 +0800863#else
864 return 0;
865#endif
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600866}
867
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200868static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
869{
Fugang Duan3a97da12020-05-03 22:41:17 +0800870#ifdef CONFIG_CLK
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200871 struct eqos_priv *eqos = dev_get_priv(dev);
872
873 return clk_get_rate(&eqos->clk_master_bus);
Fugang Duan3a97da12020-05-03 22:41:17 +0800874#else
875 return 0;
876#endif
877}
878
Fugang Duan0e9d2392020-05-03 22:41:18 +0800879__weak u32 imx_get_eqos_csr_clk(void)
880{
881 return 100 * 1000000;
882}
883__weak int imx_eqos_txclk_set_rate(unsigned long rate)
884{
885 return 0;
886}
887
Fugang Duan3a97da12020-05-03 22:41:17 +0800888static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
889{
Fugang Duan0e9d2392020-05-03 22:41:18 +0800890 return imx_get_eqos_csr_clk();
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200891}
892
893static int eqos_calibrate_pads_stm32(struct udevice *dev)
894{
895 return 0;
896}
897
Fugang Duan3a97da12020-05-03 22:41:17 +0800898static int eqos_calibrate_pads_imx(struct udevice *dev)
899{
900 return 0;
901}
902
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200903static int eqos_disable_calibration_stm32(struct udevice *dev)
904{
905 return 0;
906}
907
Fugang Duan3a97da12020-05-03 22:41:17 +0800908static int eqos_disable_calibration_imx(struct udevice *dev)
909{
910 return 0;
911}
912
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600913static int eqos_set_full_duplex(struct udevice *dev)
914{
915 struct eqos_priv *eqos = dev_get_priv(dev);
916
917 debug("%s(dev=%p):\n", __func__, dev);
918
919 setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
920
921 return 0;
922}
923
924static int eqos_set_half_duplex(struct udevice *dev)
925{
926 struct eqos_priv *eqos = dev_get_priv(dev);
927
928 debug("%s(dev=%p):\n", __func__, dev);
929
930 clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
931
932 /* WAR: Flush TX queue when switching to half-duplex */
933 setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
934 EQOS_MTL_TXQ0_OPERATION_MODE_FTQ);
935
936 return 0;
937}
938
939static int eqos_set_gmii_speed(struct udevice *dev)
940{
941 struct eqos_priv *eqos = dev_get_priv(dev);
942
943 debug("%s(dev=%p):\n", __func__, dev);
944
945 clrbits_le32(&eqos->mac_regs->configuration,
946 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
947
948 return 0;
949}
950
951static int eqos_set_mii_speed_100(struct udevice *dev)
952{
953 struct eqos_priv *eqos = dev_get_priv(dev);
954
955 debug("%s(dev=%p):\n", __func__, dev);
956
957 setbits_le32(&eqos->mac_regs->configuration,
958 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
959
960 return 0;
961}
962
963static int eqos_set_mii_speed_10(struct udevice *dev)
964{
965 struct eqos_priv *eqos = dev_get_priv(dev);
966
967 debug("%s(dev=%p):\n", __func__, dev);
968
969 clrsetbits_le32(&eqos->mac_regs->configuration,
970 EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS);
971
972 return 0;
973}
974
975static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev)
976{
Fugang Duan3a97da12020-05-03 22:41:17 +0800977#ifdef CONFIG_CLK
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600978 struct eqos_priv *eqos = dev_get_priv(dev);
979 ulong rate;
980 int ret;
981
982 debug("%s(dev=%p):\n", __func__, dev);
983
984 switch (eqos->phy->speed) {
985 case SPEED_1000:
986 rate = 125 * 1000 * 1000;
987 break;
988 case SPEED_100:
989 rate = 25 * 1000 * 1000;
990 break;
991 case SPEED_10:
992 rate = 2.5 * 1000 * 1000;
993 break;
994 default:
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900995 pr_err("invalid speed %d", eqos->phy->speed);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600996 return -EINVAL;
997 }
998
999 ret = clk_set_rate(&eqos->clk_tx, rate);
1000 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001001 pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001002 return ret;
1003 }
Fugang Duan3a97da12020-05-03 22:41:17 +08001004#endif
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001005
1006 return 0;
1007}
1008
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001009static int eqos_set_tx_clk_speed_stm32(struct udevice *dev)
1010{
1011 return 0;
1012}
1013
Fugang Duan3a97da12020-05-03 22:41:17 +08001014static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
1015{
Fugang Duan0e9d2392020-05-03 22:41:18 +08001016 struct eqos_priv *eqos = dev_get_priv(dev);
1017 ulong rate;
1018 int ret;
1019
1020 debug("%s(dev=%p):\n", __func__, dev);
1021
1022 switch (eqos->phy->speed) {
1023 case SPEED_1000:
1024 rate = 125 * 1000 * 1000;
1025 break;
1026 case SPEED_100:
1027 rate = 25 * 1000 * 1000;
1028 break;
1029 case SPEED_10:
1030 rate = 2.5 * 1000 * 1000;
1031 break;
1032 default:
1033 pr_err("invalid speed %d", eqos->phy->speed);
1034 return -EINVAL;
1035 }
1036
1037 ret = imx_eqos_txclk_set_rate(rate);
1038 if (ret < 0) {
1039 pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
1040 return ret;
1041 }
1042
Fugang Duan3a97da12020-05-03 22:41:17 +08001043 return 0;
1044}
1045
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001046static int eqos_adjust_link(struct udevice *dev)
1047{
1048 struct eqos_priv *eqos = dev_get_priv(dev);
1049 int ret;
1050 bool en_calibration;
1051
1052 debug("%s(dev=%p):\n", __func__, dev);
1053
1054 if (eqos->phy->duplex)
1055 ret = eqos_set_full_duplex(dev);
1056 else
1057 ret = eqos_set_half_duplex(dev);
1058 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001059 pr_err("eqos_set_*_duplex() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001060 return ret;
1061 }
1062
1063 switch (eqos->phy->speed) {
1064 case SPEED_1000:
1065 en_calibration = true;
1066 ret = eqos_set_gmii_speed(dev);
1067 break;
1068 case SPEED_100:
1069 en_calibration = true;
1070 ret = eqos_set_mii_speed_100(dev);
1071 break;
1072 case SPEED_10:
1073 en_calibration = false;
1074 ret = eqos_set_mii_speed_10(dev);
1075 break;
1076 default:
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001077 pr_err("invalid speed %d", eqos->phy->speed);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001078 return -EINVAL;
1079 }
1080 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001081 pr_err("eqos_set_*mii_speed*() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001082 return ret;
1083 }
1084
1085 if (en_calibration) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001086 ret = eqos->config->ops->eqos_calibrate_pads(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001087 if (ret < 0) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001088 pr_err("eqos_calibrate_pads() failed: %d",
1089 ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001090 return ret;
1091 }
1092 } else {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001093 ret = eqos->config->ops->eqos_disable_calibration(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001094 if (ret < 0) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001095 pr_err("eqos_disable_calibration() failed: %d",
1096 ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001097 return ret;
1098 }
1099 }
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001100 ret = eqos->config->ops->eqos_set_tx_clk_speed(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001101 if (ret < 0) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001102 pr_err("eqos_set_tx_clk_speed() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001103 return ret;
1104 }
1105
1106 return 0;
1107}
1108
1109static int eqos_write_hwaddr(struct udevice *dev)
1110{
1111 struct eth_pdata *plat = dev_get_platdata(dev);
1112 struct eqos_priv *eqos = dev_get_priv(dev);
1113 uint32_t val;
1114
1115 /*
1116 * This function may be called before start() or after stop(). At that
1117 * time, on at least some configurations of the EQoS HW, all clocks to
1118 * the EQoS HW block will be stopped, and a reset signal applied. If
1119 * any register access is attempted in this state, bus timeouts or CPU
1120 * hangs may occur. This check prevents that.
1121 *
1122 * A simple solution to this problem would be to not implement
1123 * write_hwaddr(), since start() always writes the MAC address into HW
1124 * anyway. However, it is desirable to implement write_hwaddr() to
1125 * support the case of SW that runs subsequent to U-Boot which expects
1126 * the MAC address to already be programmed into the EQoS registers,
1127 * which must happen irrespective of whether the U-Boot user (or
1128 * scripts) actually made use of the EQoS device, and hence
1129 * irrespective of whether start() was ever called.
1130 *
1131 * Note that this requirement by subsequent SW is not valid for
1132 * Tegra186, and is likely not valid for any non-PCI instantiation of
1133 * the EQoS HW block. This function is implemented solely as
1134 * future-proofing with the expectation the driver will eventually be
1135 * ported to some system where the expectation above is true.
1136 */
1137 if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok)
1138 return 0;
1139
1140 /* Update the MAC address */
1141 val = (plat->enetaddr[5] << 8) |
1142 (plat->enetaddr[4]);
1143 writel(val, &eqos->mac_regs->address0_high);
1144 val = (plat->enetaddr[3] << 24) |
1145 (plat->enetaddr[2] << 16) |
1146 (plat->enetaddr[1] << 8) |
1147 (plat->enetaddr[0]);
1148 writel(val, &eqos->mac_regs->address0_low);
1149
1150 return 0;
1151}
1152
Ye Li580fab42020-05-03 22:41:20 +08001153static int eqos_read_rom_hwaddr(struct udevice *dev)
1154{
1155 struct eth_pdata *pdata = dev_get_platdata(dev);
1156
1157#ifdef CONFIG_ARCH_IMX8M
1158 imx_get_mac_from_fuse(dev->req_seq, pdata->enetaddr);
1159#endif
1160 return !is_valid_ethaddr(pdata->enetaddr);
1161}
1162
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001163static int eqos_start(struct udevice *dev)
1164{
1165 struct eqos_priv *eqos = dev_get_priv(dev);
1166 int ret, i;
1167 ulong rate;
1168 u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
1169 ulong last_rx_desc;
1170
1171 debug("%s(dev=%p):\n", __func__, dev);
1172
1173 eqos->tx_desc_idx = 0;
1174 eqos->rx_desc_idx = 0;
1175
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001176 ret = eqos->config->ops->eqos_start_clks(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001177 if (ret < 0) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001178 pr_err("eqos_start_clks() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001179 goto err;
1180 }
1181
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001182 ret = eqos->config->ops->eqos_start_resets(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001183 if (ret < 0) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001184 pr_err("eqos_start_resets() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001185 goto err_stop_clks;
1186 }
1187
1188 udelay(10);
1189
1190 eqos->reg_access_ok = true;
1191
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +01001192 ret = wait_for_bit_le32(&eqos->dma_regs->mode,
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001193 EQOS_DMA_MODE_SWR, false,
1194 eqos->config->swr_wait, false);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001195 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001196 pr_err("EQOS_DMA_MODE_SWR stuck");
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001197 goto err_stop_resets;
1198 }
1199
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001200 ret = eqos->config->ops->eqos_calibrate_pads(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001201 if (ret < 0) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001202 pr_err("eqos_calibrate_pads() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001203 goto err_stop_resets;
1204 }
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001205 rate = eqos->config->ops->eqos_get_tick_clk_rate(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001206
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001207 val = (rate / 1000000) - 1;
1208 writel(val, &eqos->mac_regs->us_tic_counter);
1209
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001210 /*
1211 * if PHY was already connected and configured,
1212 * don't need to reconnect/reconfigure again
1213 */
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001214 if (!eqos->phy) {
Ye Li6a895d02020-05-03 22:41:15 +08001215 int addr = -1;
1216#ifdef CONFIG_DM_ETH_PHY
1217 addr = eth_phy_get_addr(dev);
1218#endif
1219#ifdef DWC_NET_PHYADDR
1220 addr = DWC_NET_PHYADDR;
1221#endif
1222 eqos->phy = phy_connect(eqos->mii, addr, dev,
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001223 eqos->config->interface(dev));
1224 if (!eqos->phy) {
1225 pr_err("phy_connect() failed");
1226 goto err_stop_resets;
1227 }
Patrick Delaunay4f60a512020-03-18 10:50:16 +01001228
1229 if (eqos->max_speed) {
1230 ret = phy_set_supported(eqos->phy, eqos->max_speed);
1231 if (ret) {
1232 pr_err("phy_set_supported() failed: %d", ret);
1233 goto err_shutdown_phy;
1234 }
1235 }
1236
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001237 ret = phy_config(eqos->phy);
1238 if (ret < 0) {
1239 pr_err("phy_config() failed: %d", ret);
1240 goto err_shutdown_phy;
1241 }
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001242 }
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001243
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001244 ret = phy_startup(eqos->phy);
1245 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001246 pr_err("phy_startup() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001247 goto err_shutdown_phy;
1248 }
1249
1250 if (!eqos->phy->link) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001251 pr_err("No link");
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001252 goto err_shutdown_phy;
1253 }
1254
1255 ret = eqos_adjust_link(dev);
1256 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001257 pr_err("eqos_adjust_link() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001258 goto err_shutdown_phy;
1259 }
1260
1261 /* Configure MTL */
Fugang Duan3a97da12020-05-03 22:41:17 +08001262 writel(0x60, &eqos->mtl_regs->txq0_quantum_weight - 0x100);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001263
1264 /* Enable Store and Forward mode for TX */
1265 /* Program Tx operating mode */
1266 setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
1267 EQOS_MTL_TXQ0_OPERATION_MODE_TSF |
1268 (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED <<
1269 EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT));
1270
1271 /* Transmit Queue weight */
1272 writel(0x10, &eqos->mtl_regs->txq0_quantum_weight);
1273
1274 /* Enable Store and Forward mode for RX, since no jumbo frame */
1275 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
Fugang Duan3a97da12020-05-03 22:41:17 +08001276 EQOS_MTL_RXQ0_OPERATION_MODE_RSF |
1277 EQOS_MTL_RXQ0_OPERATION_MODE_FEP |
1278 EQOS_MTL_RXQ0_OPERATION_MODE_FUP);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001279
1280 /* Transmit/Receive queue fifo size; use all RAM for 1 queue */
1281 val = readl(&eqos->mac_regs->hw_feature1);
1282 tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) &
1283 EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK;
1284 rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) &
1285 EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
1286
1287 /*
1288 * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
1289 * r/tqs is encoded as (n / 256) - 1.
1290 */
1291 tqs = (128 << tx_fifo_sz) / 256 - 1;
1292 rqs = (128 << rx_fifo_sz) / 256 - 1;
1293
1294 clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode,
1295 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<
1296 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT,
1297 tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT);
1298 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1299 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK <<
1300 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT,
1301 rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT);
1302
1303 /* Flow control used only if each channel gets 4KB or more FIFO */
1304 if (rqs >= ((4096 / 256) - 1)) {
1305 u32 rfd, rfa;
1306
1307 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1308 EQOS_MTL_RXQ0_OPERATION_MODE_EHFC);
1309
1310 /*
1311 * Set Threshold for Activating Flow Contol space for min 2
1312 * frames ie, (1500 * 1) = 1500 bytes.
1313 *
1314 * Set Threshold for Deactivating Flow Contol for space of
1315 * min 1 frame (frame size 1500bytes) in receive fifo
1316 */
1317 if (rqs == ((4096 / 256) - 1)) {
1318 /*
1319 * This violates the above formula because of FIFO size
1320 * limit therefore overflow may occur inspite of this.
1321 */
1322 rfd = 0x3; /* Full-3K */
1323 rfa = 0x1; /* Full-1.5K */
1324 } else if (rqs == ((8192 / 256) - 1)) {
1325 rfd = 0x6; /* Full-4K */
1326 rfa = 0xa; /* Full-6K */
1327 } else if (rqs == ((16384 / 256) - 1)) {
1328 rfd = 0x6; /* Full-4K */
1329 rfa = 0x12; /* Full-10K */
1330 } else {
1331 rfd = 0x6; /* Full-4K */
1332 rfa = 0x1E; /* Full-16K */
1333 }
1334
1335 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1336 (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK <<
1337 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
1338 (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK <<
1339 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT),
1340 (rfd <<
1341 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
1342 (rfa <<
1343 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT));
1344 }
1345
1346 /* Configure MAC */
1347
1348 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
1349 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
1350 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001351 eqos->config->config_mac <<
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001352 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
1353
Fugang Duan3a97da12020-05-03 22:41:17 +08001354 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
1355 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
1356 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
1357 0x2 <<
1358 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
1359
1360 /* Multicast and Broadcast Queue Enable */
1361 setbits_le32(&eqos->mac_regs->unused_0a4,
1362 0x00100000);
1363 /* enable promise mode */
1364 setbits_le32(&eqos->mac_regs->unused_004[1],
1365 0x1);
1366
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001367 /* Set TX flow control parameters */
1368 /* Set Pause Time */
1369 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
1370 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT);
1371 /* Assign priority for TX flow control */
1372 clrbits_le32(&eqos->mac_regs->txq_prty_map0,
1373 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK <<
1374 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT);
1375 /* Assign priority for RX flow control */
1376 clrbits_le32(&eqos->mac_regs->rxq_ctrl2,
1377 EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK <<
1378 EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT);
1379 /* Enable flow control */
1380 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
1381 EQOS_MAC_Q0_TX_FLOW_CTRL_TFE);
1382 setbits_le32(&eqos->mac_regs->rx_flow_ctrl,
1383 EQOS_MAC_RX_FLOW_CTRL_RFE);
1384
1385 clrsetbits_le32(&eqos->mac_regs->configuration,
1386 EQOS_MAC_CONFIGURATION_GPSLCE |
1387 EQOS_MAC_CONFIGURATION_WD |
1388 EQOS_MAC_CONFIGURATION_JD |
1389 EQOS_MAC_CONFIGURATION_JE,
1390 EQOS_MAC_CONFIGURATION_CST |
1391 EQOS_MAC_CONFIGURATION_ACS);
1392
1393 eqos_write_hwaddr(dev);
1394
1395 /* Configure DMA */
1396
1397 /* Enable OSP mode */
1398 setbits_le32(&eqos->dma_regs->ch0_tx_control,
1399 EQOS_DMA_CH0_TX_CONTROL_OSP);
1400
1401 /* RX buffer size. Must be a multiple of bus width */
1402 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
1403 EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK <<
1404 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT,
1405 EQOS_MAX_PACKET_SIZE <<
1406 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT);
1407
1408 setbits_le32(&eqos->dma_regs->ch0_control,
1409 EQOS_DMA_CH0_CONTROL_PBLX8);
1410
1411 /*
1412 * Burst length must be < 1/2 FIFO size.
1413 * FIFO size in tqs is encoded as (n / 256) - 1.
1414 * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes.
1415 * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1.
1416 */
1417 pbl = tqs + 1;
1418 if (pbl > 32)
1419 pbl = 32;
1420 clrsetbits_le32(&eqos->dma_regs->ch0_tx_control,
1421 EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK <<
1422 EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT,
1423 pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
1424
1425 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
1426 EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK <<
1427 EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT,
1428 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT);
1429
1430 /* DMA performance configuration */
1431 val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) |
1432 EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 |
1433 EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4;
1434 writel(val, &eqos->dma_regs->sysbus_mode);
1435
1436 /* Set up descriptors */
1437
1438 memset(eqos->descs, 0, EQOS_DESCRIPTORS_SIZE);
1439 for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
1440 struct eqos_desc *rx_desc = &(eqos->rx_descs[i]);
1441 rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
1442 (i * EQOS_MAX_PACKET_SIZE));
Marek Vasut4332d802020-03-23 02:02:57 +01001443 rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
Fugang Duan3a97da12020-05-03 22:41:17 +08001444 mb();
Marek Vasutdd90c2e2020-03-23 02:09:01 +01001445 eqos->config->ops->eqos_flush_desc(rx_desc);
Fugang Duan3a97da12020-05-03 22:41:17 +08001446 eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf +
1447 (i * EQOS_MAX_PACKET_SIZE),
1448 EQOS_MAX_PACKET_SIZE);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001449 }
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001450
1451 writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
1452 writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address);
1453 writel(EQOS_DESCRIPTORS_TX - 1,
1454 &eqos->dma_regs->ch0_txdesc_ring_length);
1455
1456 writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);
1457 writel((ulong)eqos->rx_descs, &eqos->dma_regs->ch0_rxdesc_list_address);
1458 writel(EQOS_DESCRIPTORS_RX - 1,
1459 &eqos->dma_regs->ch0_rxdesc_ring_length);
1460
1461 /* Enable everything */
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001462 setbits_le32(&eqos->dma_regs->ch0_tx_control,
1463 EQOS_DMA_CH0_TX_CONTROL_ST);
1464 setbits_le32(&eqos->dma_regs->ch0_rx_control,
1465 EQOS_DMA_CH0_RX_CONTROL_SR);
Fugang Duan3a97da12020-05-03 22:41:17 +08001466 setbits_le32(&eqos->mac_regs->configuration,
1467 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001468
1469 /* TX tail pointer not written until we need to TX a packet */
1470 /*
1471 * Point RX tail pointer at last descriptor. Ideally, we'd point at the
1472 * first descriptor, implying all descriptors were available. However,
1473 * that's not distinguishable from none of the descriptors being
1474 * available.
1475 */
1476 last_rx_desc = (ulong)&(eqos->rx_descs[(EQOS_DESCRIPTORS_RX - 1)]);
1477 writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
1478
1479 eqos->started = true;
1480
1481 debug("%s: OK\n", __func__);
1482 return 0;
1483
1484err_shutdown_phy:
1485 phy_shutdown(eqos->phy);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001486err_stop_resets:
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001487 eqos->config->ops->eqos_stop_resets(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001488err_stop_clks:
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001489 eqos->config->ops->eqos_stop_clks(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001490err:
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001491 pr_err("FAILED: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001492 return ret;
1493}
1494
Patrick Delaunay50d86e52019-08-01 11:29:02 +02001495static void eqos_stop(struct udevice *dev)
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001496{
1497 struct eqos_priv *eqos = dev_get_priv(dev);
1498 int i;
1499
1500 debug("%s(dev=%p):\n", __func__, dev);
1501
1502 if (!eqos->started)
1503 return;
1504 eqos->started = false;
1505 eqos->reg_access_ok = false;
1506
1507 /* Disable TX DMA */
1508 clrbits_le32(&eqos->dma_regs->ch0_tx_control,
1509 EQOS_DMA_CH0_TX_CONTROL_ST);
1510
1511 /* Wait for TX all packets to drain out of MTL */
1512 for (i = 0; i < 1000000; i++) {
1513 u32 val = readl(&eqos->mtl_regs->txq0_debug);
1514 u32 trcsts = (val >> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) &
1515 EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK;
1516 u32 txqsts = val & EQOS_MTL_TXQ0_DEBUG_TXQSTS;
1517 if ((trcsts != 1) && (!txqsts))
1518 break;
1519 }
1520
1521 /* Turn off MAC TX and RX */
1522 clrbits_le32(&eqos->mac_regs->configuration,
1523 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
1524
1525 /* Wait for all RX packets to drain out of MTL */
1526 for (i = 0; i < 1000000; i++) {
1527 u32 val = readl(&eqos->mtl_regs->rxq0_debug);
1528 u32 prxq = (val >> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT) &
1529 EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK;
1530 u32 rxqsts = (val >> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) &
1531 EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK;
1532 if ((!prxq) && (!rxqsts))
1533 break;
1534 }
1535
1536 /* Turn off RX DMA */
1537 clrbits_le32(&eqos->dma_regs->ch0_rx_control,
1538 EQOS_DMA_CH0_RX_CONTROL_SR);
1539
1540 if (eqos->phy) {
1541 phy_shutdown(eqos->phy);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001542 }
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001543 eqos->config->ops->eqos_stop_resets(dev);
1544 eqos->config->ops->eqos_stop_clks(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001545
1546 debug("%s: OK\n", __func__);
1547}
1548
Patrick Delaunay50d86e52019-08-01 11:29:02 +02001549static int eqos_send(struct udevice *dev, void *packet, int length)
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001550{
1551 struct eqos_priv *eqos = dev_get_priv(dev);
1552 struct eqos_desc *tx_desc;
1553 int i;
1554
1555 debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet,
1556 length);
1557
1558 memcpy(eqos->tx_dma_buf, packet, length);
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001559 eqos->config->ops->eqos_flush_buffer(eqos->tx_dma_buf, length);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001560
1561 tx_desc = &(eqos->tx_descs[eqos->tx_desc_idx]);
1562 eqos->tx_desc_idx++;
1563 eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
1564
1565 tx_desc->des0 = (ulong)eqos->tx_dma_buf;
1566 tx_desc->des1 = 0;
1567 tx_desc->des2 = length;
1568 /*
1569 * Make sure that if HW sees the _OWN write below, it will see all the
1570 * writes to the rest of the descriptor too.
1571 */
1572 mb();
1573 tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length;
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001574 eqos->config->ops->eqos_flush_desc(tx_desc);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001575
Marek Vasut83858d82020-03-23 02:03:50 +01001576 writel((ulong)(&(eqos->tx_descs[eqos->tx_desc_idx])),
1577 &eqos->dma_regs->ch0_txdesc_tail_pointer);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001578
1579 for (i = 0; i < 1000000; i++) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001580 eqos->config->ops->eqos_inval_desc(tx_desc);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001581 if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN))
1582 return 0;
1583 udelay(1);
1584 }
1585
1586 debug("%s: TX timeout\n", __func__);
1587
1588 return -ETIMEDOUT;
1589}
1590
Patrick Delaunay50d86e52019-08-01 11:29:02 +02001591static int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001592{
1593 struct eqos_priv *eqos = dev_get_priv(dev);
1594 struct eqos_desc *rx_desc;
1595 int length;
1596
1597 debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
1598
1599 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
Marek Vasut738ee272020-03-23 02:09:21 +01001600 eqos->config->ops->eqos_inval_desc(rx_desc);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001601 if (rx_desc->des3 & EQOS_DESC3_OWN) {
1602 debug("%s: RX packet not available\n", __func__);
1603 return -EAGAIN;
1604 }
1605
1606 *packetp = eqos->rx_dma_buf +
1607 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
1608 length = rx_desc->des3 & 0x7fff;
1609 debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length);
1610
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001611 eqos->config->ops->eqos_inval_buffer(*packetp, length);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001612
1613 return length;
1614}
1615
Patrick Delaunay50d86e52019-08-01 11:29:02 +02001616static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001617{
1618 struct eqos_priv *eqos = dev_get_priv(dev);
1619 uchar *packet_expected;
1620 struct eqos_desc *rx_desc;
1621
1622 debug("%s(packet=%p, length=%d)\n", __func__, packet, length);
1623
1624 packet_expected = eqos->rx_dma_buf +
1625 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
1626 if (packet != packet_expected) {
1627 debug("%s: Unexpected packet (expected %p)\n", __func__,
1628 packet_expected);
1629 return -EINVAL;
1630 }
1631
Fugang Duan3a97da12020-05-03 22:41:17 +08001632 eqos->config->ops->eqos_inval_buffer(packet, length);
1633
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001634 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
Marek Vasuta83ca0c2020-03-23 02:09:55 +01001635
Marek Vasut24891dd2020-03-23 02:11:46 +01001636 rx_desc->des0 = 0;
1637 mb();
1638 eqos->config->ops->eqos_flush_desc(rx_desc);
Marek Vasuta83ca0c2020-03-23 02:09:55 +01001639 eqos->config->ops->eqos_inval_buffer(packet, length);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001640 rx_desc->des0 = (u32)(ulong)packet;
1641 rx_desc->des1 = 0;
1642 rx_desc->des2 = 0;
1643 /*
1644 * Make sure that if HW sees the _OWN write below, it will see all the
1645 * writes to the rest of the descriptor too.
1646 */
1647 mb();
Marek Vasut4332d802020-03-23 02:02:57 +01001648 rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001649 eqos->config->ops->eqos_flush_desc(rx_desc);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001650
1651 writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
1652
1653 eqos->rx_desc_idx++;
1654 eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX;
1655
1656 return 0;
1657}
1658
1659static int eqos_probe_resources_core(struct udevice *dev)
1660{
1661 struct eqos_priv *eqos = dev_get_priv(dev);
1662 int ret;
1663
1664 debug("%s(dev=%p):\n", __func__, dev);
1665
1666 eqos->descs = eqos_alloc_descs(EQOS_DESCRIPTORS_TX +
1667 EQOS_DESCRIPTORS_RX);
1668 if (!eqos->descs) {
1669 debug("%s: eqos_alloc_descs() failed\n", __func__);
1670 ret = -ENOMEM;
1671 goto err;
1672 }
1673 eqos->tx_descs = (struct eqos_desc *)eqos->descs;
1674 eqos->rx_descs = (eqos->tx_descs + EQOS_DESCRIPTORS_TX);
1675 debug("%s: tx_descs=%p, rx_descs=%p\n", __func__, eqos->tx_descs,
1676 eqos->rx_descs);
1677
1678 eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE);
1679 if (!eqos->tx_dma_buf) {
1680 debug("%s: memalign(tx_dma_buf) failed\n", __func__);
1681 ret = -ENOMEM;
1682 goto err_free_descs;
1683 }
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001684 debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001685
1686 eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE);
1687 if (!eqos->rx_dma_buf) {
1688 debug("%s: memalign(rx_dma_buf) failed\n", __func__);
1689 ret = -ENOMEM;
1690 goto err_free_tx_dma_buf;
1691 }
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001692 debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001693
1694 eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE);
1695 if (!eqos->rx_pkt) {
1696 debug("%s: malloc(rx_pkt) failed\n", __func__);
1697 ret = -ENOMEM;
1698 goto err_free_rx_dma_buf;
1699 }
1700 debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
1701
Marek Vasuta83ca0c2020-03-23 02:09:55 +01001702 eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf,
1703 EQOS_MAX_PACKET_SIZE * EQOS_DESCRIPTORS_RX);
1704
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001705 debug("%s: OK\n", __func__);
1706 return 0;
1707
1708err_free_rx_dma_buf:
1709 free(eqos->rx_dma_buf);
1710err_free_tx_dma_buf:
1711 free(eqos->tx_dma_buf);
1712err_free_descs:
1713 eqos_free_descs(eqos->descs);
1714err:
1715
1716 debug("%s: returns %d\n", __func__, ret);
1717 return ret;
1718}
1719
1720static int eqos_remove_resources_core(struct udevice *dev)
1721{
1722 struct eqos_priv *eqos = dev_get_priv(dev);
1723
1724 debug("%s(dev=%p):\n", __func__, dev);
1725
1726 free(eqos->rx_pkt);
1727 free(eqos->rx_dma_buf);
1728 free(eqos->tx_dma_buf);
1729 eqos_free_descs(eqos->descs);
1730
1731 debug("%s: OK\n", __func__);
1732 return 0;
1733}
1734
1735static int eqos_probe_resources_tegra186(struct udevice *dev)
1736{
1737 struct eqos_priv *eqos = dev_get_priv(dev);
1738 int ret;
1739
1740 debug("%s(dev=%p):\n", __func__, dev);
1741
1742 ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl);
1743 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001744 pr_err("reset_get_by_name(rst) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001745 return ret;
1746 }
1747
1748 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
1749 &eqos->phy_reset_gpio,
1750 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
1751 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001752 pr_err("gpio_request_by_name(phy reset) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001753 goto err_free_reset_eqos;
1754 }
1755
1756 ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus);
1757 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001758 pr_err("clk_get_by_name(slave_bus) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001759 goto err_free_gpio_phy_reset;
1760 }
1761
1762 ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus);
1763 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001764 pr_err("clk_get_by_name(master_bus) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001765 goto err_free_clk_slave_bus;
1766 }
1767
1768 ret = clk_get_by_name(dev, "rx", &eqos->clk_rx);
1769 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001770 pr_err("clk_get_by_name(rx) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001771 goto err_free_clk_master_bus;
1772 }
1773
1774 ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
1775 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001776 pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001777 goto err_free_clk_rx;
1778 return ret;
1779 }
1780
1781 ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
1782 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001783 pr_err("clk_get_by_name(tx) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001784 goto err_free_clk_ptp_ref;
1785 }
1786
1787 debug("%s: OK\n", __func__);
1788 return 0;
1789
1790err_free_clk_ptp_ref:
1791 clk_free(&eqos->clk_ptp_ref);
1792err_free_clk_rx:
1793 clk_free(&eqos->clk_rx);
1794err_free_clk_master_bus:
1795 clk_free(&eqos->clk_master_bus);
1796err_free_clk_slave_bus:
1797 clk_free(&eqos->clk_slave_bus);
1798err_free_gpio_phy_reset:
1799 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1800err_free_reset_eqos:
1801 reset_free(&eqos->reset_ctl);
1802
1803 debug("%s: returns %d\n", __func__, ret);
1804 return ret;
1805}
1806
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001807/* board-specific Ethernet Interface initializations. */
Patrick Delaunay53e3d522019-08-01 11:29:03 +02001808__weak int board_interface_eth_init(struct udevice *dev,
1809 phy_interface_t interface_type)
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001810{
1811 return 0;
1812}
1813
1814static int eqos_probe_resources_stm32(struct udevice *dev)
1815{
1816 struct eqos_priv *eqos = dev_get_priv(dev);
1817 int ret;
1818 phy_interface_t interface;
Christophe Roullier5177b312020-03-18 10:50:15 +01001819 struct ofnode_phandle_args phandle_args;
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001820
1821 debug("%s(dev=%p):\n", __func__, dev);
1822
1823 interface = eqos->config->interface(dev);
1824
1825 if (interface == PHY_INTERFACE_MODE_NONE) {
1826 pr_err("Invalid PHY interface\n");
1827 return -EINVAL;
1828 }
1829
Patrick Delaunay53e3d522019-08-01 11:29:03 +02001830 ret = board_interface_eth_init(dev, interface);
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001831 if (ret)
1832 return -EINVAL;
1833
Patrick Delaunay4f60a512020-03-18 10:50:16 +01001834 eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
1835
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001836 ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
1837 if (ret) {
1838 pr_err("clk_get_by_name(master_bus) failed: %d", ret);
1839 goto err_probe;
1840 }
1841
1842 ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
1843 if (ret) {
1844 pr_err("clk_get_by_name(rx) failed: %d", ret);
1845 goto err_free_clk_master_bus;
1846 }
1847
1848 ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
1849 if (ret) {
1850 pr_err("clk_get_by_name(tx) failed: %d", ret);
1851 goto err_free_clk_rx;
1852 }
1853
1854 /* Get ETH_CLK clocks (optional) */
1855 ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
1856 if (ret)
1857 pr_warn("No phy clock provided %d", ret);
1858
Patrick Delaunay4f60a512020-03-18 10:50:16 +01001859 eqos->phyaddr = -1;
Christophe Roullier5177b312020-03-18 10:50:15 +01001860 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1861 &phandle_args);
1862 if (!ret) {
1863 /* search "reset-gpios" in phy node */
1864 ret = gpio_request_by_name_nodev(phandle_args.node,
1865 "reset-gpios", 0,
1866 &eqos->phy_reset_gpio,
1867 GPIOD_IS_OUT |
1868 GPIOD_IS_OUT_ACTIVE);
1869 if (ret)
1870 pr_warn("gpio_request_by_name(phy reset) not provided %d",
1871 ret);
Patrick Delaunay4f60a512020-03-18 10:50:16 +01001872
1873 eqos->phyaddr = ofnode_read_u32_default(phandle_args.node,
1874 "reg", -1);
Christophe Roullier5177b312020-03-18 10:50:15 +01001875 }
1876
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001877 debug("%s: OK\n", __func__);
1878 return 0;
1879
1880err_free_clk_rx:
1881 clk_free(&eqos->clk_rx);
1882err_free_clk_master_bus:
1883 clk_free(&eqos->clk_master_bus);
1884err_probe:
1885
1886 debug("%s: returns %d\n", __func__, ret);
1887 return ret;
1888}
1889
1890static phy_interface_t eqos_get_interface_stm32(struct udevice *dev)
1891{
1892 const char *phy_mode;
1893 phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
1894
1895 debug("%s(dev=%p):\n", __func__, dev);
1896
Patrick Delaunaycafaa302020-09-09 18:30:06 +02001897 phy_mode = dev_read_prop(dev, "phy-mode", NULL);
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001898 if (phy_mode)
1899 interface = phy_get_interface_by_name(phy_mode);
1900
1901 return interface;
1902}
1903
1904static phy_interface_t eqos_get_interface_tegra186(struct udevice *dev)
1905{
1906 return PHY_INTERFACE_MODE_MII;
1907}
1908
Fugang Duan3a97da12020-05-03 22:41:17 +08001909static int eqos_probe_resources_imx(struct udevice *dev)
1910{
1911 struct eqos_priv *eqos = dev_get_priv(dev);
1912 phy_interface_t interface;
1913
1914 debug("%s(dev=%p):\n", __func__, dev);
1915
1916 interface = eqos->config->interface(dev);
1917
1918 if (interface == PHY_INTERFACE_MODE_NONE) {
1919 pr_err("Invalid PHY interface\n");
1920 return -EINVAL;
1921 }
1922
1923 debug("%s: OK\n", __func__);
1924 return 0;
1925}
1926
1927static phy_interface_t eqos_get_interface_imx(struct udevice *dev)
1928{
Fugang Duan0e9d2392020-05-03 22:41:18 +08001929 const char *phy_mode;
1930 phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
1931
1932 debug("%s(dev=%p):\n", __func__, dev);
1933
Patrick Delaunaycafaa302020-09-09 18:30:06 +02001934 phy_mode = dev_read_prop(dev, "phy-mode", NULL);
Fugang Duan0e9d2392020-05-03 22:41:18 +08001935 if (phy_mode)
1936 interface = phy_get_interface_by_name(phy_mode);
1937
1938 return interface;
Fugang Duan3a97da12020-05-03 22:41:17 +08001939}
1940
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001941static int eqos_remove_resources_tegra186(struct udevice *dev)
1942{
1943 struct eqos_priv *eqos = dev_get_priv(dev);
1944
1945 debug("%s(dev=%p):\n", __func__, dev);
1946
Fugang Duan3a97da12020-05-03 22:41:17 +08001947#ifdef CONFIG_CLK
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001948 clk_free(&eqos->clk_tx);
1949 clk_free(&eqos->clk_ptp_ref);
1950 clk_free(&eqos->clk_rx);
1951 clk_free(&eqos->clk_slave_bus);
1952 clk_free(&eqos->clk_master_bus);
Fugang Duan3a97da12020-05-03 22:41:17 +08001953#endif
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001954 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1955 reset_free(&eqos->reset_ctl);
1956
1957 debug("%s: OK\n", __func__);
1958 return 0;
1959}
1960
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001961static int eqos_remove_resources_stm32(struct udevice *dev)
1962{
Fugang Duan3a97da12020-05-03 22:41:17 +08001963#ifdef CONFIG_CLK
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001964 struct eqos_priv *eqos = dev_get_priv(dev);
1965
1966 debug("%s(dev=%p):\n", __func__, dev);
1967
1968 clk_free(&eqos->clk_tx);
1969 clk_free(&eqos->clk_rx);
1970 clk_free(&eqos->clk_master_bus);
1971 if (clk_valid(&eqos->clk_ck))
1972 clk_free(&eqos->clk_ck);
Fugang Duan3a97da12020-05-03 22:41:17 +08001973#endif
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001974
Christophe Roullier5177b312020-03-18 10:50:15 +01001975 if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
1976 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1977
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001978 debug("%s: OK\n", __func__);
1979 return 0;
1980}
1981
Fugang Duan3a97da12020-05-03 22:41:17 +08001982static int eqos_remove_resources_imx(struct udevice *dev)
1983{
1984 return 0;
1985}
1986
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001987static int eqos_probe(struct udevice *dev)
1988{
1989 struct eqos_priv *eqos = dev_get_priv(dev);
1990 int ret;
1991
1992 debug("%s(dev=%p):\n", __func__, dev);
1993
1994 eqos->dev = dev;
1995 eqos->config = (void *)dev_get_driver_data(dev);
1996
Masahiro Yamada25484932020-07-17 14:36:48 +09001997 eqos->regs = dev_read_addr(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001998 if (eqos->regs == FDT_ADDR_T_NONE) {
Masahiro Yamada25484932020-07-17 14:36:48 +09001999 pr_err("dev_read_addr() failed");
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002000 return -ENODEV;
2001 }
2002 eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
2003 eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE);
2004 eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE);
2005 eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE);
2006
2007 ret = eqos_probe_resources_core(dev);
2008 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09002009 pr_err("eqos_probe_resources_core() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002010 return ret;
2011 }
2012
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02002013 ret = eqos->config->ops->eqos_probe_resources(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002014 if (ret < 0) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02002015 pr_err("eqos_probe_resources() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002016 goto err_remove_resources_core;
2017 }
2018
Ye Li6a895d02020-05-03 22:41:15 +08002019#ifdef CONFIG_DM_ETH_PHY
2020 eqos->mii = eth_phy_get_mdio_bus(dev);
2021#endif
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002022 if (!eqos->mii) {
Ye Li6a895d02020-05-03 22:41:15 +08002023 eqos->mii = mdio_alloc();
2024 if (!eqos->mii) {
2025 pr_err("mdio_alloc() failed");
2026 ret = -ENOMEM;
2027 goto err_remove_resources_tegra;
2028 }
2029 eqos->mii->read = eqos_mdio_read;
2030 eqos->mii->write = eqos_mdio_write;
2031 eqos->mii->priv = eqos;
2032 strcpy(eqos->mii->name, dev->name);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002033
Ye Li6a895d02020-05-03 22:41:15 +08002034 ret = mdio_register(eqos->mii);
2035 if (ret < 0) {
2036 pr_err("mdio_register() failed: %d", ret);
2037 goto err_free_mdio;
2038 }
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002039 }
2040
Ye Li6a895d02020-05-03 22:41:15 +08002041#ifdef CONFIG_DM_ETH_PHY
2042 eth_phy_set_mdio_bus(dev, eqos->mii);
2043#endif
2044
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002045 debug("%s: OK\n", __func__);
2046 return 0;
2047
2048err_free_mdio:
2049 mdio_free(eqos->mii);
2050err_remove_resources_tegra:
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02002051 eqos->config->ops->eqos_remove_resources(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002052err_remove_resources_core:
2053 eqos_remove_resources_core(dev);
2054
2055 debug("%s: returns %d\n", __func__, ret);
2056 return ret;
2057}
2058
2059static int eqos_remove(struct udevice *dev)
2060{
2061 struct eqos_priv *eqos = dev_get_priv(dev);
2062
2063 debug("%s(dev=%p):\n", __func__, dev);
2064
2065 mdio_unregister(eqos->mii);
2066 mdio_free(eqos->mii);
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02002067 eqos->config->ops->eqos_remove_resources(dev);
2068
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002069 eqos_probe_resources_core(dev);
2070
2071 debug("%s: OK\n", __func__);
2072 return 0;
2073}
2074
2075static const struct eth_ops eqos_ops = {
2076 .start = eqos_start,
2077 .stop = eqos_stop,
2078 .send = eqos_send,
2079 .recv = eqos_recv,
2080 .free_pkt = eqos_free_pkt,
2081 .write_hwaddr = eqos_write_hwaddr,
Ye Li580fab42020-05-03 22:41:20 +08002082 .read_rom_hwaddr = eqos_read_rom_hwaddr,
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002083};
2084
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02002085static struct eqos_ops eqos_tegra186_ops = {
2086 .eqos_inval_desc = eqos_inval_desc_tegra186,
2087 .eqos_flush_desc = eqos_flush_desc_tegra186,
2088 .eqos_inval_buffer = eqos_inval_buffer_tegra186,
2089 .eqos_flush_buffer = eqos_flush_buffer_tegra186,
2090 .eqos_probe_resources = eqos_probe_resources_tegra186,
2091 .eqos_remove_resources = eqos_remove_resources_tegra186,
2092 .eqos_stop_resets = eqos_stop_resets_tegra186,
2093 .eqos_start_resets = eqos_start_resets_tegra186,
2094 .eqos_stop_clks = eqos_stop_clks_tegra186,
2095 .eqos_start_clks = eqos_start_clks_tegra186,
2096 .eqos_calibrate_pads = eqos_calibrate_pads_tegra186,
2097 .eqos_disable_calibration = eqos_disable_calibration_tegra186,
2098 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186,
2099 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186
2100};
2101
Patrick Delaunaya08f2f72020-06-08 11:27:19 +02002102static const struct eqos_config __maybe_unused eqos_tegra186_config = {
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002103 .reg_access_always_ok = false,
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02002104 .mdio_wait = 10,
2105 .swr_wait = 10,
2106 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
2107 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35,
2108 .interface = eqos_get_interface_tegra186,
2109 .ops = &eqos_tegra186_ops
2110};
2111
2112static struct eqos_ops eqos_stm32_ops = {
Fugang Duan3a97da12020-05-03 22:41:17 +08002113 .eqos_inval_desc = eqos_inval_desc_generic,
2114 .eqos_flush_desc = eqos_flush_desc_generic,
2115 .eqos_inval_buffer = eqos_inval_buffer_generic,
2116 .eqos_flush_buffer = eqos_flush_buffer_generic,
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02002117 .eqos_probe_resources = eqos_probe_resources_stm32,
2118 .eqos_remove_resources = eqos_remove_resources_stm32,
2119 .eqos_stop_resets = eqos_stop_resets_stm32,
2120 .eqos_start_resets = eqos_start_resets_stm32,
2121 .eqos_stop_clks = eqos_stop_clks_stm32,
2122 .eqos_start_clks = eqos_start_clks_stm32,
2123 .eqos_calibrate_pads = eqos_calibrate_pads_stm32,
2124 .eqos_disable_calibration = eqos_disable_calibration_stm32,
2125 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32,
2126 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
2127};
2128
Patrick Delaunaya08f2f72020-06-08 11:27:19 +02002129static const struct eqos_config __maybe_unused eqos_stm32_config = {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02002130 .reg_access_always_ok = false,
2131 .mdio_wait = 10000,
2132 .swr_wait = 50,
2133 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
2134 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
2135 .interface = eqos_get_interface_stm32,
2136 .ops = &eqos_stm32_ops
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002137};
2138
Fugang Duan3a97da12020-05-03 22:41:17 +08002139static struct eqos_ops eqos_imx_ops = {
2140 .eqos_inval_desc = eqos_inval_desc_generic,
2141 .eqos_flush_desc = eqos_flush_desc_generic,
2142 .eqos_inval_buffer = eqos_inval_buffer_generic,
2143 .eqos_flush_buffer = eqos_flush_buffer_generic,
2144 .eqos_probe_resources = eqos_probe_resources_imx,
2145 .eqos_remove_resources = eqos_remove_resources_imx,
2146 .eqos_stop_resets = eqos_stop_resets_imx,
2147 .eqos_start_resets = eqos_start_resets_imx,
2148 .eqos_stop_clks = eqos_stop_clks_imx,
2149 .eqos_start_clks = eqos_start_clks_imx,
2150 .eqos_calibrate_pads = eqos_calibrate_pads_imx,
2151 .eqos_disable_calibration = eqos_disable_calibration_imx,
2152 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
2153 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
2154};
2155
Patrick Delaunaya08f2f72020-06-08 11:27:19 +02002156struct eqos_config __maybe_unused eqos_imx_config = {
Fugang Duan3a97da12020-05-03 22:41:17 +08002157 .reg_access_always_ok = false,
2158 .mdio_wait = 10000,
2159 .swr_wait = 50,
2160 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
2161 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
2162 .interface = eqos_get_interface_imx,
2163 .ops = &eqos_imx_ops
2164};
2165
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002166static const struct udevice_id eqos_ids[] = {
Patrick Delaunaya08f2f72020-06-08 11:27:19 +02002167#if IS_ENABLED(CONFIG_DWC_ETH_QOS_TEGRA186)
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002168 {
2169 .compatible = "nvidia,tegra186-eqos",
2170 .data = (ulong)&eqos_tegra186_config
2171 },
Patrick Delaunaya08f2f72020-06-08 11:27:19 +02002172#endif
2173#if IS_ENABLED(CONFIG_DWC_ETH_QOS_STM32)
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02002174 {
Patrick Delaunaya718a5d2020-05-14 15:00:23 +02002175 .compatible = "st,stm32mp1-dwmac",
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02002176 .data = (ulong)&eqos_stm32_config
2177 },
Patrick Delaunaya08f2f72020-06-08 11:27:19 +02002178#endif
2179#if IS_ENABLED(CONFIG_DWC_ETH_QOS_IMX)
Fugang Duan3a97da12020-05-03 22:41:17 +08002180 {
2181 .compatible = "fsl,imx-eqos",
2182 .data = (ulong)&eqos_imx_config
2183 },
Patrick Delaunaya08f2f72020-06-08 11:27:19 +02002184#endif
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02002185
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002186 { }
2187};
2188
2189U_BOOT_DRIVER(eth_eqos) = {
2190 .name = "eth_eqos",
2191 .id = UCLASS_ETH,
Fugang Duan3a97da12020-05-03 22:41:17 +08002192 .of_match = of_match_ptr(eqos_ids),
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002193 .probe = eqos_probe,
2194 .remove = eqos_remove,
2195 .ops = &eqos_ops,
Simon Glass41575d82020-12-03 16:55:17 -07002196 .priv_auto = sizeof(struct eqos_priv),
2197 .platdata_auto = sizeof(struct eth_pdata),
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002198};