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TsiChungLiew8ae158c2007-08-16 15:05:11 -05001/*
2 *
3 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <asm/processor.h>
27
28#include <asm/immap.h>
29
30DECLARE_GLOBAL_DATA_PTR;
31
32/*
33 * Low Power Divider specifications
34 */
35#define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
36#define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
37
38#define CLOCK_PLL_FVCO_MAX 540000000
39#define CLOCK_PLL_FVCO_MIN 300000000
40
41#define CLOCK_PLL_FSYS_MAX 266666666
42#define CLOCK_PLL_FSYS_MIN 100000000
43#define MHZ 1000000
44
45void clock_enter_limp(int lpdiv)
46{
47 volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
48 int i, j;
49
50 /* Check bounds of divider */
51 if (lpdiv < CLOCK_LPD_MIN)
52 lpdiv = CLOCK_LPD_MIN;
53 if (lpdiv > CLOCK_LPD_MAX)
54 lpdiv = CLOCK_LPD_MAX;
55
56 /* Round divider down to nearest power of two */
57 for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
58
59 /* Apply the divider to the system clock */
60 ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i);
61
62 /* Enable Limp Mode */
63 ccm->misccr |= CCM_MISCCR_LIMP;
64}
65
66/*
67 * brief Exit Limp mode
68 * warning The PLL should be set and locked prior to exiting Limp mode
69 */
70void clock_exit_limp(void)
71{
72 volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
73 volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
74
75 /* Exit Limp mode */
76 ccm->misccr &= ~CCM_MISCCR_LIMP;
77
78 /* Wait for the PLL to lock */
79 while (!(pll->psr & PLL_PSR_LOCK)) ;
80}
81
82/*
83 * get_clocks() fills in gd->cpu_clock and gd->bus_clk
84 */
85int get_clocks(void)
86{
87 volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
88 volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
89 volatile u8 *cpld = (volatile u8 *)(CFG_CS2_BASE + 3);
90 volatile u8 *fpga = (volatile u8 *)(CFG_CS3_BASE + 14);
91 int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
92 int pllmult_pci[] = { 12, 6, 16, 8 };
93 int vco, bPci, temp, fbtemp, pcrvalue;
94 int *pPllmult = NULL;
95 u16 fbpll_mask;
96 u8 cpldmode;
97
98 /* To determine PCI is present or not */
99 if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
100 ((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
101 pPllmult = &pllmult_pci[0];
102 fbpll_mask = 3;
103 bPci = 1;
104 } else {
105 pPllmult = &pllmult_nopci[0];
106 fbpll_mask = 7;
107#ifdef CONFIG_PCI
108 gd->pci_clk = 0;
109#endif
110 bPci = 0;
111 }
112
113#ifdef CONFIG_M54455EVB
114 /* Temporary place here, belongs in board/freescale/... */
115 /* Temporary read from CCR- fixed fb issue, must be the same clock
116 as pci or input clock, causing cpld/fpga read inconsistancy */
117 fbtemp = pPllmult[ccm->ccr & fbpll_mask];
118
119 /* Break down into small pieces, code still in flex bus */
120 pcrvalue = pll->pcr & 0xFFFFF0FF;
121 temp = fbtemp - 1;
122 pcrvalue |= PLL_PCR_OUTDIV3(temp);
123
124 pll->pcr = pcrvalue;
125
126 cpldmode = *cpld & 0x03;
127 if (cpldmode == 0) {
128 /* RCON mode */
129 vco = pPllmult[ccm->rcon & fbpll_mask] * CFG_INPUT_CLKSRC;
130
131 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
132 /* invaild range, re-set in PCR */
133 int temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
134 int i, j, bus;
135
136 j = (pll->pcr & 0xFF000000) >> 24;
137 for (i = j; i < 0xFF; i++) {
138 vco = i * CFG_INPUT_CLKSRC;
139 if (vco >= CLOCK_PLL_FVCO_MIN) {
140 bus = vco / temp;
141 if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
142 continue;
143 else
144 break;
145 }
146 }
147 pcrvalue = pll->pcr & 0x00FF00FF;
148 fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
149 pcrvalue |= ((i << 24) | fbtemp);
150
151 pll->pcr = pcrvalue;
152 }
153 gd->vco_clk = vco; /* Vco clock */
154 } else if (cpldmode == 2) {
155 /* Normal mode */
156 vco = pPllmult[ccm->ccr & fbpll_mask] * CFG_INPUT_CLKSRC;
157 gd->vco_clk = vco; /* Vco clock */
158 } else if (cpldmode == 3) {
159 /* serial mode */
160 }
161#endif /* CONFIG_M54455EVB */
162
163 if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
164 /* Limp mode */
165 } else {
166 gd->inp_clk = CFG_INPUT_CLKSRC; /* Input clock */
167
168 temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
169 gd->cpu_clk = vco / temp; /* cpu clock */
170
171 temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
172 gd->bus_clk = vco / temp; /* bus clock */
173
174 temp = ((pll->pcr & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
175 gd->flb_clk = vco / temp; /* FlexBus clock */
176
177#ifdef CONFIG_PCI
178 if (bPci) {
179 temp = ((pll->pcr & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
180 gd->pci_clk = vco / temp; /* PCI clock */
181 }
182#endif
183 }
184
185 return (0);
186}