blob: 529cc65f70c9952f63682dccf2b767a5faeea89b [file] [log] [blame]
Stefan Roesec157d8e2005-08-01 16:41:48 +02001/*
Wolfgang Denk1a459662013-07-08 09:37:19 +02002 * SPDX-License-Identifier: GPL-2.0+
Stefan Roesec157d8e2005-08-01 16:41:48 +02003*/
4
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +02005#include <asm-offsets.h>
Stefan Roesec157d8e2005-08-01 16:41:48 +02006#include <ppc_asm.tmpl>
Stefan Roesecf6eb6d2010-04-14 13:57:18 +02007#include <asm/mmu.h>
Stefan Roesec157d8e2005-08-01 16:41:48 +02008#include <config.h>
9
Stefan Roesec157d8e2005-08-01 16:41:48 +020010/**************************************************************************
11 * TLB TABLE
12 *
13 * This table is used by the cpu boot code to setup the initial tlb
14 * entries. Rather than make broad assumptions in the cpu source tree,
15 * this table lets each board set things up however they like.
16 *
17 * Pointer to the table is returned in r1
18 *
19 *************************************************************************/
20
21 .section .bootpg,"ax"
22 .globl tlbtab
23
24tlbtab:
25 tlbtab_start
Stefan Roese84286382005-08-11 18:03:14 +020026
27 /*
28 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
29 * speed up boot process. It is patched after relocation to enable SA_I
30 */
Stefan Roesecf6eb6d2010-04-14 13:57:18 +020031 tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/)
Stefan Roese84286382005-08-11 18:03:14 +020032
33 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
Stefan Roesecf6eb6d2010-04-14 13:57:18 +020034 tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
Stefan Roese84286382005-08-11 18:03:14 +020035
Stefan Roesecf6eb6d2010-04-14 13:57:18 +020036 tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG )
37 tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG )
38 tlbentry( CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I )
Stefan Roesec157d8e2005-08-01 16:41:48 +020039
40 /* PCI */
Stefan Roesecf6eb6d2010-04-14 13:57:18 +020041 tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG )
42 tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG )
43 tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG )
44 tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG )
Stefan Roesec157d8e2005-08-01 16:41:48 +020045
46 /* USB 2.0 Device */
Stefan Roesecf6eb6d2010-04-14 13:57:18 +020047 tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG )
Stefan Roesec157d8e2005-08-01 16:41:48 +020048
49 tlbtab_end