Bartlomiej Sieka | addb2e1 | 2006-03-05 18:57:33 +0100 | [diff] [blame] | 1 | /* |
| 2 | * linux/include/linux/mtd/nand.h |
| 3 | * |
| 4 | * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com> |
| 5 | * Steven J. Hill <sjhill@cotw.com> |
| 6 | * Thomas Gleixner <gleixner@autronix.de> |
| 7 | * |
| 8 | * $Id: nand.h,v 1.7 2003/07/24 23:30:46 a0384864 Exp $ |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | * |
| 14 | * Info: |
| 15 | * Contains standard defines and IDs for NAND flash devices |
| 16 | * |
| 17 | * Changelog: |
| 18 | * 01-31-2000 DMW Created |
| 19 | * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers |
| 20 | * so it can be used by other NAND flash device |
| 21 | * drivers. I also changed the copyright since none |
| 22 | * of the original contents of this file are specific |
| 23 | * to DoC devices. David can whack me with a baseball |
| 24 | * bat later if I did something naughty. |
| 25 | * 10-11-2000 SJH Added private NAND flash structure for driver |
| 26 | * 10-24-2000 SJH Added prototype for 'nand_scan' function |
| 27 | * 10-29-2001 TG changed nand_chip structure to support |
| 28 | * hardwarespecific function for accessing control lines |
| 29 | * 02-21-2002 TG added support for different read/write adress and |
| 30 | * ready/busy line access function |
| 31 | * 02-26-2002 TG added chip_delay to nand_chip structure to optimize |
| 32 | * command delay times for different chips |
| 33 | * 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate |
| 34 | * defines in jffs2/wbuf.c |
| 35 | */ |
| 36 | #ifndef __LINUX_MTD_NAND_LEGACY_H |
| 37 | #define __LINUX_MTD_NAND_LEGACY_H |
| 38 | |
| 39 | #ifndef CFG_NAND_LEGACY |
| 40 | #error This module is for the legacy NAND support |
| 41 | #endif |
| 42 | |
| 43 | /* |
| 44 | * Standard NAND flash commands |
| 45 | */ |
| 46 | #define NAND_CMD_READ0 0 |
| 47 | #define NAND_CMD_READ1 1 |
| 48 | #define NAND_CMD_PAGEPROG 0x10 |
| 49 | #define NAND_CMD_READOOB 0x50 |
| 50 | #define NAND_CMD_ERASE1 0x60 |
| 51 | #define NAND_CMD_STATUS 0x70 |
| 52 | #define NAND_CMD_SEQIN 0x80 |
| 53 | #define NAND_CMD_READID 0x90 |
| 54 | #define NAND_CMD_ERASE2 0xd0 |
| 55 | #define NAND_CMD_RESET 0xff |
| 56 | |
| 57 | /* |
| 58 | * Enumeration for NAND flash chip state |
| 59 | */ |
| 60 | typedef enum { |
| 61 | FL_READY, |
| 62 | FL_READING, |
| 63 | FL_WRITING, |
| 64 | FL_ERASING, |
| 65 | FL_SYNCING |
| 66 | } nand_state_t; |
| 67 | |
| 68 | |
| 69 | /* |
| 70 | * NAND Private Flash Chip Data |
| 71 | * |
| 72 | * Structure overview: |
| 73 | * |
| 74 | * IO_ADDR - address to access the 8 I/O lines of the flash device |
| 75 | * |
| 76 | * hwcontrol - hardwarespecific function for accesing control-lines |
| 77 | * |
| 78 | * dev_ready - hardwarespecific function for accesing device ready/busy line |
| 79 | * |
| 80 | * chip_lock - spinlock used to protect access to this structure |
| 81 | * |
| 82 | * wq - wait queue to sleep on if a NAND operation is in progress |
| 83 | * |
| 84 | * state - give the current state of the NAND device |
| 85 | * |
| 86 | * page_shift - number of address bits in a page (column address bits) |
| 87 | * |
| 88 | * data_buf - data buffer passed to/from MTD user modules |
| 89 | * |
| 90 | * data_cache - data cache for redundant page access and shadow for |
| 91 | * ECC failure |
| 92 | * |
| 93 | * ecc_code_buf - used only for holding calculated or read ECCs for |
| 94 | * a page read or written when ECC is in use |
| 95 | * |
| 96 | * reserved - padding to make structure fall on word boundary if |
| 97 | * when ECC is in use |
| 98 | */ |
| 99 | struct Nand { |
| 100 | char floor, chip; |
| 101 | unsigned long curadr; |
| 102 | unsigned char curmode; |
| 103 | /* Also some erase/write/pipeline info when we get that far */ |
| 104 | }; |
| 105 | |
| 106 | struct nand_chip { |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 107 | int page_shift; |
| 108 | u_char *data_buf; |
| 109 | u_char *data_cache; |
Bartlomiej Sieka | addb2e1 | 2006-03-05 18:57:33 +0100 | [diff] [blame] | 110 | int cache_page; |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 111 | u_char ecc_code_buf[6]; |
| 112 | u_char reserved[2]; |
Bartlomiej Sieka | addb2e1 | 2006-03-05 18:57:33 +0100 | [diff] [blame] | 113 | char ChipID; /* Type of DiskOnChip */ |
| 114 | struct Nand *chips; |
| 115 | int chipshift; |
| 116 | char* chips_name; |
| 117 | unsigned long erasesize; |
| 118 | unsigned long mfr; /* Flash IDs - only one type of flash per device */ |
| 119 | unsigned long id; |
| 120 | char* name; |
| 121 | int numchips; |
| 122 | char page256; |
| 123 | char pageadrlen; |
| 124 | unsigned long IO_ADDR; /* address to access the 8 I/O lines to the flash device */ |
| 125 | unsigned long totlen; |
| 126 | uint oobblock; /* Size of OOB blocks (e.g. 512) */ |
| 127 | uint oobsize; /* Amount of OOB data per block (e.g. 16) */ |
| 128 | uint eccsize; |
| 129 | int bus16; |
| 130 | }; |
| 131 | |
| 132 | /* |
| 133 | * NAND Flash Manufacturer ID Codes |
| 134 | */ |
| 135 | #define NAND_MFR_TOSHIBA 0x98 |
| 136 | #define NAND_MFR_SAMSUNG 0xec |
| 137 | |
| 138 | /* |
| 139 | * NAND Flash Device ID Structure |
| 140 | * |
| 141 | * Structure overview: |
| 142 | * |
| 143 | * name - Complete name of device |
| 144 | * |
| 145 | * manufacture_id - manufacturer ID code of device. |
| 146 | * |
| 147 | * model_id - model ID code of device. |
| 148 | * |
| 149 | * chipshift - total number of address bits for the device which |
| 150 | * is used to calculate address offsets and the total |
| 151 | * number of bytes the device is capable of. |
| 152 | * |
| 153 | * page256 - denotes if flash device has 256 byte pages or not. |
| 154 | * |
| 155 | * pageadrlen - number of bytes minus one needed to hold the |
| 156 | * complete address into the flash array. Keep in |
| 157 | * mind that when a read or write is done to a |
| 158 | * specific address, the address is input serially |
| 159 | * 8 bits at a time. This structure member is used |
| 160 | * by the read/write routines as a loop index for |
| 161 | * shifting the address out 8 bits at a time. |
| 162 | * |
| 163 | * erasesize - size of an erase block in the flash device. |
| 164 | */ |
| 165 | struct nand_flash_dev { |
| 166 | char * name; |
| 167 | int manufacture_id; |
| 168 | int model_id; |
| 169 | int chipshift; |
| 170 | char page256; |
| 171 | char pageadrlen; |
| 172 | unsigned long erasesize; |
| 173 | int bus16; |
| 174 | }; |
| 175 | |
| 176 | /* |
| 177 | * Constants for oob configuration |
| 178 | */ |
| 179 | #define NAND_NOOB_ECCPOS0 0 |
| 180 | #define NAND_NOOB_ECCPOS1 1 |
| 181 | #define NAND_NOOB_ECCPOS2 2 |
| 182 | #define NAND_NOOB_ECCPOS3 3 |
| 183 | #define NAND_NOOB_ECCPOS4 6 |
| 184 | #define NAND_NOOB_ECCPOS5 7 |
| 185 | #define NAND_NOOB_BADBPOS -1 |
| 186 | #define NAND_NOOB_ECCVPOS -1 |
| 187 | |
| 188 | #define NAND_JFFS2_OOB_ECCPOS0 0 |
| 189 | #define NAND_JFFS2_OOB_ECCPOS1 1 |
| 190 | #define NAND_JFFS2_OOB_ECCPOS2 2 |
| 191 | #define NAND_JFFS2_OOB_ECCPOS3 3 |
| 192 | #define NAND_JFFS2_OOB_ECCPOS4 6 |
| 193 | #define NAND_JFFS2_OOB_ECCPOS5 7 |
| 194 | #define NAND_JFFS2_OOB_BADBPOS 5 |
| 195 | #define NAND_JFFS2_OOB_ECCVPOS 4 |
| 196 | |
| 197 | #define NAND_JFFS2_OOB8_FSDAPOS 6 |
| 198 | #define NAND_JFFS2_OOB16_FSDAPOS 8 |
| 199 | #define NAND_JFFS2_OOB8_FSDALEN 2 |
| 200 | #define NAND_JFFS2_OOB16_FSDALEN 8 |
| 201 | |
| 202 | unsigned long nand_probe(unsigned long physadr); |
| 203 | #endif /* __LINUX_MTD_NAND_LEGACY_H */ |