| Christophe Kerello | 6899385 | 2019-04-05 11:41:49 +0200 | [diff] [blame] | 1 | STMicroelectronics Flexible Memory Controller 2 (FMC2) |
| 2 | NAND Interface |
| 3 | |
| 4 | Required properties: |
| 5 | - compatible: Should be one of: |
| 6 | * st,stm32mp15-fmc2 |
| 7 | - reg: NAND flash controller memory areas. |
| 8 | First region contains the register location. |
| 9 | Regions 2 to 4 respectively contain the data, command, |
| 10 | and address space for CS0. |
| 11 | Regions 5 to 7 contain the same areas for CS1. |
| 12 | - interrupts: The interrupt number |
| 13 | - pinctrl-0: Standard Pinctrl phandle (see: pinctrl/pinctrl-bindings.txt) |
| 14 | - clocks: The clock needed by the NAND flash controller |
| 15 | |
| 16 | Optional properties: |
| 17 | - resets: Reference to a reset controller asserting the FMC controller |
| 18 | - dmas: DMA specifiers (see: dma/stm32-mdma.txt) |
| 19 | - dma-names: Must be "tx", "rx" and "ecc" |
| 20 | |
| Patrick Delaunay | 4f28092 | 2020-01-28 10:10:58 +0100 | [diff] [blame] | 21 | * NAND device bindings: |
| 22 | |
| 23 | Required properties: |
| 24 | - reg: describes the CS lines assigned to the NAND device. |
| Christophe Kerello | 6899385 | 2019-04-05 11:41:49 +0200 | [diff] [blame] | 25 | |
| 26 | Optional properties: |
| 27 | - nand-on-flash-bbt: see nand.txt |
| 28 | - nand-ecc-strength: see nand.txt |
| 29 | - nand-ecc-step-size: see nand.txt |
| 30 | |
| 31 | The following ECC strength and step size are currently supported: |
| 32 | - nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Hamming) |
| 33 | - nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4) |
| 34 | - nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8) (default) |
| 35 | |
| 36 | Example: |
| 37 | |
| 38 | fmc: nand-controller@58002000 { |
| 39 | compatible = "st,stm32mp15-fmc2"; |
| 40 | reg = <0x58002000 0x1000>, |
| 41 | <0x80000000 0x1000>, |
| 42 | <0x88010000 0x1000>, |
| 43 | <0x88020000 0x1000>, |
| 44 | <0x81000000 0x1000>, |
| 45 | <0x89010000 0x1000>, |
| 46 | <0x89020000 0x1000>; |
| 47 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
| 48 | clocks = <&rcc FMC_K>; |
| 49 | resets = <&rcc FMC_R>; |
| 50 | pinctrl-names = "default"; |
| 51 | pinctrl-0 = <&fmc_pins_a>; |
| 52 | #address-cells = <1>; |
| 53 | #size-cells = <0>; |
| 54 | |
| 55 | nand@0 { |
| 56 | reg = <0>; |
| 57 | nand-on-flash-bbt; |
| 58 | #address-cells = <1>; |
| 59 | #size-cells = <1>; |
| 60 | }; |
| 61 | }; |