blob: c4f2520a3b744b1a7ea87a9d5e5c78299ec253fb [file] [log] [blame]
Matt Waddelb80e41a2010-10-07 15:48:45 -06001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8 *
9 * (C) Copyright 2003
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
12 *
13 * (C) Copyright 2004
14 * ARM Ltd.
15 * Philippe Robin, <philippe.robin@arm.com>
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35#include <common.h>
John Rigby10ed93d2012-07-31 08:59:31 +000036#include <malloc.h>
37#include <errno.h>
Matt Waddelb80e41a2010-10-07 15:48:45 -060038#include <netdev.h>
39#include <asm/io.h>
40#include <asm/arch/systimer.h>
41#include <asm/arch/sysctrl.h>
42#include <asm/arch/wdt.h>
Dirk Behmea6f479c2011-05-23 07:40:26 +000043#include "../drivers/mmc/arm_pl180_mmci.h"
Matt Waddelb80e41a2010-10-07 15:48:45 -060044
45static ulong timestamp;
46static ulong lastdec;
47
48static struct wdt *wdt_base = (struct wdt *)WDT_BASE;
49static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE;
50static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
51
52static void flash__init(void);
53static void vexpress_timer_init(void);
54DECLARE_GLOBAL_DATA_PTR;
55
56#if defined(CONFIG_SHOW_BOOT_PROGRESS)
57void show_boot_progress(int progress)
58{
59 printf("Boot reached stage %d\n", progress);
60}
61#endif
62
63static inline void delay(ulong loops)
64{
65 __asm__ volatile ("1:\n"
66 "subs %0, %1, #1\n"
67 "bne 1b" : "=r" (loops) : "0" (loops));
68}
69
70int board_init(void)
71{
72 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
73 gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
74 gd->flags = 0;
75
76 icache_enable();
77 flash__init();
78 vexpress_timer_init();
79
80 return 0;
81}
82
83int board_eth_init(bd_t *bis)
84{
85 int rc = 0;
86#ifdef CONFIG_SMC911X
87 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
88#endif
89 return rc;
90}
91
Matt Waddelf0c64522011-04-16 11:54:08 +000092int cpu_mmc_init(bd_t *bis)
93{
94 int rc = 0;
John Rigby10ed93d2012-07-31 08:59:31 +000095 (void) bis;
Matt Waddelf0c64522011-04-16 11:54:08 +000096#ifdef CONFIG_ARM_PL180_MMCI
John Rigby10ed93d2012-07-31 08:59:31 +000097 struct pl180_mmc_host *host;
98
99 host = malloc(sizeof(struct pl180_mmc_host));
100 if (!host)
101 return -ENOMEM;
102 memset(host, 0, sizeof(*host));
103
104 strcpy(host->name, "MMC");
105 host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
106 host->pwr_init = INIT_PWR;
107 host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN;
108 host->voltages = VOLTAGE_WINDOW_MMC;
109 host->caps = 0;
110 host->clock_in = ARM_MCLK;
111 host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
112 host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
113 rc = arm_pl180_mmci_init(host);
Matt Waddelf0c64522011-04-16 11:54:08 +0000114#endif
115 return rc;
116}
117
Matt Waddelb80e41a2010-10-07 15:48:45 -0600118static void flash__init(void)
119{
120 /* Setup the sytem control register to allow writing to flash */
121 writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
122 &sysctrl_base->scflashctrl);
123}
124
125int dram_init(void)
126{
Matt Waddel9d37cf32010-11-02 17:25:21 -0600127 gd->ram_size =
128 get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
Matt Waddelb80e41a2010-10-07 15:48:45 -0600129 return 0;
130}
131
132void dram_init_banksize(void)
133{
134 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
Matt Waddel9d37cf32010-11-02 17:25:21 -0600135 gd->bd->bi_dram[0].size =
136 get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
Matt Waddelb80e41a2010-10-07 15:48:45 -0600137 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
Matt Waddel9d37cf32010-11-02 17:25:21 -0600138 gd->bd->bi_dram[1].size =
139 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
Matt Waddelb80e41a2010-10-07 15:48:45 -0600140}
141
142int timer_init(void)
143{
144 return 0;
145}
146
147/*
148 * Start timer:
149 * Setup a 32 bit timer, running at 1KHz
150 * Versatile Express Motherboard provides 1 MHz timer
151 */
152static void vexpress_timer_init(void)
153{
154 /*
155 * Set clock frequency in system controller:
156 * VEXPRESS_REFCLK is 32KHz
157 * VEXPRESS_TIMCLK is 1MHz
158 */
159 writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
160 SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
161 readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
162
163 /*
164 * Set Timer0 to be:
165 * Enabled, free running, no interrupt, 32-bit, wrapping
166 */
167 writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
168 writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
Ryan Harkin9b58a3f2013-04-09 02:20:30 +0000169 writel(SYSTIMER_EN | SYSTIMER_32BIT |
170 readl(&systimer_base->timer0control),
Matt Waddelb80e41a2010-10-07 15:48:45 -0600171 &systimer_base->timer0control);
172
173 reset_timer_masked();
174}
175
176/* Use the ARM Watchdog System to cause reset */
177void reset_cpu(ulong addr)
178{
179 writeb(WDT_EN, &wdt_base->wdogcontrol);
180 writel(WDT_RESET_LOAD, &wdt_base->wdogload);
181 while (1)
182 ;
183}
184
185/*
186 * Delay x useconds AND perserve advance timstamp value
187 * assumes timer is ticking at 1 msec
188 */
Dirk Behme44b0a382010-11-29 19:56:59 +0100189void __udelay(ulong usec)
Matt Waddelb80e41a2010-10-07 15:48:45 -0600190{
191 ulong tmo, tmp;
192
193 tmo = usec / 1000;
194 tmp = get_timer(0); /* get current timestamp */
195
196 /*
197 * If setting this forward will roll time stamp then
198 * reset "advancing" timestamp to 0 and set lastdec value
199 * otherwise set the advancing stamp to the wake up time
200 */
201 if ((tmo + tmp + 1) < tmp)
202 reset_timer_masked();
203 else
204 tmo += tmp;
205
206 while (get_timer_masked() < tmo)
207 ; /* loop till wakeup event */
208}
209
210ulong get_timer(ulong base)
211{
212 return get_timer_masked() - base;
213}
214
215void reset_timer_masked(void)
216{
217 lastdec = readl(&systimer_base->timer0value) / 1000;
218 timestamp = 0;
219}
220
Matt Waddelb80e41a2010-10-07 15:48:45 -0600221ulong get_timer_masked(void)
222{
223 ulong now = readl(&systimer_base->timer0value) / 1000;
224
225 if (lastdec >= now) { /* normal mode (non roll) */
226 timestamp += lastdec - now;
227 } else { /* count down timer overflowed */
228 /*
229 * nts = ts + ld - now
230 * ts = old stamp, ld = time before passing through - 1
231 * now = amount of time after passing though - 1
232 * nts = new "advancing time stamp"
233 */
234 timestamp += lastdec + SYSTIMER_RELOAD - now;
235 }
236 lastdec = now;
237
238 return timestamp;
239}
240
241void lowlevel_init(void)
242{
243}
244
245ulong get_board_rev(void){
246 return readl((u32 *)SYS_ID);
247}
Liming Wangd721a3a2012-02-22 04:56:31 +0000248
249unsigned long long get_ticks(void)
250{
251 return get_timer(0);
252}
253
Ryan Harkin9b58a3f2013-04-09 02:20:30 +0000254ulong get_tbclk(void)
Liming Wangd721a3a2012-02-22 04:56:31 +0000255{
256 return (ulong)CONFIG_SYS_HZ;
257}