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Nobuhiro Iwamatsu1086bfa2013-09-27 16:58:30 +09001/*
2 * drivers/i2c/rcar_i2c.c
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0
8 */
9
10#include <common.h>
11#include <i2c.h>
12#include <asm/io.h>
13
14DECLARE_GLOBAL_DATA_PTR;
15
16struct rcar_i2c {
17 u32 icscr;
18 u32 icmcr;
19 u32 icssr;
20 u32 icmsr;
21 u32 icsier;
22 u32 icmier;
23 u32 icccr;
24 u32 icsar;
25 u32 icmar;
26 u32 icrxdtxd;
27 u32 icccr2;
28 u32 icmpr;
29 u32 ichpr;
30 u32 iclpr;
31};
32
33#define MCR_MDBS 0x80 /* non-fifo mode switch */
34#define MCR_FSCL 0x40 /* override SCL pin */
35#define MCR_FSDA 0x20 /* override SDA pin */
36#define MCR_OBPC 0x10 /* override pins */
37#define MCR_MIE 0x08 /* master if enable */
38#define MCR_TSBE 0x04
39#define MCR_FSB 0x02 /* force stop bit */
40#define MCR_ESG 0x01 /* en startbit gen. */
41
42#define MSR_MASK 0x7f
43#define MSR_MNR 0x40 /* nack received */
44#define MSR_MAL 0x20 /* arbitration lost */
45#define MSR_MST 0x10 /* sent a stop */
46#define MSR_MDE 0x08
47#define MSR_MDT 0x04
48#define MSR_MDR 0x02
49#define MSR_MAT 0x01 /* slave addr xfer done */
50
51static const struct rcar_i2c *i2c_dev[CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS] = {
52 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C0_BASE,
53 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C1_BASE,
54 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C2_BASE,
55 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C3_BASE,
56};
57
58static void rcar_i2c_raw_rw_common(struct rcar_i2c *dev, u8 chip, uint addr)
59{
60 /* set slave address */
61 writel(chip << 1, &dev->icmar);
62 /* set register address */
63 writel(addr, &dev->icrxdtxd);
64 /* clear status */
65 writel(0, &dev->icmsr);
66 /* start master send */
67 writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr);
68
69 while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDE))
70 != (MSR_MAT | MSR_MDE))
71 udelay(10);
72
73 /* clear ESG */
74 writel(MCR_MDBS | MCR_MIE, &dev->icmcr);
75 /* start SCLclk */
76 writel(~(MSR_MAT | MSR_MDE), &dev->icmsr);
77
78 while (!(readl(&dev->icmsr) & MSR_MDE))
79 udelay(10);
80}
81
82static void rcar_i2c_raw_rw_finish(struct rcar_i2c *dev)
83{
84 while (!(readl(&dev->icmsr) & MSR_MST))
85 udelay(10);
86
87 writel(0, &dev->icmcr);
88}
89
90static int
91rcar_i2c_raw_write(struct rcar_i2c *dev, u8 chip, uint addr, u8 *val, int size)
92{
93 rcar_i2c_raw_rw_common(dev, chip, addr);
94
95 /* set send date */
96 writel(*val, &dev->icrxdtxd);
97 /* start SCLclk */
98 writel(~MSR_MDE, &dev->icmsr);
99
100 while (!(readl(&dev->icmsr) & MSR_MDE))
101 udelay(10);
102
103 /* set stop condition */
104 writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr);
105 /* start SCLclk */
106 writel(~MSR_MDE, &dev->icmsr);
107
108 rcar_i2c_raw_rw_finish(dev);
109
110 return 0;
111}
112
113static u8
114rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr)
115{
116 u8 ret;
117
118 rcar_i2c_raw_rw_common(dev, chip, addr);
119
120 /* set slave address, receive */
121 writel((chip << 1) | 1, &dev->icmar);
Nobuhiro Iwamatsuda1ed0d2013-12-11 15:49:28 +0900122 /* clear status */
123 writel(0, &dev->icmsr);
Nobuhiro Iwamatsu1086bfa2013-09-27 16:58:30 +0900124 /* start master receive */
125 writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr);
126
Hisashi Nakamuraad5e14e2013-12-11 15:49:27 +0900127 while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDR))
128 != (MSR_MAT | MSR_MDR))
Nobuhiro Iwamatsu1086bfa2013-09-27 16:58:30 +0900129 udelay(10);
130
131 /* clear ESG */
132 writel(MCR_MDBS | MCR_MIE, &dev->icmcr);
133 /* prepare stop condition */
134 writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr);
135 /* start SCLclk */
136 writel(~(MSR_MAT | MSR_MDR), &dev->icmsr);
137
138 while (!(readl(&dev->icmsr) & MSR_MDR))
139 udelay(10);
140
141 /* get receive data */
142 ret = (u8)readl(&dev->icrxdtxd);
143 /* start SCLclk */
144 writel(~MSR_MDR, &dev->icmsr);
145
146 rcar_i2c_raw_rw_finish(dev);
147
148 return ret;
149}
150
151/*
152 * SCL = iicck / (20 + SCGD * 8 + F[(ticf + tr + intd) * iicck])
153 * iicck : I2C internal clock < 20 MHz
154 * ticf : I2C SCL falling time: 35 ns
155 * tr : I2C SCL rising time: 200 ns
156 * intd : LSI internal delay: I2C0: 50 ns I2C1-3: 5
157 * F[n] : n rounded up to an integer
158 */
159static u32 rcar_clock_gen(int i2c_no, u32 bus_speed)
160{
161 u32 iicck, f, scl, scgd;
162 u32 intd = 5;
163
164 int bit = 0, cdf_width = 3;
165 for (bit = 0; bit < (1 << cdf_width); bit++) {
166 iicck = CONFIG_HP_CLK_FREQ / (1 + bit);
167 if (iicck < 20000000)
168 break;
169 }
170
171 if (bit > (1 << cdf_width)) {
172 puts("rcar-i2c: Can not get CDF\n");
173 return 0;
174 }
175
176 if (i2c_no == 0)
177 intd = 50;
178
179 f = (35 + 200 + intd) * (iicck / 1000000000);
180
181 for (scgd = 0; scgd < 0x40; scgd++) {
182 scl = iicck / (20 + (scgd * 8) + f);
183 if (scl <= bus_speed)
184 break;
185 }
186
187 if (scgd > 0x40) {
188 puts("rcar-i2c: Can not get SDGB\n");
189 return 0;
190 }
191
192 debug("%s: scl: %d\n", __func__, scl);
193 debug("%s: bit %x\n", __func__, bit);
194 debug("%s: scgd %x\n", __func__, scgd);
195 debug("%s: iccr %x\n", __func__, (scgd << (cdf_width) | bit));
196
197 return scgd << (cdf_width) | bit;
198}
199
200static void
201rcar_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
202{
203 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
204 u32 icccr = 0;
205
206 /* No i2c support prior to relocation */
207 if (!(gd->flags & GD_FLG_RELOC))
208 return;
209
210 /*
211 * reset slave mode.
212 * slave mode is not used on this driver
213 */
214 writel(0, &dev->icsier);
215 writel(0, &dev->icsar);
216 writel(0, &dev->icscr);
217 writel(0, &dev->icssr);
218
219 /* reset master mode */
220 writel(0, &dev->icmier);
221 writel(0, &dev->icmcr);
222 writel(0, &dev->icmsr);
223 writel(0, &dev->icmar);
224
225 icccr = rcar_clock_gen(adap->hwadapnr, adap->speed);
226 if (icccr == 0)
227 puts("I2C: Init failed\n");
228 else
229 writel(icccr, &dev->icccr);
230}
231
232static int rcar_i2c_read(struct i2c_adapter *adap, uint8_t chip,
233 uint addr, int alen, u8 *data, int len)
234{
235 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
236 int i;
237
238 for (i = 0; i < len; i++)
239 data[i] = rcar_i2c_raw_read(dev, chip, addr + i);
240
241 return 0;
242}
243
244static int rcar_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
245 int alen, u8 *data, int len)
246{
247 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
248 return rcar_i2c_raw_write(dev, chip, addr, data, len);
249}
250
251static int
252rcar_i2c_probe(struct i2c_adapter *adap, u8 dev)
253{
254 return rcar_i2c_read(adap, dev, 0, 0, NULL, 0);
255}
256
257static unsigned int rcar_i2c_set_bus_speed(struct i2c_adapter *adap,
258 unsigned int speed)
259{
260 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr];
261 u32 icccr;
262 int ret = 0;
263
264 rcar_i2c_raw_rw_finish(dev);
265
266 icccr = rcar_clock_gen(adap->hwadapnr, speed);
267 if (icccr == 0) {
268 puts("I2C: Init failed\n");
269 ret = -1;
270 } else {
271 writel(icccr, &dev->icccr);
272 }
273 return ret;
274}
275
276/*
277 * Register RCAR i2c adapters
278 */
279U_BOOT_I2C_ADAP_COMPLETE(rcar_0, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
280 rcar_i2c_write, rcar_i2c_set_bus_speed,
281 CONFIG_SYS_RCAR_I2C0_SPEED, 0, 0)
282U_BOOT_I2C_ADAP_COMPLETE(rcar_1, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
283 rcar_i2c_write, rcar_i2c_set_bus_speed,
284 CONFIG_SYS_RCAR_I2C1_SPEED, 0, 1)
285U_BOOT_I2C_ADAP_COMPLETE(rcar_2, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
286 rcar_i2c_write, rcar_i2c_set_bus_speed,
287 CONFIG_SYS_RCAR_I2C2_SPEED, 0, 2)
288U_BOOT_I2C_ADAP_COMPLETE(rcar_3, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read,
289 rcar_i2c_write, rcar_i2c_set_bus_speed,
290 CONFIG_SYS_RCAR_I2C3_SPEED, 0, 3)