blob: edcb7aacb8ee6e3062e5b5ce60e788af92435c4c [file] [log] [blame]
Stephen Warrenc7ba99c2016-05-12 13:32:55 -06001#include "skeleton.dtsi"
Stephen Warren19014202016-07-27 15:24:51 -06002#include <dt-bindings/clock/tegra186-clock.h>
Stephen Warren03886342016-07-18 12:15:03 -06003#include <dt-bindings/gpio/tegra186-gpio.h>
Stephen Warrenc7ba99c2016-05-12 13:32:55 -06004#include <dt-bindings/interrupt-controller/arm-gic.h>
Stephen Warren729c2db2016-07-27 15:24:49 -06005#include <dt-bindings/mailbox/tegra186-hsp.h>
Stephen Warren20bbde02016-07-27 15:48:19 -06006#include <dt-bindings/power/tegra186-powergate.h>
Stephen Warren19014202016-07-27 15:24:51 -06007#include <dt-bindings/reset/tegra186-reset.h>
Stephen Warrenc7ba99c2016-05-12 13:32:55 -06008
9/ {
10 compatible = "nvidia,tegra186";
Stephen Warren20bbde02016-07-27 15:48:19 -060011 interrupt-parent = <&gic>;
Stephen Warrenc7ba99c2016-05-12 13:32:55 -060012 #address-cells = <2>;
13 #size-cells = <2>;
14
Stephen Warren19014202016-07-27 15:24:51 -060015 gpio_main: gpio@2200000 {
Stephen Warrenc7ba99c2016-05-12 13:32:55 -060016 compatible = "nvidia,tegra186-gpio";
17 reg-names = "security", "gpio";
18 reg =
19 <0x0 0x2200000 0x0 0x10000>,
20 <0x0 0x2210000 0x0 0x10000>;
21 interrupts =
22 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
23 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
24 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
25 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
26 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
27 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
28 gpio-controller;
29 #gpio-cells = <2>;
30 interrupt-controller;
31 #interrupt-cells = <2>;
32 };
33
Stephen Warren31c1ff92016-09-12 11:51:14 -060034 ethernet@2490000 {
35 compatible = "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10";
36 reg = <0x0 0x02490000 0x0 0x10000>;
37 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
38 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
39 <&bpmp TEGRA186_CLK_EQOS_AXI>,
40 <&bpmp TEGRA186_CLK_EQOS_RX>,
41 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>,
42 <&bpmp TEGRA186_CLK_EQOS_TX>;
43 clock-names = "slave_bus",
44 "master_bus",
45 "rx",
46 "ptp_ref",
47 "tx";
48 resets = <&bpmp TEGRA186_RESET_EQOS>;
49 reset-names = "eqos";
50 phy-mode = "rgmii";
51 status = "disabled";
52 };
53
Stephen Warrenc7ba99c2016-05-12 13:32:55 -060054 uarta: serial@3100000 {
55 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
56 reg = <0x0 0x03100000 0x0 0x10000>;
57 reg-shift = <2>;
58 status = "disabled";
59 };
60
Bryan Wu9e613de2016-07-27 15:48:21 -060061 gen1_i2c: i2c@3160000 {
62 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
63 reg = <0x0 0x3160000 0x0 0x100>;
64 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
65 #address-cells = <1>;
66 #size-cells = <0>;
67 clocks = <&bpmp TEGRA186_CLK_I2C1>;
Stephen Warrenb4ee0812016-08-18 11:08:43 -060068 clock-names = "div-clk";
Bryan Wu9e613de2016-07-27 15:48:21 -060069 resets = <&bpmp TEGRA186_RESET_I2C1>;
70 reset-names = "i2c";
71 status = "disabled";
72 };
73
74 cam_i2c: i2c@3180000 {
75 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
76 reg = <0x0 0x3180000 0x0 0x100>;
77 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
78 #address-cells = <1>;
79 #size-cells = <0>;
80 clocks = <&bpmp TEGRA186_CLK_I2C3>;
Stephen Warrenb4ee0812016-08-18 11:08:43 -060081 clock-names = "div-clk";
Bryan Wu9e613de2016-07-27 15:48:21 -060082 resets = <&bpmp TEGRA186_RESET_I2C3>;
83 reset-names = "i2c";
84 status = "disabled";
85 };
86
87 dp_aux_ch1_i2c: i2c@3190000 {
88 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
89 reg = <0x0 0x3190000 0x0 0x100>;
90 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
91 #address-cells = <1>;
92 #size-cells = <0>;
93 clocks = <&bpmp TEGRA186_CLK_I2C4>;
Stephen Warrenb4ee0812016-08-18 11:08:43 -060094 clock-names = "div-clk";
Bryan Wu9e613de2016-07-27 15:48:21 -060095 resets = <&bpmp TEGRA186_RESET_I2C4>;
96 reset-names = "i2c";
97 status = "disabled";
98 };
99
100 dp_aux_ch0_i2c: i2c@31b0000 {
101 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
102 reg = <0x0 0x31b0000 0x0 0x100>;
103 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
104 #address-cells = <1>;
105 #size-cells = <0>;
106 clocks = <&bpmp TEGRA186_CLK_I2C6>;
Stephen Warrenb4ee0812016-08-18 11:08:43 -0600107 clock-names = "div-clk";
Bryan Wu9e613de2016-07-27 15:48:21 -0600108 resets = <&bpmp TEGRA186_RESET_I2C6>;
109 reset-names = "i2c";
110 status = "disabled";
111 };
112
113 gen7_i2c: i2c@31c0000 {
114 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
115 reg = <0x0 0x31c0000 0x0 0x100>;
116 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
117 #address-cells = <1>;
118 #size-cells = <0>;
119 clocks = <&bpmp TEGRA186_CLK_I2C7>;
Stephen Warrenb4ee0812016-08-18 11:08:43 -0600120 clock-names = "div-clk";
Bryan Wu9e613de2016-07-27 15:48:21 -0600121 resets = <&bpmp TEGRA186_RESET_I2C7>;
122 reset-names = "i2c";
123 status = "disabled";
124 };
125
126 gen9_i2c: i2c@31e0000 {
127 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
128 reg = <0x0 0x31e0000 0x0 0x100>;
129 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
130 #address-cells = <1>;
131 #size-cells = <0>;
132 clocks = <&bpmp TEGRA186_CLK_I2C9>;
Stephen Warrenb4ee0812016-08-18 11:08:43 -0600133 clock-names = "div-clk";
Bryan Wu9e613de2016-07-27 15:48:21 -0600134 resets = <&bpmp TEGRA186_RESET_I2C9>;
135 reset-names = "i2c";
136 status = "disabled";
137 };
138
Stephen Warren19014202016-07-27 15:24:51 -0600139 sdhci@3400000 {
140 compatible = "nvidia,tegra186-sdhci";
141 reg = <0x0 0x03400000 0x0 0x200>;
142 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
Stephen Warreneb3f68a2016-08-18 11:08:44 -0600143 reset-names = "sdhci";
Stephen Warren19014202016-07-27 15:24:51 -0600144 clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
Stephen Warren19014202016-07-27 15:24:51 -0600145 interrupts = <GIC_SPI 62 0x04>;
146 status = "disabled";
147 };
148
Stephen Warrenc7ba99c2016-05-12 13:32:55 -0600149 sdhci@3460000 {
150 compatible = "nvidia,tegra186-sdhci";
151 reg = <0x0 0x03460000 0x0 0x200>;
Stephen Warren19014202016-07-27 15:24:51 -0600152 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
Stephen Warreneb3f68a2016-08-18 11:08:44 -0600153 reset-names = "sdhci";
Stephen Warren19014202016-07-27 15:24:51 -0600154 clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
Stephen Warrenc7ba99c2016-05-12 13:32:55 -0600155 interrupts = <GIC_SPI 31 0x04>;
156 status = "disabled";
157 };
158
Stephen Warren20bbde02016-07-27 15:48:19 -0600159 gic: interrupt-controller@3881000 {
160 compatible = "arm,gic-400";
161 #interrupt-cells = <3>;
162 interrupt-controller;
163 reg = <0x0 0x3881000 0x0 0x1000>,
164 <0x0 0x3882000 0x0 0x2000>,
165 <0x0 0x3884000 0x0 0x2000>,
166 <0x0 0x3886000 0x0 0x2000>;
167 interrupts = <GIC_PPI 9
168 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
169 interrupt-parent = <&gic>;
170 };
171
Stephen Warren0f67e232016-06-17 09:43:57 -0600172 hsp: hsp@3c00000 {
173 compatible = "nvidia,tegra186-hsp";
174 reg = <0x0 0x03c00000 0x0 0xa0000>;
175 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren729c2db2016-07-27 15:24:49 -0600176 interrupt-names = "doorbell";
177 #mbox-cells = <2>;
Stephen Warren0f67e232016-06-17 09:43:57 -0600178 };
179
Bryan Wu9e613de2016-07-27 15:48:21 -0600180 gen2_i2c: i2c@c240000 {
181 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
182 reg = <0x0 0xc240000 0x0 0x100>;
183 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
184 #address-cells = <1>;
185 #size-cells = <0>;
186 clocks = <&bpmp TEGRA186_CLK_I2C2>;
Stephen Warrenb4ee0812016-08-18 11:08:43 -0600187 clock-names = "div-clk";
Bryan Wu9e613de2016-07-27 15:48:21 -0600188 resets = <&bpmp TEGRA186_RESET_I2C2>;
189 reset-names = "i2c";
190 status = "disabled";
191 };
192
193 gen8_i2c: i2c@c250000 {
194 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
195 reg = <0x0 0xc250000 0x0 0x100>;
196 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
197 #address-cells = <1>;
198 #size-cells = <0>;
199 clocks = <&bpmp TEGRA186_CLK_I2C8>;
Stephen Warrenb4ee0812016-08-18 11:08:43 -0600200 clock-names = "div-clk";
Bryan Wu9e613de2016-07-27 15:48:21 -0600201 resets = <&bpmp TEGRA186_RESET_I2C8>;
202 reset-names = "i2c";
203 status = "disabled";
204 };
205
Stephen Warren19014202016-07-27 15:24:51 -0600206 gpio_aon: gpio@c2f0000 {
Stephen Warrenc7ba99c2016-05-12 13:32:55 -0600207 compatible = "nvidia,tegra186-gpio-aon";
208 reg-names = "security", "gpio";
209 reg =
210 <0x0 0xc2f0000 0x0 0x1000>,
211 <0x0 0xc2f1000 0x0 0x1000>;
212 interrupts =
213 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
214 gpio-controller;
215 #gpio-cells = <2>;
216 interrupt-controller;
217 #interrupt-cells = <2>;
218 };
Stephen Warren19014202016-07-27 15:24:51 -0600219
Thierry Reding1e669b42019-04-15 11:32:37 +0200220 pcie@10003000 {
Stephen Warren20bbde02016-07-27 15:48:19 -0600221 compatible = "nvidia,tegra186-pcie";
222 device_type = "pci";
223 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
224 0x0 0x10003800 0x0 0x00000800 /* AFI registers */
225 0x0 0x40000000 0x0 0x10000000>; /* configuration space */
226 reg-names = "pads", "afi", "cs";
227 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
228 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, /* MSI interrupt */
229 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; /* Wake interrupt */
230 interrupt-names = "intr", "msi", "wake";
231
232 #interrupt-cells = <1>;
233 interrupt-map-mask = <0 0 0 0>;
234 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
235
236 bus-range = <0x00 0xff>;
237 #address-cells = <3>;
238 #size-cells = <2>;
239
240 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
241 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
242 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
243 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
244 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07f00000 /* non-prefetchable memory (127 MiB) */
245 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
246
247 clocks = <&bpmp TEGRA186_CLK_PCIE>,
248 <&bpmp TEGRA186_CLK_AFI>;
249 clock-names = "pex", "afi";
250 resets = <&bpmp TEGRA186_RESET_PCIE>,
251 <&bpmp TEGRA186_RESET_AFI>,
252 <&bpmp TEGRA186_RESET_PCIEXCLK>;
253 reset-names = "pex", "afi", "pcie_x";
254 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
255 status = "disabled";
256
257 pci@1,0 {
258 device_type = "pci";
259 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
260 reg = <0x000800 0 0 0 0>;
261 status = "disabled";
262
263 #address-cells = <3>;
264 #size-cells = <2>;
265 ranges;
266
267 nvidia,num-lanes = <2>;
268 };
269
270 pci@2,0 {
271 device_type = "pci";
272 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
273 reg = <0x001000 0 0 0 0>;
274 status = "disabled";
275
276 #address-cells = <3>;
277 #size-cells = <2>;
278 ranges;
279
280 nvidia,num-lanes = <1>;
281 };
282
283 pci@3,0 {
284 device_type = "pci";
285 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
286 reg = <0x001800 0 0 0 0>;
287 status = "disabled";
288
289 #address-cells = <3>;
290 #size-cells = <2>;
291 ranges;
292
293 nvidia,num-lanes = <1>;
294 };
295 };
296
Stephen Warren19014202016-07-27 15:24:51 -0600297 sysram@30000000 {
298 compatible = "nvidia,tegra186-sysram", "mmio-sram";
299 reg = <0x0 0x30000000 0x0 0x50000>;
300 #address-cells = <2>;
301 #size-cells = <2>;
302 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
303
304 sysram_cpu_bpmp_tx: shmem@4e000 {
305 compatible = "nvidia,tegra186-bpmp-shmem";
306 reg = <0x0 0x4e000 0x0 0x1000>;
307 };
308
309 sysram_cpu_bpmp_rx: shmem@4f000 {
310 compatible = "nvidia,tegra186-bpmp-shmem";
311 reg = <0x0 0x4f000 0x0 0x1000>;
312 };
313 };
314
315 bpmp: bpmp {
316 compatible = "nvidia,tegra186-bpmp";
317 mboxes = <&hsp HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>;
318 /*
319 * In theory, these references, and the configuration in the
320 * node these reference point at, are board-specific, since
321 * they depend on the BCT's memory carve-out setup, the
322 * firmware that's actually loaded onto the BPMP, etc. However,
323 * in practice, all boards are likely to use identical values.
324 */
325 shmem = <&sysram_cpu_bpmp_tx &sysram_cpu_bpmp_rx>;
326 #clock-cells = <1>;
327 #power-domain-cells = <1>;
328 #reset-cells = <1>;
Stephen Warren23ab5bd2016-07-29 13:15:04 -0600329
330 bpmp_i2c: i2c {
331 compatible = "nvidia,tegra186-bpmp-i2c";
Stephen Warren23ab5bd2016-07-29 13:15:04 -0600332 nvidia,bpmp-bus-id = <5>;
333 #address-cells = <1>;
334 #size-cells = <0>;
335 status = "disabled";
336 };
Stephen Warren19014202016-07-27 15:24:51 -0600337 };
Jon Hunter1ec74532020-06-18 12:54:39 +0100338
339 psci {
340 compatible = "arm,psci-1.0";
341 method = "smc";
342 };
Stephen Warrenc7ba99c2016-05-12 13:32:55 -0600343};