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Stefan Roese779e9752007-08-14 14:44:41 +02001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/************************************************************************
25 * zeus.h - configuration for Zeus board
26 ***********************************************************************/
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*-----------------------------------------------------------------------
31 * High Level Configuration Options
32 *----------------------------------------------------------------------*/
33#define CONFIG_ZEUS 1 /* Board is Zeus */
34#define CONFIG_4xx 1 /* ... PPC4xx family */
35#define CONFIG_405EP 1 /* Specifc 405EP support*/
36
37#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
38
39#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
40#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
41
42#define PLLMR0_DEFAULT PLLMR0_333_111_55_111
43#define PLLMR1_DEFAULT PLLMR1_333_111_55_111
44
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020045#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese779e9752007-08-14 14:44:41 +020046
47#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
48
Ben Warren96e21f82008-10-27 23:50:15 -070049#define CONFIG_PPC4xx_EMAC
Stefan Roese779e9752007-08-14 14:44:41 +020050#define CONFIG_MII 1 /* MII PHY management */
51#define CONFIG_PHY_ADDR 0x01 /* PHY address */
52#define CONFIG_HAS_ETH1 1
53#define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */
54#define CONFIG_NET_MULTI 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
Stefan Roese779e9752007-08-14 14:44:41 +020056#define CONFIG_PHY_RESET 1
57#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
58
Stefan Roese3b3bff42007-08-14 16:36:29 +020059/*
60 * BOOTP options
61 */
62#define CONFIG_BOOTP_BOOTFILESIZE
63#define CONFIG_BOOTP_BOOTPATH
64#define CONFIG_BOOTP_GATEWAY
65#define CONFIG_BOOTP_HOSTNAME
66
67/*
68 * Command line configuration.
69 */
70#include <config_cmd_default.h>
71
72#define CONFIG_CMD_ASKENV
73#define CONFIG_CMD_CACHE
74#define CONFIG_CMD_DHCP
75#define CONFIG_CMD_DIAG
76#define CONFIG_CMD_EEPROM
77#define CONFIG_CMD_ELF
78#define CONFIG_CMD_I2C
79#define CONFIG_CMD_IRQ
80#define CONFIG_CMD_LOG
81#define CONFIG_CMD_MII
82#define CONFIG_CMD_NET
83#define CONFIG_CMD_NFS
84#define CONFIG_CMD_PING
85#define CONFIG_CMD_REGINFO
Stefan Roese779e9752007-08-14 14:44:41 +020086
87/* POST support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
89 CONFIG_SYS_POST_CPU | \
90 CONFIG_SYS_POST_CACHE | \
91 CONFIG_SYS_POST_UART | \
92 CONFIG_SYS_POST_ETHER)
Stefan Roese779e9752007-08-14 14:44:41 +020093
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */
Stefan Roese779e9752007-08-14 14:44:41 +020095
96/* Define here the base-addresses of the UARTs to test in POST */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE}
Stefan Roese779e9752007-08-14 14:44:41 +020098
99#define CONFIG_LOGBUFFER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
Stefan Roese779e9752007-08-14 14:44:41 +0200101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
Stefan Roese779e9752007-08-14 14:44:41 +0200103
Stefan Roese779e9752007-08-14 14:44:41 +0200104#undef CONFIG_WATCHDOG /* watchdog disabled */
105
106/*-----------------------------------------------------------------------
107 * SDRAM
108 *----------------------------------------------------------------------*/
109/*
110 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
111 */
112#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
113#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
114
115/* SDRAM timings used in datasheet */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
117#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
118#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
119#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
120#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
Stefan Roese779e9752007-08-14 14:44:41 +0200121
122/*-----------------------------------------------------------------------
123 * Serial Port
124 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
126#define CONFIG_SYS_BASE_BAUD 691200
Stefan Roese779e9752007-08-14 14:44:41 +0200127#define CONFIG_BAUDRATE 115200
128#define CONFIG_SERIAL_MULTI
129
130/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_BAUDRATE_TABLE \
Stefan Roese779e9752007-08-14 14:44:41 +0200132 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
133
134/*-----------------------------------------------------------------------
135 * Miscellaneous configurable options
136 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_LONGHELP /* undef to save memory */
138#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Stefan Roese3b3bff42007-08-14 16:36:29 +0200139#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roese779e9752007-08-14 14:44:41 +0200141#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roese779e9752007-08-14 14:44:41 +0200143#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
145#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
146#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Stefan Roese779e9752007-08-14 14:44:41 +0200147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
149#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Stefan Roese779e9752007-08-14 14:44:41 +0200150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
152#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Stefan Roese779e9752007-08-14 14:44:41 +0200153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Stefan Roese779e9752007-08-14 14:44:41 +0200155
156#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Stefan Roese779e9752007-08-14 14:44:41 +0200158
159#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
160#define CONFIG_LOOPW 1 /* enable loopw command */
161#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
162#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
163#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
164
165/*-----------------------------------------------------------------------
166 * I2C
167 *----------------------------------------------------------------------*/
168#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
169#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
171#define CONFIG_SYS_I2C_SLAVE 0x7F
Stefan Roese779e9752007-08-14 14:44:41 +0200172
173/* these are for the ST M24C02 2kbit serial i2c eeprom */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
175#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
Stefan Roese779e9752007-08-14 14:44:41 +0200176/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
Stefan Roese779e9752007-08-14 14:44:41 +0200178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */
180#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
Stefan Roese779e9752007-08-14 14:44:41 +0200181
182/*
183 * The layout of the I2C EEPROM, used for bootstrap setup and for board-
184 * specific values, like ethaddr... that can be restored via the sw-reset
185 * button
186 */
187#define FACTORY_RESET_I2C_EEPROM 0x50
188#define FACTORY_RESET_ENV_OFFS 0x80
189#define FACTORY_RESET_ENV_SIZE 0x80
190
191/*-----------------------------------------------------------------------
192 * Start addresses for the final memory configuration
193 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Stefan Roese779e9752007-08-14 14:44:41 +0200195 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_SDRAM_BASE 0x00000000
197#define CONFIG_SYS_FLASH_BASE 0xFF000000
198#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
199#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
200#define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN)
Stefan Roese779e9752007-08-14 14:44:41 +0200201
202/*
203 * For booting Linux, the board info and command line data
204 * have to be in the first 8 MB of memory, since this is
205 * the maximum mapped by the Linux kernel during initialization.
206 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roese779e9752007-08-14 14:44:41 +0200208
209/*-----------------------------------------------------------------------
210 * FLASH organization
211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200213#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Stefan Roese779e9752007-08-14 14:44:41 +0200214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Stefan Roese779e9752007-08-14 14:44:41 +0200216
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
218#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Stefan Roese779e9752007-08-14 14:44:41 +0200219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
221#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese779e9752007-08-14 14:44:41 +0200222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
224#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
Stefan Roese779e9752007-08-14 14:44:41 +0200225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
227#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Stefan Roese779e9752007-08-14 14:44:41 +0200228
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200229#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200230#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200232#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Stefan Roese779e9752007-08-14 14:44:41 +0200233
234/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200235#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
236#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese779e9752007-08-14 14:44:41 +0200237#endif
238
239/*-----------------------------------------------------------------------
Stefan Roese779e9752007-08-14 14:44:41 +0200240 * Definitions for initial stack pointer and data area (in data cache)
241 */
242/* use on chip memory (OCM) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_TEMP_STACK_OCM 1
Stefan Roese779e9752007-08-14 14:44:41 +0200244
245/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
247#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
248#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */
249#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
Stefan Roese779e9752007-08-14 14:44:41 +0200250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
252#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
Stefan Roese779e9752007-08-14 14:44:41 +0200253/* reserve some memory for POST and BOOT limit info */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 16)
Stefan Roese779e9752007-08-14 14:44:41 +0200255
256/* extra data in OCM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 4)
258#define CONFIG_SYS_POST_MAGIC (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 8)
259#define CONFIG_SYS_POST_VAL (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 12)
Stefan Roese779e9752007-08-14 14:44:41 +0200260
261/*-----------------------------------------------------------------------
262 * External Bus Controller (EBC) Setup
263 */
264
265/* Memory Bank 0 (Flash 16M) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_EBC_PB0AP 0x05815600
267#define CONFIG_SYS_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
Stefan Roese779e9752007-08-14 14:44:41 +0200268
269/*-----------------------------------------------------------------------
270 * Definitions for GPIO setup (PPC405EP specific)
271 *
272 * GPIO0[0] - External Bus Controller BLAST output
273 * GPIO0[1-9] - Instruction trace outputs
274 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
275 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
276 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
277 * GPIO0[24-27] - UART0 control signal inputs/outputs
278 * GPIO0[28-29] - UART1 data signal input/output
279 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
280 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_GPIO0_OSRH 0x15555550 /* Chip selects */
282#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* UART_DTR-pin 27 alt out */
283#define CONFIG_SYS_GPIO0_ISR1H 0x10000041 /* Pin 2, 12 is input */
284#define CONFIG_SYS_GPIO0_ISR1L 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
285#define CONFIG_SYS_GPIO0_TSRH 0x00000000
286#define CONFIG_SYS_GPIO0_TSRL 0x00000000
287#define CONFIG_SYS_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */
288#define CONFIG_SYS_GPIO0_ODR 0x00000000
Stefan Roese779e9752007-08-14 14:44:41 +0200289
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_GPIO_SW_RESET 1
291#define CONFIG_SYS_GPIO_ZEUS_PE 12
292#define CONFIG_SYS_GPIO_LED_RED 22
293#define CONFIG_SYS_GPIO_LED_GREEN 23
Stefan Roese779e9752007-08-14 14:44:41 +0200294
295/* Time in milli-seconds */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_TIME_POST 5000
297#define CONFIG_SYS_TIME_FACTORY_RESET 10000
Stefan Roese779e9752007-08-14 14:44:41 +0200298
299/*
300 * Internal Definitions
301 *
302 * Boot Flags
303 */
304#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
305#define BOOTFLAG_WARM 0x02 /* Software reboot */
306
Stefan Roese3b3bff42007-08-14 16:36:29 +0200307#if defined(CONFIG_CMD_KGDB)
Stefan Roese779e9752007-08-14 14:44:41 +0200308#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
309#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
310#endif
311
Stefan Roeseb18410e2008-09-11 13:05:56 +0200312/*
313 * Pass open firmware flat tree
314 */
315#define CONFIG_OF_LIBFDT
316#define CONFIG_OF_BOARD_SETUP
317
Stefan Roese779e9752007-08-14 14:44:41 +0200318/* ENVIRONMENT VARS */
319
320#define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo"
321#define CONFIG_IPADDR 192.168.1.10
322#define CONFIG_SERVERIP 192.168.1.100
323#define CONFIG_GATEWAYIP 192.168.1.100
324#define CONFIG_ETHADDR 50:00:00:00:06:00
325#define CONFIG_ETH1ADDR 50:00:00:00:06:01
326#if 0
327#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
328#else
329#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
330#endif
331
332#define CONFIG_EXTRA_ENV_SETTINGS \
333 "logversion=2\0" \
334 "hostname=zeus\0" \
335 "netdev=eth0\0" \
336 "ethact=ppc_4xx_eth0\0" \
337 "netmask=255.255.255.0\0" \
338 "ramdisk_size=50000\0" \
339 "nfsargs=setenv bootargs root=/dev/nfs rw" \
340 " nfsroot=${serverip}:${rootpath}\0" \
341 "ramargs=setenv bootargs root=/dev/ram rw" \
Detlev Zundele5084af2008-02-22 17:21:32 +0100342 " ramdisk_size=${ramdisk_size}\0" \
Stefan Roese779e9752007-08-14 14:44:41 +0200343 "addip=setenv bootargs ${bootargs} " \
344 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
345 ":${hostname}:${netdev}:off panic=1\0" \
346 "addtty=setenv bootargs ${bootargs} console=ttyS0," \
347 "${baudrate}\0" \
348 "net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \
349 "run nfsargs addip addtty;bootm\0" \
350 "net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \
351 "tftp ${ramdisk_mem_addr} ${file_fs};" \
352 "run ramargs addip addtty;" \
353 "bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \
354 "rootpath=/target_fs/zeus\0" \
355 "kernel_fl_addr=ff000000\0" \
356 "kernel_mem_addr=200000\0" \
357 "ramdisk_fl_addr=ff300000\0" \
358 "ramdisk_mem_addr=4000000\0" \
359 "uboot_fl_addr=fffc0000\0" \
360 "uboot_mem_addr=100000\0" \
361 "file_uboot=/zeus/u-boot.bin\0" \
362 "tftp_uboot=tftp 100000 ${file_uboot}\0" \
363 "update_uboot=protect off fffc0000 ffffffff;" \
364 "era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \
365 "protect on fffc0000 ffffffff\0" \
366 "upd_uboot=run tftp_uboot;run update_uboot\0" \
367 "file_kernel=/zeus/uImage_ba\0" \
368 "tftp_kernel=tftp 100000 ${file_kernel}\0" \
369 "update_kernel=protect off ff000000 ff17ffff;" \
370 "era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \
371 "upd_kernel=run tftp_kernel;run update_kernel\0" \
372 "file_fs=/zeus/rootfs_ba.img\0" \
373 "tftp_fs=tftp 100000 ${file_fs}\0" \
374 "update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
375 "cp.b 100000 ff300000 580000\0" \
376 "upd_fs=run tftp_fs;run update_fs\0" \
377 "bootcmd=chkreset;run ramargs addip addtty addmisc;" \
378 "bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \
379 ""
380
381#endif /* __CONFIG_H */