blob: 84f8b8db2b4b056540e520788c98749a0a857f32 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chin Liang Seec5c1af22013-12-30 18:26:14 -06002/*
3 * (C) Copyright 2013 Altera Corporation <www.altera.com>
Chin Liang Seec5c1af22013-12-30 18:26:14 -06004 */
5
6#include <common.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06007#include <log.h>
Marek Vasutc35ed772015-11-30 20:41:04 +01008#include <asm/arch/clock_manager.h>
Marek Vasutc35ed772015-11-30 20:41:04 +01009#include <asm/arch/system_manager.h>
Marek Vasut12ea13a2018-08-01 18:28:35 +020010#include <clk.h>
Marek Vasutc35ed772015-11-30 20:41:04 +010011#include <dm.h>
Chin Liang Seec5c1af22013-12-30 18:26:14 -060012#include <dwmmc.h>
Pavel Machek498d1a62014-09-08 14:08:45 +020013#include <errno.h>
Marek Vasutc35ed772015-11-30 20:41:04 +010014#include <fdtdec.h>
Simon Glass336d4612020-02-03 07:36:16 -070015#include <dm/device_compat.h>
Masahiro Yamadab08c8c42018-03-05 01:20:11 +090016#include <linux/libfdt.h>
Marek Vasutc35ed772015-11-30 20:41:04 +010017#include <linux/err.h>
18#include <malloc.h>
Ley Foon Tan2d4d6932018-06-14 18:45:21 +080019#include <reset.h>
Marek Vasutc35ed772015-11-30 20:41:04 +010020
21DECLARE_GLOBAL_DATA_PTR;
Chin Liang Seec5c1af22013-12-30 18:26:14 -060022
Simon Glassf1a485a2016-07-05 17:10:16 -060023struct socfpga_dwmci_plat {
24 struct mmc_config cfg;
25 struct mmc mmc;
26};
27
Marek Vasutc35ed772015-11-30 20:41:04 +010028/* socfpga implmentation specific driver private data */
Chin Liang See9a414042015-11-26 09:43:43 +080029struct dwmci_socfpga_priv_data {
Marek Vasutc35ed772015-11-30 20:41:04 +010030 struct dwmci_host host;
31 unsigned int drvsel;
32 unsigned int smplsel;
Chin Liang See9a414042015-11-26 09:43:43 +080033};
34
Ley Foon Tan2d4d6932018-06-14 18:45:21 +080035static void socfpga_dwmci_reset(struct udevice *dev)
36{
37 struct reset_ctl_bulk reset_bulk;
38 int ret;
39
40 ret = reset_get_bulk(dev, &reset_bulk);
41 if (ret) {
42 dev_warn(dev, "Can't get reset: %d\n", ret);
43 return;
44 }
45
46 reset_deassert_bulk(&reset_bulk);
47}
48
Chin Liang See9a414042015-11-26 09:43:43 +080049static void socfpga_dwmci_clksel(struct dwmci_host *host)
50{
51 struct dwmci_socfpga_priv_data *priv = host->priv;
Dinh Nguyena1684b62015-12-02 13:31:33 -060052 u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
53 ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
Chin Liang Seec5c1af22013-12-30 18:26:14 -060054
55 /* Disable SDMMC clock. */
Ley Foon Tan94172c72019-11-08 10:38:21 +080056 clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
57 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
Chin Liang Seec5c1af22013-12-30 18:26:14 -060058
Chin Liang See9a414042015-11-26 09:43:43 +080059 debug("%s: drvsel %d smplsel %d\n", __func__,
60 priv->drvsel, priv->smplsel);
Ley Foon Tandb5741f2019-11-08 10:38:20 +080061 writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
Chin Liang Seec5c1af22013-12-30 18:26:14 -060062
63 debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
Ley Foon Tandb5741f2019-11-08 10:38:20 +080064 readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
Chin Liang Seec5c1af22013-12-30 18:26:14 -060065
66 /* Enable SDMMC clock */
Ley Foon Tan94172c72019-11-08 10:38:21 +080067 setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
68 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
Chin Liang Seec5c1af22013-12-30 18:26:14 -060069}
70
Marek Vasut12ea13a2018-08-01 18:28:35 +020071static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
Chin Liang Seec5c1af22013-12-30 18:26:14 -060072{
Marek Vasutc35ed772015-11-30 20:41:04 +010073 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
74 struct dwmci_host *host = &priv->host;
Marek Vasut12ea13a2018-08-01 18:28:35 +020075#if CONFIG_IS_ENABLED(CLK)
76 struct clk clk;
77 int ret;
Pavel Machek498d1a62014-09-08 14:08:45 +020078
Marek Vasut12ea13a2018-08-01 18:28:35 +020079 ret = clk_get_by_index(dev, 1, &clk);
80 if (ret)
81 return ret;
82
83 host->bus_hz = clk_get_rate(&clk);
84
85 clk_free(&clk);
86#else
87 /* Fixed clock divide by 4 which due to the SDMMC wrapper */
88 host->bus_hz = cm_get_mmc_controller_clk_hz();
89#endif
90 if (host->bus_hz == 0) {
Marek Vasutc35ed772015-11-30 20:41:04 +010091 printf("DWMMC: MMC clock is zero!");
Pavel Machek498d1a62014-09-08 14:08:45 +020092 return -EINVAL;
93 }
Pavel Machek78606492014-07-21 13:30:19 +020094
Marek Vasut12ea13a2018-08-01 18:28:35 +020095 return 0;
96}
97
98static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
99{
100 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
101 struct dwmci_host *host = &priv->host;
102 int fifo_depth;
103
Simon Glasse160f7d2017-01-17 16:52:55 -0700104 fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
Marek Vasutc35ed772015-11-30 20:41:04 +0100105 "fifo-depth", 0);
Marek Vasut129adf52015-07-25 10:48:14 +0200106 if (fifo_depth < 0) {
Marek Vasutc35ed772015-11-30 20:41:04 +0100107 printf("DWMMC: Can't get FIFO depth\n");
Marek Vasut129adf52015-07-25 10:48:14 +0200108 return -EINVAL;
109 }
110
Marek Vasutc35ed772015-11-30 20:41:04 +0100111 host->name = dev->name;
Masahiro Yamada8613c8d2020-07-17 14:36:46 +0900112 host->ioaddr = dev_read_addr_ptr(dev);
Simon Glasse160f7d2017-01-17 16:52:55 -0700113 host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
Marek Vasutc35ed772015-11-30 20:41:04 +0100114 "bus-width", 4);
Chin Liang Seec5c1af22013-12-30 18:26:14 -0600115 host->clksel = socfpga_dwmci_clksel;
Marek Vasutc35ed772015-11-30 20:41:04 +0100116
117 /*
118 * TODO(sjg@chromium.org): Remove the need for this hack.
119 * We only have one dwmmc block on gen5 SoCFPGA.
120 */
121 host->dev_index = 0;
Chin Liang Seec5c1af22013-12-30 18:26:14 -0600122 host->fifoth_val = MSIZE(0x2) |
Marek Vasut129adf52015-07-25 10:48:14 +0200123 RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
Simon Glasse160f7d2017-01-17 16:52:55 -0700124 priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
Marek Vasutc35ed772015-11-30 20:41:04 +0100125 "drvsel", 3);
Simon Glasse160f7d2017-01-17 16:52:55 -0700126 priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
Marek Vasutc35ed772015-11-30 20:41:04 +0100127 "smplsel", 0);
Chin Liang See9a414042015-11-26 09:43:43 +0800128 host->priv = priv;
Chin Liang Seec5c1af22013-12-30 18:26:14 -0600129
Marek Vasut129adf52015-07-25 10:48:14 +0200130 return 0;
131}
132
Marek Vasutc35ed772015-11-30 20:41:04 +0100133static int socfpga_dwmmc_probe(struct udevice *dev)
Marek Vasut129adf52015-07-25 10:48:14 +0200134{
Simon Glassf1a485a2016-07-05 17:10:16 -0600135#ifdef CONFIG_BLK
Simon Glassc69cda22020-12-03 16:55:20 -0700136 struct socfpga_dwmci_plat *plat = dev_get_plat(dev);
Simon Glassf1a485a2016-07-05 17:10:16 -0600137#endif
Marek Vasutc35ed772015-11-30 20:41:04 +0100138 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
139 struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
140 struct dwmci_host *host = &priv->host;
Marek Vasut12ea13a2018-08-01 18:28:35 +0200141 int ret;
142
143 ret = socfpga_dwmmc_get_clk_rate(dev);
144 if (ret)
145 return ret;
Simon Glassf1a485a2016-07-05 17:10:16 -0600146
Ley Foon Tan2d4d6932018-06-14 18:45:21 +0800147 socfpga_dwmci_reset(dev);
148
Simon Glassf1a485a2016-07-05 17:10:16 -0600149#ifdef CONFIG_BLK
Jaehoon Chunge5113c32016-09-23 19:13:16 +0900150 dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
Simon Glassf1a485a2016-07-05 17:10:16 -0600151 host->mmc = &plat->mmc;
152#else
Marek Vasut129adf52015-07-25 10:48:14 +0200153
Marek Vasutc35ed772015-11-30 20:41:04 +0100154 ret = add_dwmci(host, host->bus_hz, 400000);
155 if (ret)
156 return ret;
Simon Glassf1a485a2016-07-05 17:10:16 -0600157#endif
158 host->mmc->priv = &priv->host;
Marek Vasutc35ed772015-11-30 20:41:04 +0100159 upriv->mmc = host->mmc;
Simon Glasscffe5d82016-05-01 13:52:34 -0600160 host->mmc->dev = dev;
Marek Vasut129adf52015-07-25 10:48:14 +0200161
Patrick Bruenn55118ec2018-03-06 09:07:23 +0100162 return dwmci_probe(dev);
Marek Vasut129adf52015-07-25 10:48:14 +0200163}
Marek Vasutc35ed772015-11-30 20:41:04 +0100164
Simon Glassf1a485a2016-07-05 17:10:16 -0600165static int socfpga_dwmmc_bind(struct udevice *dev)
166{
167#ifdef CONFIG_BLK
Simon Glassc69cda22020-12-03 16:55:20 -0700168 struct socfpga_dwmci_plat *plat = dev_get_plat(dev);
Simon Glassf1a485a2016-07-05 17:10:16 -0600169 int ret;
170
171 ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
172 if (ret)
173 return ret;
174#endif
175
176 return 0;
177}
178
Marek Vasutc35ed772015-11-30 20:41:04 +0100179static const struct udevice_id socfpga_dwmmc_ids[] = {
180 { .compatible = "altr,socfpga-dw-mshc" },
181 { }
182};
183
184U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
185 .name = "socfpga_dwmmc",
186 .id = UCLASS_MMC,
187 .of_match = socfpga_dwmmc_ids,
188 .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
Sylvain Lesnef55ae192016-10-24 18:24:37 +0200189 .ops = &dm_dwmci_ops,
Simon Glassf1a485a2016-07-05 17:10:16 -0600190 .bind = socfpga_dwmmc_bind,
Marek Vasutc35ed772015-11-30 20:41:04 +0100191 .probe = socfpga_dwmmc_probe,
Simon Glass41575d82020-12-03 16:55:17 -0700192 .priv_auto = sizeof(struct dwmci_socfpga_priv_data),
Simon Glasscaa4daa2020-12-03 16:55:18 -0700193 .plat_auto = sizeof(struct socfpga_dwmci_plat),
Marek Vasutc35ed772015-11-30 20:41:04 +0100194};