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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Patrice Chotardeee20f82017-02-21 13:37:09 +01002/*
Patrice Chotardfb48bc42017-10-23 09:53:57 +02003 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
Patrice Chotardeee20f82017-02-21 13:37:09 +01005 */
6
7#include <common.h>
8#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06009#include <log.h>
Patrice Chotardeee20f82017-02-21 13:37:09 +010010#include <mmc.h>
Patrice Chotarddca31662017-09-05 11:04:20 +020011#include <reset-uclass.h>
Patrice Chotardeee20f82017-02-21 13:37:09 +010012#include <sdhci.h>
13#include <asm/arch/sdhci.h>
14
15DECLARE_GLOBAL_DATA_PTR;
16
17struct sti_sdhci_plat {
18 struct mmc_config cfg;
19 struct mmc mmc;
Patrice Chotarddca31662017-09-05 11:04:20 +020020 struct reset_ctl reset;
Patrice Chotard819c6262017-09-05 11:04:18 +020021 int instance;
Patrice Chotardeee20f82017-02-21 13:37:09 +010022};
23
Patrice Chotardeee20f82017-02-21 13:37:09 +010024/**
25 * sti_mmc_core_config: configure the Arasan HC
Patrice Chotard819c6262017-09-05 11:04:18 +020026 * @dev : udevice
27 *
Patrice Chotardeee20f82017-02-21 13:37:09 +010028 * Description: this function is to configure the Arasan MMC HC.
29 * This should be called when the system starts in case of, on the SoC,
30 * it is needed to configure the host controller.
31 * This happens on some SoCs, i.e. StiH410, where the MMC0 inside the flashSS
32 * needs to be configured as MMC 4.5 to have full capabilities.
33 * W/o these settings the SDHCI could configure and use the embedded controller
34 * with limited features.
35 */
Patrice Chotarddca31662017-09-05 11:04:20 +020036static int sti_mmc_core_config(struct udevice *dev)
Patrice Chotardeee20f82017-02-21 13:37:09 +010037{
Simon Glassc69cda22020-12-03 16:55:20 -070038 struct sti_sdhci_plat *plat = dev_get_plat(dev);
Patrice Chotard819c6262017-09-05 11:04:18 +020039 struct sdhci_host *host = dev_get_priv(dev);
Patrice Chotarddca31662017-09-05 11:04:20 +020040 int ret;
Patrice Chotardeee20f82017-02-21 13:37:09 +010041
42 /* only MMC1 has a reset line */
Patrice Chotard819c6262017-09-05 11:04:18 +020043 if (plat->instance) {
Patrice Chotarddca31662017-09-05 11:04:20 +020044 ret = reset_deassert(&plat->reset);
45 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +090046 pr_err("MMC1 deassert failed: %d", ret);
Patrice Chotarddca31662017-09-05 11:04:20 +020047 return ret;
48 }
Patrice Chotardeee20f82017-02-21 13:37:09 +010049 }
50
51 writel(STI_FLASHSS_MMC_CORE_CONFIG_1,
Patrice Chotard819c6262017-09-05 11:04:18 +020052 host->ioaddr + FLASHSS_MMC_CORE_CONFIG_1);
Patrice Chotardeee20f82017-02-21 13:37:09 +010053
Patrice Chotard819c6262017-09-05 11:04:18 +020054 if (plat->instance) {
Patrice Chotardeee20f82017-02-21 13:37:09 +010055 writel(STI_FLASHSS_MMC_CORE_CONFIG2,
Patrice Chotard819c6262017-09-05 11:04:18 +020056 host->ioaddr + FLASHSS_MMC_CORE_CONFIG_2);
Patrice Chotardeee20f82017-02-21 13:37:09 +010057 writel(STI_FLASHSS_MMC_CORE_CONFIG3,
Patrice Chotard819c6262017-09-05 11:04:18 +020058 host->ioaddr + FLASHSS_MMC_CORE_CONFIG_3);
Patrice Chotardeee20f82017-02-21 13:37:09 +010059 } else {
60 writel(STI_FLASHSS_SDCARD_CORE_CONFIG2,
Patrice Chotard819c6262017-09-05 11:04:18 +020061 host->ioaddr + FLASHSS_MMC_CORE_CONFIG_2);
Patrice Chotardeee20f82017-02-21 13:37:09 +010062 writel(STI_FLASHSS_SDCARD_CORE_CONFIG3,
Patrice Chotard819c6262017-09-05 11:04:18 +020063 host->ioaddr + FLASHSS_MMC_CORE_CONFIG_3);
Patrice Chotardeee20f82017-02-21 13:37:09 +010064 }
65 writel(STI_FLASHSS_MMC_CORE_CONFIG4,
Patrice Chotard819c6262017-09-05 11:04:18 +020066 host->ioaddr + FLASHSS_MMC_CORE_CONFIG_4);
Patrice Chotarddca31662017-09-05 11:04:20 +020067
68 return 0;
Patrice Chotardeee20f82017-02-21 13:37:09 +010069}
70
71static int sti_sdhci_probe(struct udevice *dev)
72{
73 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
Simon Glassc69cda22020-12-03 16:55:20 -070074 struct sti_sdhci_plat *plat = dev_get_plat(dev);
Patrice Chotardeee20f82017-02-21 13:37:09 +010075 struct sdhci_host *host = dev_get_priv(dev);
Patrice Chotard819c6262017-09-05 11:04:18 +020076 int ret;
Patrice Chotardeee20f82017-02-21 13:37:09 +010077
78 /*
79 * identify current mmc instance, mmc1 has a reset, not mmc0
80 * MMC0 is wired to the SD slot,
81 * MMC1 is wired on the high speed connector
82 */
Patrice Chotarddca31662017-09-05 11:04:20 +020083 ret = reset_get_by_index(dev, 0, &plat->reset);
84 if (!ret)
Patrice Chotard819c6262017-09-05 11:04:18 +020085 plat->instance = 1;
Patrice Chotardeee20f82017-02-21 13:37:09 +010086 else
Patrice Chotarddca31662017-09-05 11:04:20 +020087 if (ret == -ENOENT)
88 plat->instance = 0;
89 else
90 return ret;
Patrice Chotardeee20f82017-02-21 13:37:09 +010091
Patrice Chotarddca31662017-09-05 11:04:20 +020092 ret = sti_mmc_core_config(dev);
93 if (ret)
94 return ret;
Patrice Chotardeee20f82017-02-21 13:37:09 +010095
96 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
97 SDHCI_QUIRK_32BIT_DMA_ADDR |
98 SDHCI_QUIRK_NO_HISPD_BIT;
99
100 host->host_caps = MMC_MODE_DDR_52MHz;
Patrice Chotard2e01fcf2019-07-24 09:51:02 +0200101 host->mmc = &plat->mmc;
102 host->mmc->dev = dev;
103 host->mmc->priv = host;
Patrice Chotardeee20f82017-02-21 13:37:09 +0100104
105 ret = sdhci_setup_cfg(&plat->cfg, host, 50000000, 400000);
106 if (ret)
107 return ret;
108
Patrice Chotardeee20f82017-02-21 13:37:09 +0100109 upriv->mmc = host->mmc;
110
111 return sdhci_probe(dev);
112}
113
Simon Glassd1998a92020-12-03 16:55:21 -0700114static int sti_sdhci_of_to_plat(struct udevice *dev)
Patrice Chotardeee20f82017-02-21 13:37:09 +0100115{
116 struct sdhci_host *host = dev_get_priv(dev);
117
118 host->name = strdup(dev->name);
Masahiro Yamada8613c8d2020-07-17 14:36:46 +0900119 host->ioaddr = dev_read_addr_ptr(dev);
Patrice Chotardeee20f82017-02-21 13:37:09 +0100120
121 host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
122 "bus-width", 4);
123
124 return 0;
125}
126
127static int sti_sdhci_bind(struct udevice *dev)
128{
Simon Glassc69cda22020-12-03 16:55:20 -0700129 struct sti_sdhci_plat *plat = dev_get_plat(dev);
Patrice Chotardeee20f82017-02-21 13:37:09 +0100130
131 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
132}
133
134static const struct udevice_id sti_sdhci_ids[] = {
135 { .compatible = "st,sdhci" },
136 { }
137};
138
139U_BOOT_DRIVER(sti_mmc) = {
140 .name = "sti_sdhci",
141 .id = UCLASS_MMC,
142 .of_match = sti_sdhci_ids,
143 .bind = sti_sdhci_bind,
144 .ops = &sdhci_ops,
Simon Glassd1998a92020-12-03 16:55:21 -0700145 .of_to_plat = sti_sdhci_of_to_plat,
Patrice Chotardeee20f82017-02-21 13:37:09 +0100146 .probe = sti_sdhci_probe,
Simon Glass41575d82020-12-03 16:55:17 -0700147 .priv_auto = sizeof(struct sdhci_host),
Simon Glasscaa4daa2020-12-03 16:55:18 -0700148 .plat_auto = sizeof(struct sti_sdhci_plat),
Patrice Chotardeee20f82017-02-21 13:37:09 +0100149};