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Mike Frysingerbe853bf2008-10-06 04:16:47 -04001/*
2 * i2c.c - driver for Blackfin on-chip TWI/I2C
3 *
Mike Frysingerb5cebb42010-05-05 03:20:30 -04004 * Copyright (c) 2006-2010 Analog Devices Inc.
Mike Frysingerbe853bf2008-10-06 04:16:47 -04005 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <common.h>
10#include <i2c.h>
11
12#include <asm/blackfin.h>
Sonic Zhangd6a320d2014-01-28 13:53:34 +080013#include <asm/clock.h>
Mike Frysingerbe853bf2008-10-06 04:16:47 -040014#include <asm/mach-common/bits/twi.h>
15
Mike Frysingerb5cebb42010-05-05 03:20:30 -040016/* Every register is 32bit aligned, but only 16bits in size */
17#define ureg(name) u16 name; u16 __pad_##name;
18struct twi_regs {
19 ureg(clkdiv);
20 ureg(control);
21 ureg(slave_ctl);
22 ureg(slave_stat);
23 ureg(slave_addr);
24 ureg(master_ctl);
25 ureg(master_stat);
26 ureg(master_addr);
27 ureg(int_stat);
28 ureg(int_mask);
29 ureg(fifo_ctl);
30 ureg(fifo_stat);
31 char __pad[0x50];
32 ureg(xmt_data8);
33 ureg(xmt_data16);
34 ureg(rcv_data8);
35 ureg(rcv_data16);
36};
37#undef ureg
38
39/* U-Boot I2C framework allows only one active device at a time. */
40#ifdef TWI_CLKDIV
41#define TWI0_CLKDIV TWI_CLKDIV
42#endif
43static volatile struct twi_regs *twi = (void *)TWI0_CLKDIV;
44
Mike Frysingerbe853bf2008-10-06 04:16:47 -040045#ifdef DEBUG
46# define dmemset(s, c, n) memset(s, c, n)
47#else
48# define dmemset(s, c, n)
49#endif
50#define debugi(fmt, args...) \
51 debug( \
Mike Frysingerb5cebb42010-05-05 03:20:30 -040052 "MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t%-20s:%-3i: " fmt "\n", \
53 twi->master_stat, twi->fifo_stat, twi->int_stat, \
Mike Frysingerbe853bf2008-10-06 04:16:47 -040054 __func__, __LINE__, ## args)
55
Mike Frysingerbe853bf2008-10-06 04:16:47 -040056#ifdef CONFIG_TWICLK_KHZ
57# error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED
58#endif
Mike Frysinger08a1c622009-10-14 19:27:27 -040059
60/*
61 * The way speed is changed into duty often results in integer truncation
62 * with 50% duty, so we'll force rounding up to the next duty by adding 1
63 * to the max. In practice this will get us a speed of something like
64 * 385 KHz. The other limit is easy to handle as it is only 8 bits.
65 */
66#define I2C_SPEED_MAX 400000
67#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed))
68#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
69#define I2C_DUTY_MIN 0xff /* 8 bit limited */
70#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
71/* Note: duty is inverse of speed, so the comparisons below are correct */
72#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN
73# error "The Blackfin I2C hardware can only operate 20KHz - 400KHz"
Mike Frysingerbe853bf2008-10-06 04:16:47 -040074#endif
75
76/* All transfers are described by this data structure */
77struct i2c_msg {
78 u8 flags;
79#define I2C_M_COMBO 0x4
80#define I2C_M_STOP 0x2
81#define I2C_M_READ 0x1
82 int len; /* msg length */
83 u8 *buf; /* pointer to msg data */
84 int alen; /* addr length */
85 u8 *abuf; /* addr buffer */
86};
87
Mike Frysinger3814ea42009-10-14 19:27:26 -040088/* Allow msec timeout per ~byte transfer */
89#define I2C_TIMEOUT 10
90
Mike Frysingerbe853bf2008-10-06 04:16:47 -040091/**
92 * wait_for_completion - manage the actual i2c transfer
93 * @msg: the i2c msg
94 */
95static int wait_for_completion(struct i2c_msg *msg)
96{
97 uint16_t int_stat;
Mike Frysinger3814ea42009-10-14 19:27:26 -040098 ulong timebase = get_timer(0);
Mike Frysingerbe853bf2008-10-06 04:16:47 -040099
Mike Frysinger3814ea42009-10-14 19:27:26 -0400100 do {
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400101 int_stat = twi->int_stat;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400102
103 if (int_stat & XMTSERV) {
104 debugi("processing XMTSERV");
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400105 twi->int_stat = XMTSERV;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400106 SSYNC();
107 if (msg->alen) {
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400108 twi->xmt_data8 = *(msg->abuf++);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400109 --msg->alen;
110 } else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400111 twi->xmt_data8 = *(msg->buf++);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400112 --msg->len;
113 } else {
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400114 twi->master_ctl |= (msg->flags & I2C_M_COMBO) ? RSTART | MDIR : STOP;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400115 SSYNC();
116 }
117 }
118 if (int_stat & RCVSERV) {
119 debugi("processing RCVSERV");
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400120 twi->int_stat = RCVSERV;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400121 SSYNC();
122 if (msg->len) {
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400123 *(msg->buf++) = twi->rcv_data8;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400124 --msg->len;
125 } else if (msg->flags & I2C_M_STOP) {
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400126 twi->master_ctl |= STOP;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400127 SSYNC();
128 }
129 }
130 if (int_stat & MERR) {
131 debugi("processing MERR");
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400132 twi->int_stat = MERR;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400133 SSYNC();
Mike Frysinger3814ea42009-10-14 19:27:26 -0400134 return msg->len;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400135 }
136 if (int_stat & MCOMP) {
137 debugi("processing MCOMP");
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400138 twi->int_stat = MCOMP;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400139 SSYNC();
140 if (msg->flags & I2C_M_COMBO && msg->len) {
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400141 twi->master_ctl = (twi->master_ctl & ~RSTART) |
142 (min(msg->len, 0xff) << 6) | MEN | MDIR;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400143 SSYNC();
144 } else
145 break;
146 }
Mike Frysinger3814ea42009-10-14 19:27:26 -0400147
148 /* If we were able to do something, reset timeout */
149 if (int_stat)
150 timebase = get_timer(0);
151
152 } while (get_timer(timebase) < I2C_TIMEOUT);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400153
154 return msg->len;
155}
156
157/**
158 * i2c_transfer - setup an i2c transfer
159 * @return: 0 if things worked, non-0 if things failed
160 *
161 * Here we just get the i2c stuff all prepped and ready, and then tail off
162 * into wait_for_completion() for all the bits to go.
163 */
164static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, u8 flags)
165{
166 uchar addr_buffer[] = {
167 (addr >> 0),
168 (addr >> 8),
169 (addr >> 16),
170 };
171 struct i2c_msg msg = {
172 .flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
173 .buf = buffer,
174 .len = len,
175 .abuf = addr_buffer,
176 .alen = alen,
177 };
178 int ret;
179
180 dmemset(buffer, 0xff, len);
181 debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i flags=0x%02x[%s] ",
182 chip, addr, alen, buffer[0], len, flags, (flags & I2C_M_READ ? "rd" : "wr"));
183
184 /* wait for things to settle */
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400185 while (twi->master_stat & BUSBUSY)
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400186 if (ctrlc())
187 return 1;
188
189 /* Set Transmit device address */
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400190 twi->master_addr = chip;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400191
192 /* Clear the FIFO before starting things */
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400193 twi->fifo_ctl = XMTFLUSH | RCVFLUSH;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400194 SSYNC();
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400195 twi->fifo_ctl = 0;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400196 SSYNC();
197
198 /* prime the pump */
199 if (msg.alen) {
Peter Meerwald98ab14e2009-06-29 15:48:33 -0400200 len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400201 debugi("first byte=0x%02x", *msg.abuf);
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400202 twi->xmt_data8 = *(msg.abuf++);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400203 --msg.alen;
204 } else if (!(msg.flags & I2C_M_READ) && msg.len) {
205 debugi("first byte=0x%02x", *msg.buf);
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400206 twi->xmt_data8 = *(msg.buf++);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400207 --msg.len;
208 }
209
210 /* clear int stat */
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400211 twi->master_stat = -1;
212 twi->int_stat = -1;
213 twi->int_mask = 0;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400214 SSYNC();
215
216 /* Master enable */
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400217 twi->master_ctl =
218 (twi->master_ctl & FAST) |
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400219 (min(len, 0xff) << 6) | MEN |
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400220 ((msg.flags & I2C_M_READ) ? MDIR : 0);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400221 SSYNC();
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400222 debugi("CTL=0x%04x", twi->master_ctl);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400223
224 /* process the rest */
225 ret = wait_for_completion(&msg);
226 debugi("ret=%d", ret);
227
228 if (ret) {
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400229 twi->master_ctl &= ~MEN;
230 twi->control &= ~TWI_ENA;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400231 SSYNC();
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400232 twi->control |= TWI_ENA;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400233 SSYNC();
234 }
235
236 return ret;
237}
238
Mike Frysinger08a1c622009-10-14 19:27:27 -0400239/**
240 * i2c_set_bus_speed - set i2c bus speed
241 * @speed: bus speed (in HZ)
242 */
243int i2c_set_bus_speed(unsigned int speed)
244{
245 u16 clkdiv = I2C_SPEED_TO_DUTY(speed);
246
247 /* Set TWI interface clock */
248 if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN)
249 return -1;
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400250 twi->clkdiv = (clkdiv << 8) | (clkdiv & 0xff);
Mike Frysinger08a1c622009-10-14 19:27:27 -0400251
252 /* Don't turn it on */
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400253 twi->master_ctl = (speed > 100000 ? FAST : 0);
Mike Frysinger08a1c622009-10-14 19:27:27 -0400254
255 return 0;
256}
257
258/**
259 * i2c_get_bus_speed - get i2c bus speed
260 * @speed: bus speed (in HZ)
261 */
262unsigned int i2c_get_bus_speed(void)
263{
264 /* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400265 return 5000000 / (twi->clkdiv & 0xff);
Mike Frysinger08a1c622009-10-14 19:27:27 -0400266}
267
268/**
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400269 * i2c_init - initialize the i2c bus
270 * @speed: bus speed (in HZ)
271 * @slaveaddr: address of device in slave mode (0 - not slave)
272 *
273 * Slave mode isn't actually implemented. It'll stay that way until
274 * we get a real request for it.
275 */
276void i2c_init(int speed, int slaveaddr)
277{
Sonic Zhangd6a320d2014-01-28 13:53:34 +0800278 uint8_t prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400279
280 /* Set TWI internal clock as 10MHz */
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400281 twi->control = prescale;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400282
283 /* Set TWI interface clock as specified */
Mike Frysinger08a1c622009-10-14 19:27:27 -0400284 i2c_set_bus_speed(speed);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400285
Mike Frysinger08a1c622009-10-14 19:27:27 -0400286 /* Enable it */
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400287 twi->control = TWI_ENA | prescale;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400288 SSYNC();
289
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400290 debugi("CONTROL:0x%04x CLKDIV:0x%04x", twi->control, twi->clkdiv);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400291
292#if CONFIG_SYS_I2C_SLAVE
293# error I2C slave support not tested/supported
294 /* If they want us as a slave, do it */
295 if (slaveaddr) {
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400296 twi->slave_addr = slaveaddr;
297 twi->slave_ctl = SEN;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400298 }
299#endif
300}
301
302/**
303 * i2c_probe - test if a chip exists at a given i2c address
304 * @chip: i2c chip addr to search for
305 * @return: 0 if found, non-0 if not found
306 */
307int i2c_probe(uchar chip)
308{
309 u8 byte;
310 return i2c_read(chip, 0, 0, &byte, 1);
311}
312
313/**
314 * i2c_read - read data from an i2c device
315 * @chip: i2c chip addr
316 * @addr: memory (register) address in the chip
317 * @alen: byte size of address
318 * @buffer: buffer to store data read from chip
319 * @len: how many bytes to read
320 * @return: 0 on success, non-0 on failure
321 */
322int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
323{
324 return i2c_transfer(chip, addr, alen, buffer, len, (alen ? I2C_M_COMBO : I2C_M_READ));
325}
326
327/**
328 * i2c_write - write data to an i2c device
329 * @chip: i2c chip addr
330 * @addr: memory (register) address in the chip
331 * @alen: byte size of address
Peter Meerwald98ab14e2009-06-29 15:48:33 -0400332 * @buffer: buffer holding data to write to chip
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400333 * @len: how many bytes to write
334 * @return: 0 on success, non-0 on failure
335 */
336int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
337{
338 return i2c_transfer(chip, addr, alen, buffer, len, 0);
339}
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400340
341/**
342 * i2c_set_bus_num - change active I2C bus
343 * @bus: bus index, zero based
344 * @returns: 0 on success, non-0 on failure
345 */
346int i2c_set_bus_num(unsigned int bus)
347{
348 switch (bus) {
349#if CONFIG_SYS_MAX_I2C_BUS > 0
350 case 0: twi = (void *)TWI0_CLKDIV; return 0;
351#endif
352#if CONFIG_SYS_MAX_I2C_BUS > 1
353 case 1: twi = (void *)TWI1_CLKDIV; return 0;
354#endif
355#if CONFIG_SYS_MAX_I2C_BUS > 2
356 case 2: twi = (void *)TWI2_CLKDIV; return 0;
357#endif
358 default: return -1;
359 }
360}
361
362/**
363 * i2c_get_bus_num - returns index of active I2C bus
364 */
365unsigned int i2c_get_bus_num(void)
366{
367 switch ((unsigned long)twi) {
368#if CONFIG_SYS_MAX_I2C_BUS > 0
369 case TWI0_CLKDIV: return 0;
370#endif
371#if CONFIG_SYS_MAX_I2C_BUS > 1
372 case TWI1_CLKDIV: return 1;
373#endif
374#if CONFIG_SYS_MAX_I2C_BUS > 2
375 case TWI2_CLKDIV: return 2;
376#endif
377 default: return -1;
378 }
379}