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Dinh Nguyen3da42852015-06-02 22:52:49 -05001/*
2 * Copyright Altera Corporation (C) 2012-2015
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common.h>
8#include <asm/io.h>
9#include <asm/arch/sdram.h>
10#include "sequencer.h"
11#include "sequencer_auto.h"
12#include "sequencer_auto_ac_init.h"
13#include "sequencer_auto_inst_init.h"
14#include "sequencer_defines.h"
15
Dinh Nguyen3da42852015-06-02 22:52:49 -050016static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
Marek Vasut6afb4fe2015-07-12 18:46:52 +020017 (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
Dinh Nguyen3da42852015-06-02 22:52:49 -050018
19static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
Marek Vasut6afb4fe2015-07-12 18:46:52 +020020 (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
Dinh Nguyen3da42852015-06-02 22:52:49 -050021
22static struct socfpga_sdr_reg_file *sdr_reg_file =
Marek Vasuta1c654a2015-07-12 18:31:05 +020023 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
Dinh Nguyen3da42852015-06-02 22:52:49 -050024
25static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
Marek Vasute79025a2015-07-12 18:42:34 +020026 (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
Dinh Nguyen3da42852015-06-02 22:52:49 -050027
28static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
Marek Vasut1bc6f142015-07-12 18:54:37 +020029 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
Dinh Nguyen3da42852015-06-02 22:52:49 -050030
31static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
Marek Vasut1bc6f142015-07-12 18:54:37 +020032 (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
Dinh Nguyen3da42852015-06-02 22:52:49 -050033
34static struct socfpga_data_mgr *data_mgr =
Marek Vasutc4815f72015-07-12 19:03:33 +020035 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
Dinh Nguyen3da42852015-06-02 22:52:49 -050036
Marek Vasut6cb9f162015-07-12 20:49:39 +020037static struct socfpga_sdr_ctrl *sdr_ctrl =
38 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
39
Dinh Nguyen3da42852015-06-02 22:52:49 -050040#define DELTA_D 1
Dinh Nguyen3da42852015-06-02 22:52:49 -050041
42/*
43 * In order to reduce ROM size, most of the selectable calibration steps are
44 * decided at compile time based on the user's calibration mode selection,
45 * as captured by the STATIC_CALIB_STEPS selection below.
46 *
47 * However, to support simulation-time selection of fast simulation mode, where
48 * we skip everything except the bare minimum, we need a few of the steps to
49 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
50 * check, which is based on the rtl-supplied value, or we dynamically compute
51 * the value to use based on the dynamically-chosen calibration mode
52 */
53
54#define DLEVEL 0
55#define STATIC_IN_RTL_SIM 0
56#define STATIC_SKIP_DELAY_LOOPS 0
57
58#define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
59 STATIC_SKIP_DELAY_LOOPS)
60
61/* calibration steps requested by the rtl */
62uint16_t dyn_calib_steps;
63
64/*
65 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
66 * instead of static, we use boolean logic to select between
67 * non-skip and skip values
68 *
69 * The mask is set to include all bits when not-skipping, but is
70 * zero when skipping
71 */
72
73uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
74
75#define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
76 ((non_skip_value) & skip_delay_mask)
77
78struct gbl_type *gbl;
79struct param_type *param;
80uint32_t curr_shadow_reg;
81
82static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
83 uint32_t write_group, uint32_t use_dm,
84 uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
85
Dinh Nguyen3da42852015-06-02 22:52:49 -050086static void set_failing_group_stage(uint32_t group, uint32_t stage,
87 uint32_t substage)
88{
89 /*
90 * Only set the global stage if there was not been any other
91 * failing group
92 */
93 if (gbl->error_stage == CAL_STAGE_NIL) {
94 gbl->error_substage = substage;
95 gbl->error_stage = stage;
96 gbl->error_group = group;
97 }
98}
99
Marek Vasut2c0d2d92015-07-12 21:10:24 +0200100static void reg_file_set_group(u16 set_group)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500101{
Marek Vasut2c0d2d92015-07-12 21:10:24 +0200102 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500103}
104
Marek Vasut2c0d2d92015-07-12 21:10:24 +0200105static void reg_file_set_stage(u8 set_stage)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500106{
Marek Vasut2c0d2d92015-07-12 21:10:24 +0200107 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500108}
109
Marek Vasut2c0d2d92015-07-12 21:10:24 +0200110static void reg_file_set_sub_stage(u8 set_sub_stage)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500111{
Marek Vasut2c0d2d92015-07-12 21:10:24 +0200112 set_sub_stage &= 0xff;
113 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500114}
115
Marek Vasut7c89c2d2015-07-17 01:36:32 +0200116/**
117 * phy_mgr_initialize() - Initialize PHY Manager
118 *
119 * Initialize PHY Manager.
120 */
Marek Vasut9fa9c902015-07-17 01:12:07 +0200121static void phy_mgr_initialize(void)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500122{
Marek Vasut7c89c2d2015-07-17 01:36:32 +0200123 u32 ratio;
124
Dinh Nguyen3da42852015-06-02 22:52:49 -0500125 debug("%s:%d\n", __func__, __LINE__);
Marek Vasut7c89c2d2015-07-17 01:36:32 +0200126 /* Calibration has control over path to memory */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500127 /*
128 * In Hard PHY this is a 2-bit control:
129 * 0: AFI Mux Select
130 * 1: DDIO Mux Select
131 */
Marek Vasut1273dd92015-07-12 21:05:08 +0200132 writel(0x3, &phy_mgr_cfg->mux_sel);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500133
134 /* USER memory clock is not stable we begin initialization */
Marek Vasut1273dd92015-07-12 21:05:08 +0200135 writel(0, &phy_mgr_cfg->reset_mem_stbl);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500136
137 /* USER calibration status all set to zero */
Marek Vasut1273dd92015-07-12 21:05:08 +0200138 writel(0, &phy_mgr_cfg->cal_status);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500139
Marek Vasut1273dd92015-07-12 21:05:08 +0200140 writel(0, &phy_mgr_cfg->cal_debug_info);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500141
Marek Vasut7c89c2d2015-07-17 01:36:32 +0200142 /* Init params only if we do NOT skip calibration. */
143 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
144 return;
145
146 ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
147 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
148 param->read_correct_mask_vg = (1 << ratio) - 1;
149 param->write_correct_mask_vg = (1 << ratio) - 1;
150 param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
151 param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
152 ratio = RW_MGR_MEM_DATA_WIDTH /
153 RW_MGR_MEM_DATA_MASK_WIDTH;
154 param->dm_correct_mask = (1 << ratio) - 1;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500155}
156
Marek Vasut080bf642015-07-20 08:15:57 +0200157/**
158 * set_rank_and_odt_mask() - Set Rank and ODT mask
159 * @rank: Rank mask
160 * @odt_mode: ODT mode, OFF or READ_WRITE
161 *
162 * Set Rank and ODT mask (On-Die Termination).
163 */
Marek Vasutb2dfd102015-07-20 08:03:11 +0200164static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500165{
Marek Vasutb2dfd102015-07-20 08:03:11 +0200166 u32 odt_mask_0 = 0;
167 u32 odt_mask_1 = 0;
168 u32 cs_and_odt_mask;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500169
Marek Vasutb2dfd102015-07-20 08:03:11 +0200170 if (odt_mode == RW_MGR_ODT_MODE_OFF) {
171 odt_mask_0 = 0x0;
172 odt_mask_1 = 0x0;
173 } else { /* RW_MGR_ODT_MODE_READ_WRITE */
Marek Vasut287cdf62015-07-20 08:09:05 +0200174 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
175 case 1: /* 1 Rank */
176 /* Read: ODT = 0 ; Write: ODT = 1 */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500177 odt_mask_0 = 0x0;
178 odt_mask_1 = 0x1;
Marek Vasut287cdf62015-07-20 08:09:05 +0200179 break;
180 case 2: /* 2 Ranks */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500181 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
Marek Vasut080bf642015-07-20 08:15:57 +0200182 /*
183 * - Dual-Slot , Single-Rank (1 CS per DIMM)
184 * OR
185 * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
186 *
187 * Since MEM_NUMBER_OF_RANKS is 2, they
188 * are both single rank with 2 CS each
189 * (special for RDIMM).
190 *
Dinh Nguyen3da42852015-06-02 22:52:49 -0500191 * Read: Turn on ODT on the opposite rank
192 * Write: Turn on ODT on all ranks
193 */
194 odt_mask_0 = 0x3 & ~(1 << rank);
195 odt_mask_1 = 0x3;
196 } else {
197 /*
Marek Vasut080bf642015-07-20 08:15:57 +0200198 * - Single-Slot , Dual-Rank (2 CS per DIMM)
199 *
200 * Read: Turn on ODT off on all ranks
201 * Write: Turn on ODT on active rank
Dinh Nguyen3da42852015-06-02 22:52:49 -0500202 */
203 odt_mask_0 = 0x0;
204 odt_mask_1 = 0x3 & (1 << rank);
205 }
Marek Vasut287cdf62015-07-20 08:09:05 +0200206 break;
207 case 4: /* 4 Ranks */
208 /* Read:
Dinh Nguyen3da42852015-06-02 22:52:49 -0500209 * ----------+-----------------------+
Dinh Nguyen3da42852015-06-02 22:52:49 -0500210 * | ODT |
211 * Read From +-----------------------+
212 * Rank | 3 | 2 | 1 | 0 |
213 * ----------+-----+-----+-----+-----+
214 * 0 | 0 | 1 | 0 | 0 |
215 * 1 | 1 | 0 | 0 | 0 |
216 * 2 | 0 | 0 | 0 | 1 |
217 * 3 | 0 | 0 | 1 | 0 |
218 * ----------+-----+-----+-----+-----+
219 *
220 * Write:
221 * ----------+-----------------------+
Dinh Nguyen3da42852015-06-02 22:52:49 -0500222 * | ODT |
223 * Write To +-----------------------+
224 * Rank | 3 | 2 | 1 | 0 |
225 * ----------+-----+-----+-----+-----+
226 * 0 | 0 | 1 | 0 | 1 |
227 * 1 | 1 | 0 | 1 | 0 |
228 * 2 | 0 | 1 | 0 | 1 |
229 * 3 | 1 | 0 | 1 | 0 |
230 * ----------+-----+-----+-----+-----+
231 */
232 switch (rank) {
233 case 0:
234 odt_mask_0 = 0x4;
235 odt_mask_1 = 0x5;
236 break;
237 case 1:
238 odt_mask_0 = 0x8;
239 odt_mask_1 = 0xA;
240 break;
241 case 2:
242 odt_mask_0 = 0x1;
243 odt_mask_1 = 0x5;
244 break;
245 case 3:
246 odt_mask_0 = 0x2;
247 odt_mask_1 = 0xA;
248 break;
249 }
Marek Vasut287cdf62015-07-20 08:09:05 +0200250 break;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500251 }
Dinh Nguyen3da42852015-06-02 22:52:49 -0500252 }
253
Marek Vasutb2dfd102015-07-20 08:03:11 +0200254 cs_and_odt_mask = (0xFF & ~(1 << rank)) |
255 ((0xFF & odt_mask_0) << 8) |
256 ((0xFF & odt_mask_1) << 16);
Marek Vasut1273dd92015-07-12 21:05:08 +0200257 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
258 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500259}
260
Marek Vasutc76976d2015-07-12 22:28:33 +0200261/**
262 * scc_mgr_set() - Set SCC Manager register
263 * @off: Base offset in SCC Manager space
264 * @grp: Read/Write group
265 * @val: Value to be set
266 *
267 * This function sets the SCC Manager (Scan Chain Control Manager) register.
268 */
269static void scc_mgr_set(u32 off, u32 grp, u32 val)
270{
271 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
272}
273
Marek Vasute893f4d2015-07-20 07:16:42 +0200274/**
275 * scc_mgr_initialize() - Initialize SCC Manager registers
276 *
277 * Initialize SCC Manager registers.
278 */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500279static void scc_mgr_initialize(void)
280{
Dinh Nguyen3da42852015-06-02 22:52:49 -0500281 /*
Marek Vasute893f4d2015-07-20 07:16:42 +0200282 * Clear register file for HPS. 16 (2^4) is the size of the
283 * full register file in the scc mgr:
284 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
285 * MEM_IF_READ_DQS_WIDTH - 1);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500286 */
Marek Vasutc76976d2015-07-12 22:28:33 +0200287 int i;
Marek Vasute893f4d2015-07-20 07:16:42 +0200288
Dinh Nguyen3da42852015-06-02 22:52:49 -0500289 for (i = 0; i < 16; i++) {
Marek Vasut7ac40d22015-06-26 18:56:54 +0200290 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
Dinh Nguyen3da42852015-06-02 22:52:49 -0500291 __func__, __LINE__, i);
Marek Vasutc76976d2015-07-12 22:28:33 +0200292 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500293 }
294}
295
Marek Vasut5ff825b2015-07-12 22:11:55 +0200296static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
297{
Marek Vasutc76976d2015-07-12 22:28:33 +0200298 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200299}
300
301static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500302{
Marek Vasutc76976d2015-07-12 22:28:33 +0200303 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500304}
305
Dinh Nguyen3da42852015-06-02 22:52:49 -0500306static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
307{
Marek Vasutc76976d2015-07-12 22:28:33 +0200308 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500309}
310
Marek Vasut5ff825b2015-07-12 22:11:55 +0200311static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
312{
Marek Vasutc76976d2015-07-12 22:28:33 +0200313 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200314}
315
Marek Vasut32675242015-07-17 06:07:13 +0200316static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
Marek Vasut5ff825b2015-07-12 22:11:55 +0200317{
Marek Vasutc76976d2015-07-12 22:28:33 +0200318 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
319 delay);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200320}
321
322static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
323{
Marek Vasutc76976d2015-07-12 22:28:33 +0200324 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200325}
326
327static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
328{
Marek Vasutc76976d2015-07-12 22:28:33 +0200329 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200330}
331
Marek Vasut32675242015-07-17 06:07:13 +0200332static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
Marek Vasut5ff825b2015-07-12 22:11:55 +0200333{
Marek Vasutc76976d2015-07-12 22:28:33 +0200334 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
335 delay);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200336}
337
338static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
339{
Marek Vasutc76976d2015-07-12 22:28:33 +0200340 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
341 RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
342 delay);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200343}
344
345/* load up dqs config settings */
346static void scc_mgr_load_dqs(uint32_t dqs)
347{
348 writel(dqs, &sdr_scc_mgr->dqs_ena);
349}
350
351/* load up dqs io config settings */
352static void scc_mgr_load_dqs_io(void)
353{
354 writel(0, &sdr_scc_mgr->dqs_io_ena);
355}
356
357/* load up dq config settings */
358static void scc_mgr_load_dq(uint32_t dq_in_group)
359{
360 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
361}
362
363/* load up dm config settings */
364static void scc_mgr_load_dm(uint32_t dm)
365{
366 writel(dm, &sdr_scc_mgr->dm_ena);
367}
368
Marek Vasut0b69b802015-07-12 23:25:21 +0200369/**
370 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
371 * @off: Base offset in SCC Manager space
372 * @grp: Read/Write group
373 * @val: Value to be set
374 * @update: If non-zero, trigger SCC Manager update for all ranks
375 *
376 * This function sets the SCC Manager (Scan Chain Control Manager) register
377 * and optionally triggers the SCC update for all ranks.
378 */
379static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
380 const int update)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500381{
Marek Vasut0b69b802015-07-12 23:25:21 +0200382 u32 r;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500383
384 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
385 r += NUM_RANKS_PER_SHADOW_REG) {
Marek Vasut0b69b802015-07-12 23:25:21 +0200386 scc_mgr_set(off, grp, val);
Marek Vasut162d60e2015-07-12 23:14:33 +0200387
Marek Vasut0b69b802015-07-12 23:25:21 +0200388 if (update || (r == 0)) {
389 writel(grp, &sdr_scc_mgr->dqs_ena);
Marek Vasut1273dd92015-07-12 21:05:08 +0200390 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500391 }
392 }
393}
394
Marek Vasut0b69b802015-07-12 23:25:21 +0200395static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
396{
397 /*
398 * USER although the h/w doesn't support different phases per
399 * shadow register, for simplicity our scc manager modeling
400 * keeps different phase settings per shadow reg, and it's
401 * important for us to keep them in sync to match h/w.
402 * for efficiency, the scan chain update should occur only
403 * once to sr0.
404 */
405 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
406 read_group, phase, 0);
407}
408
Dinh Nguyen3da42852015-06-02 22:52:49 -0500409static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
410 uint32_t phase)
411{
Marek Vasut0b69b802015-07-12 23:25:21 +0200412 /*
413 * USER although the h/w doesn't support different phases per
414 * shadow register, for simplicity our scc manager modeling
415 * keeps different phase settings per shadow reg, and it's
416 * important for us to keep them in sync to match h/w.
417 * for efficiency, the scan chain update should occur only
418 * once to sr0.
419 */
420 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
421 write_group, phase, 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500422}
423
Dinh Nguyen3da42852015-06-02 22:52:49 -0500424static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
425 uint32_t delay)
426{
Dinh Nguyen3da42852015-06-02 22:52:49 -0500427 /*
428 * In shadow register mode, the T11 settings are stored in
429 * registers in the core, which are updated by the DQS_ENA
430 * signals. Not issuing the SCC_MGR_UPD command allows us to
431 * save lots of rank switching overhead, by calling
432 * select_shadow_regs_for_update with update_scan_chains
433 * set to 0.
434 */
Marek Vasut0b69b802015-07-12 23:25:21 +0200435 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
436 read_group, delay, 1);
Marek Vasut1273dd92015-07-12 21:05:08 +0200437 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500438}
439
Marek Vasut5be355c2015-07-12 23:39:06 +0200440/**
441 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
442 * @write_group: Write group
443 * @delay: Delay value
444 *
445 * This function sets the OCT output delay in SCC manager.
446 */
447static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500448{
Marek Vasut5be355c2015-07-12 23:39:06 +0200449 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
450 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
451 const int base = write_group * ratio;
452 int i;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500453 /*
454 * Load the setting in the SCC manager
455 * Although OCT affects only write data, the OCT delay is controlled
456 * by the DQS logic block which is instantiated once per read group.
457 * For protocols where a write group consists of multiple read groups,
458 * the setting must be set multiple times.
459 */
Marek Vasut5be355c2015-07-12 23:39:06 +0200460 for (i = 0; i < ratio; i++)
461 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500462}
463
Marek Vasut37a37ca2015-07-19 01:32:55 +0200464/**
465 * scc_mgr_set_hhp_extras() - Set HHP extras.
466 *
467 * Load the fixed setting in the SCC manager HHP extras.
468 */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500469static void scc_mgr_set_hhp_extras(void)
470{
471 /*
472 * Load the fixed setting in the SCC manager
Marek Vasut37a37ca2015-07-19 01:32:55 +0200473 * bits: 0:0 = 1'b1 - DQS bypass
474 * bits: 1:1 = 1'b1 - DQ bypass
475 * bits: 4:2 = 3'b001 - rfifo_mode
476 * bits: 6:5 = 2'b01 - rfifo clock_select
477 * bits: 7:7 = 1'b0 - separate gating from ungating setting
478 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
Dinh Nguyen3da42852015-06-02 22:52:49 -0500479 */
Marek Vasut37a37ca2015-07-19 01:32:55 +0200480 const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
481 (1 << 2) | (1 << 1) | (1 << 0);
482 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
483 SCC_MGR_HHP_GLOBALS_OFFSET |
484 SCC_MGR_HHP_EXTRAS_OFFSET;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500485
Marek Vasut37a37ca2015-07-19 01:32:55 +0200486 debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
487 __func__, __LINE__);
488 writel(value, addr);
489 debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
490 __func__, __LINE__);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500491}
492
Marek Vasutf42af352015-07-20 04:41:53 +0200493/**
494 * scc_mgr_zero_all() - Zero all DQS config
495 *
496 * Zero all DQS config.
Dinh Nguyen3da42852015-06-02 22:52:49 -0500497 */
498static void scc_mgr_zero_all(void)
499{
Marek Vasutf42af352015-07-20 04:41:53 +0200500 int i, r;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500501
502 /*
503 * USER Zero all DQS config settings, across all groups and all
504 * shadow registers
505 */
Marek Vasutf42af352015-07-20 04:41:53 +0200506 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
507 r += NUM_RANKS_PER_SHADOW_REG) {
Dinh Nguyen3da42852015-06-02 22:52:49 -0500508 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
509 /*
510 * The phases actually don't exist on a per-rank basis,
511 * but there's no harm updating them several times, so
512 * let's keep the code simple.
513 */
514 scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
515 scc_mgr_set_dqs_en_phase(i, 0);
516 scc_mgr_set_dqs_en_delay(i, 0);
517 }
518
519 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
520 scc_mgr_set_dqdqs_output_phase(i, 0);
Marek Vasutf42af352015-07-20 04:41:53 +0200521 /* Arria V/Cyclone V don't have out2. */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500522 scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
523 }
524 }
525
Marek Vasutf42af352015-07-20 04:41:53 +0200526 /* Multicast to all DQS group enables. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200527 writel(0xff, &sdr_scc_mgr->dqs_ena);
528 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500529}
530
Marek Vasutc5c5f532015-07-17 02:06:20 +0200531/**
532 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
533 * @write_group: Write group
534 *
535 * Set bypass mode and trigger SCC update.
536 */
537static void scc_set_bypass_mode(const u32 write_group)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500538{
Marek Vasutc5c5f532015-07-17 02:06:20 +0200539 /* Multicast to all DQ enables. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200540 writel(0xff, &sdr_scc_mgr->dq_ena);
541 writel(0xff, &sdr_scc_mgr->dm_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500542
Marek Vasutc5c5f532015-07-17 02:06:20 +0200543 /* Update current DQS IO enable. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200544 writel(0, &sdr_scc_mgr->dqs_io_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500545
Marek Vasutc5c5f532015-07-17 02:06:20 +0200546 /* Update the DQS logic. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200547 writel(write_group, &sdr_scc_mgr->dqs_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500548
Marek Vasutc5c5f532015-07-17 02:06:20 +0200549 /* Hit update. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200550 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500551}
552
Marek Vasut5e837892015-07-13 00:30:09 +0200553/**
554 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
555 * @write_group: Write group
556 *
557 * Load DQS settings for Write Group, do not trigger SCC update.
558 */
559static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
Marek Vasut5ff825b2015-07-12 22:11:55 +0200560{
Marek Vasut5e837892015-07-13 00:30:09 +0200561 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
562 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
563 const int base = write_group * ratio;
564 int i;
Marek Vasut5ff825b2015-07-12 22:11:55 +0200565 /*
Marek Vasut5e837892015-07-13 00:30:09 +0200566 * Load the setting in the SCC manager
Marek Vasut5ff825b2015-07-12 22:11:55 +0200567 * Although OCT affects only write data, the OCT delay is controlled
568 * by the DQS logic block which is instantiated once per read group.
569 * For protocols where a write group consists of multiple read groups,
Marek Vasut5e837892015-07-13 00:30:09 +0200570 * the setting must be set multiple times.
Marek Vasut5ff825b2015-07-12 22:11:55 +0200571 */
Marek Vasut5e837892015-07-13 00:30:09 +0200572 for (i = 0; i < ratio; i++)
573 writel(base + i, &sdr_scc_mgr->dqs_ena);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200574}
575
Marek Vasutd41ea932015-07-20 08:41:04 +0200576/**
577 * scc_mgr_zero_group() - Zero all configs for a group
578 *
579 * Zero DQ, DM, DQS and OCT configs for a group.
580 */
581static void scc_mgr_zero_group(const u32 write_group, const int out_only)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500582{
Marek Vasutd41ea932015-07-20 08:41:04 +0200583 int i, r;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500584
Marek Vasutd41ea932015-07-20 08:41:04 +0200585 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
586 r += NUM_RANKS_PER_SHADOW_REG) {
587 /* Zero all DQ config settings. */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500588 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
Marek Vasut07aee5b2015-07-12 22:07:33 +0200589 scc_mgr_set_dq_out1_delay(i, 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500590 if (!out_only)
Marek Vasut07aee5b2015-07-12 22:07:33 +0200591 scc_mgr_set_dq_in_delay(i, 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500592 }
593
Marek Vasutd41ea932015-07-20 08:41:04 +0200594 /* Multicast to all DQ enables. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200595 writel(0xff, &sdr_scc_mgr->dq_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500596
Marek Vasutd41ea932015-07-20 08:41:04 +0200597 /* Zero all DM config settings. */
598 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
Marek Vasut07aee5b2015-07-12 22:07:33 +0200599 scc_mgr_set_dm_out1_delay(i, 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500600
Marek Vasutd41ea932015-07-20 08:41:04 +0200601 /* Multicast to all DM enables. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200602 writel(0xff, &sdr_scc_mgr->dm_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500603
Marek Vasutd41ea932015-07-20 08:41:04 +0200604 /* Zero all DQS IO settings. */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500605 if (!out_only)
Marek Vasut32675242015-07-17 06:07:13 +0200606 scc_mgr_set_dqs_io_in_delay(0);
Marek Vasutd41ea932015-07-20 08:41:04 +0200607
608 /* Arria V/Cyclone V don't have out2. */
Marek Vasut32675242015-07-17 06:07:13 +0200609 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500610 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
611 scc_mgr_load_dqs_for_write_group(write_group);
612
Marek Vasutd41ea932015-07-20 08:41:04 +0200613 /* Multicast to all DQS IO enables (only 1 in total). */
Marek Vasut1273dd92015-07-12 21:05:08 +0200614 writel(0, &sdr_scc_mgr->dqs_io_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500615
Marek Vasutd41ea932015-07-20 08:41:04 +0200616 /* Hit update to zero everything. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200617 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500618 }
619}
620
Dinh Nguyen3da42852015-06-02 22:52:49 -0500621/*
622 * apply and load a particular input delay for the DQ pins in a group
623 * group_bgn is the index of the first dq pin (in the write group)
624 */
Marek Vasut32675242015-07-17 06:07:13 +0200625static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500626{
627 uint32_t i, p;
628
629 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
Marek Vasut07aee5b2015-07-12 22:07:33 +0200630 scc_mgr_set_dq_in_delay(p, delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500631 scc_mgr_load_dq(p);
632 }
633}
634
Marek Vasut300c2e62015-07-17 05:42:49 +0200635/**
636 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
637 * @delay: Delay value
638 *
639 * Apply and load a particular output delay for the DQ pins in a group.
640 */
641static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500642{
Marek Vasut300c2e62015-07-17 05:42:49 +0200643 int i;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500644
Marek Vasut300c2e62015-07-17 05:42:49 +0200645 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
646 scc_mgr_set_dq_out1_delay(i, delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500647 scc_mgr_load_dq(i);
648 }
649}
650
651/* apply and load a particular output delay for the DM pins in a group */
Marek Vasut32675242015-07-17 06:07:13 +0200652static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500653{
654 uint32_t i;
655
656 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
Marek Vasut07aee5b2015-07-12 22:07:33 +0200657 scc_mgr_set_dm_out1_delay(i, delay1);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500658 scc_mgr_load_dm(i);
659 }
660}
661
662
663/* apply and load delay on both DQS and OCT out1 */
664static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
665 uint32_t delay)
666{
Marek Vasut32675242015-07-17 06:07:13 +0200667 scc_mgr_set_dqs_out1_delay(delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500668 scc_mgr_load_dqs_io();
669
670 scc_mgr_set_oct_out1_delay(write_group, delay);
671 scc_mgr_load_dqs_for_write_group(write_group);
672}
673
Marek Vasut5cb1b502015-07-17 05:33:28 +0200674/**
675 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
676 * @write_group: Write group
677 * @delay: Delay value
678 *
679 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
680 */
Marek Vasut8eccde32015-07-17 05:30:14 +0200681static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
Marek Vasut8eccde32015-07-17 05:30:14 +0200682 const u32 delay)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500683{
Marek Vasut8eccde32015-07-17 05:30:14 +0200684 u32 i, new_delay;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500685
Marek Vasut8eccde32015-07-17 05:30:14 +0200686 /* DQ shift */
687 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500688 scc_mgr_load_dq(i);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500689
Marek Vasut8eccde32015-07-17 05:30:14 +0200690 /* DM shift */
691 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500692 scc_mgr_load_dm(i);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500693
Marek Vasut5cb1b502015-07-17 05:33:28 +0200694 /* DQS shift */
695 new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500696 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
Marek Vasut5cb1b502015-07-17 05:33:28 +0200697 debug_cond(DLEVEL == 1,
698 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
699 __func__, __LINE__, write_group, delay, new_delay,
700 IO_IO_OUT2_DELAY_MAX,
Dinh Nguyen3da42852015-06-02 22:52:49 -0500701 new_delay - IO_IO_OUT2_DELAY_MAX);
Marek Vasut5cb1b502015-07-17 05:33:28 +0200702 new_delay -= IO_IO_OUT2_DELAY_MAX;
703 scc_mgr_set_dqs_out1_delay(new_delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500704 }
705
706 scc_mgr_load_dqs_io();
707
Marek Vasut5cb1b502015-07-17 05:33:28 +0200708 /* OCT shift */
709 new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500710 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
Marek Vasut5cb1b502015-07-17 05:33:28 +0200711 debug_cond(DLEVEL == 1,
712 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
713 __func__, __LINE__, write_group, delay,
714 new_delay, IO_IO_OUT2_DELAY_MAX,
Dinh Nguyen3da42852015-06-02 22:52:49 -0500715 new_delay - IO_IO_OUT2_DELAY_MAX);
Marek Vasut5cb1b502015-07-17 05:33:28 +0200716 new_delay -= IO_IO_OUT2_DELAY_MAX;
717 scc_mgr_set_oct_out1_delay(write_group, new_delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500718 }
719
720 scc_mgr_load_dqs_for_write_group(write_group);
721}
722
Marek Vasutf51a7d32015-07-19 02:18:21 +0200723/**
724 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
725 * @write_group: Write group
726 * @delay: Delay value
727 *
728 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
Dinh Nguyen3da42852015-06-02 22:52:49 -0500729 */
Marek Vasutf51a7d32015-07-19 02:18:21 +0200730static void
731scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
732 const u32 delay)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500733{
Marek Vasutf51a7d32015-07-19 02:18:21 +0200734 int r;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500735
736 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
Marek Vasutf51a7d32015-07-19 02:18:21 +0200737 r += NUM_RANKS_PER_SHADOW_REG) {
Marek Vasut5cb1b502015-07-17 05:33:28 +0200738 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
Marek Vasut1273dd92015-07-12 21:05:08 +0200739 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500740 }
741}
742
Marek Vasutf936f942015-07-26 11:07:19 +0200743/**
744 * set_jump_as_return() - Return instruction optimization
745 *
746 * Optimization used to recover some slots in ddr3 inst_rom could be
747 * applied to other protocols if we wanted to
748 */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500749static void set_jump_as_return(void)
750{
Dinh Nguyen3da42852015-06-02 22:52:49 -0500751 /*
Marek Vasutf936f942015-07-26 11:07:19 +0200752 * To save space, we replace return with jump to special shared
Dinh Nguyen3da42852015-06-02 22:52:49 -0500753 * RETURN instruction so we set the counter to large value so that
Marek Vasutf936f942015-07-26 11:07:19 +0200754 * we always jump.
Dinh Nguyen3da42852015-06-02 22:52:49 -0500755 */
Marek Vasut1273dd92015-07-12 21:05:08 +0200756 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
757 writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500758}
759
760/*
761 * should always use constants as argument to ensure all computations are
762 * performed at compile time
763 */
764static void delay_for_n_mem_clocks(const uint32_t clocks)
765{
766 uint32_t afi_clocks;
767 uint8_t inner = 0;
768 uint8_t outer = 0;
769 uint16_t c_loop = 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500770
771 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
772
773
774 afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
775 /* scale (rounding up) to get afi clocks */
776
777 /*
778 * Note, we don't bother accounting for being off a little bit
779 * because of a few extra instructions in outer loops
780 * Note, the loops have a test at the end, and do the test before
781 * the decrement, and so always perform the loop
782 * 1 time more than the counter value
783 */
784 if (afi_clocks == 0) {
785 ;
786 } else if (afi_clocks <= 0x100) {
787 inner = afi_clocks-1;
788 outer = 0;
789 c_loop = 0;
790 } else if (afi_clocks <= 0x10000) {
791 inner = 0xff;
792 outer = (afi_clocks-1) >> 8;
793 c_loop = 0;
794 } else {
795 inner = 0xff;
796 outer = 0xff;
797 c_loop = (afi_clocks-1) >> 16;
798 }
799
800 /*
801 * rom instructions are structured as follows:
802 *
803 * IDLE_LOOP2: jnz cntr0, TARGET_A
804 * IDLE_LOOP1: jnz cntr1, TARGET_B
805 * return
806 *
807 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
808 * TARGET_B is set to IDLE_LOOP2 as well
809 *
810 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
811 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
812 *
813 * a little confusing, but it helps save precious space in the inst_rom
814 * and sequencer rom and keeps the delays more accurate and reduces
815 * overhead
816 */
817 if (afi_clocks <= 0x100) {
Marek Vasut1273dd92015-07-12 21:05:08 +0200818 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
819 &sdr_rw_load_mgr_regs->load_cntr1);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500820
Marek Vasut1273dd92015-07-12 21:05:08 +0200821 writel(RW_MGR_IDLE_LOOP1,
822 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500823
Marek Vasut1273dd92015-07-12 21:05:08 +0200824 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
825 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500826 } else {
Marek Vasut1273dd92015-07-12 21:05:08 +0200827 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
828 &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500829
Marek Vasut1273dd92015-07-12 21:05:08 +0200830 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
831 &sdr_rw_load_mgr_regs->load_cntr1);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500832
Marek Vasut1273dd92015-07-12 21:05:08 +0200833 writel(RW_MGR_IDLE_LOOP2,
834 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500835
Marek Vasut1273dd92015-07-12 21:05:08 +0200836 writel(RW_MGR_IDLE_LOOP2,
837 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500838
839 /* hack to get around compiler not being smart enough */
840 if (afi_clocks <= 0x10000) {
841 /* only need to run once */
Marek Vasut1273dd92015-07-12 21:05:08 +0200842 writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
843 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500844 } else {
845 do {
Marek Vasut1273dd92015-07-12 21:05:08 +0200846 writel(RW_MGR_IDLE_LOOP2,
847 SDR_PHYGRP_RWMGRGRP_ADDRESS |
848 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500849 } while (c_loop-- != 0);
850 }
851 }
852 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
853}
854
Marek Vasut944fe712015-07-13 00:44:30 +0200855/**
856 * rw_mgr_mem_init_load_regs() - Load instruction registers
857 * @cntr0: Counter 0 value
858 * @cntr1: Counter 1 value
859 * @cntr2: Counter 2 value
860 * @jump: Jump instruction value
861 *
862 * Load instruction registers.
863 */
864static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
865{
866 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
867 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
868
869 /* Load counters */
870 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
871 &sdr_rw_load_mgr_regs->load_cntr0);
872 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
873 &sdr_rw_load_mgr_regs->load_cntr1);
874 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
875 &sdr_rw_load_mgr_regs->load_cntr2);
876
877 /* Load jump address */
878 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
879 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
880 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
881
882 /* Execute count instruction */
883 writel(jump, grpaddr);
884}
885
Marek Vasutecd23342015-07-13 00:51:05 +0200886/**
887 * rw_mgr_mem_load_user() - Load user calibration values
888 * @fin1: Final instruction 1
889 * @fin2: Final instruction 2
890 * @precharge: If 1, precharge the banks at the end
891 *
892 * Load user calibration values and optionally precharge the banks.
893 */
894static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
895 const int precharge)
896{
897 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
898 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
899 u32 r;
900
901 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
902 if (param->skip_ranks[r]) {
903 /* request to skip the rank */
904 continue;
905 }
906
907 /* set rank */
908 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
909
910 /* precharge all banks ... */
911 if (precharge)
912 writel(RW_MGR_PRECHARGE_ALL, grpaddr);
913
914 /*
915 * USER Use Mirror-ed commands for odd ranks if address
916 * mirrorring is on
917 */
918 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
919 set_jump_as_return();
920 writel(RW_MGR_MRS2_MIRR, grpaddr);
921 delay_for_n_mem_clocks(4);
922 set_jump_as_return();
923 writel(RW_MGR_MRS3_MIRR, grpaddr);
924 delay_for_n_mem_clocks(4);
925 set_jump_as_return();
926 writel(RW_MGR_MRS1_MIRR, grpaddr);
927 delay_for_n_mem_clocks(4);
928 set_jump_as_return();
929 writel(fin1, grpaddr);
930 } else {
931 set_jump_as_return();
932 writel(RW_MGR_MRS2, grpaddr);
933 delay_for_n_mem_clocks(4);
934 set_jump_as_return();
935 writel(RW_MGR_MRS3, grpaddr);
936 delay_for_n_mem_clocks(4);
937 set_jump_as_return();
938 writel(RW_MGR_MRS1, grpaddr);
939 set_jump_as_return();
940 writel(fin2, grpaddr);
941 }
942
943 if (precharge)
944 continue;
945
946 set_jump_as_return();
947 writel(RW_MGR_ZQCL, grpaddr);
948
949 /* tZQinit = tDLLK = 512 ck cycles */
950 delay_for_n_mem_clocks(512);
951 }
952}
953
Marek Vasut8e9d7d02015-07-26 10:57:06 +0200954/**
955 * rw_mgr_mem_initialize() - Initialize RW Manager
956 *
957 * Initialize RW Manager.
958 */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500959static void rw_mgr_mem_initialize(void)
960{
Dinh Nguyen3da42852015-06-02 22:52:49 -0500961 debug("%s:%d\n", __func__, __LINE__);
962
963 /* The reset / cke part of initialization is broadcasted to all ranks */
Marek Vasut1273dd92015-07-12 21:05:08 +0200964 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
965 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500966
967 /*
968 * Here's how you load register for a loop
969 * Counters are located @ 0x800
970 * Jump address are located @ 0xC00
971 * For both, registers 0 to 3 are selected using bits 3 and 2, like
972 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
973 * I know this ain't pretty, but Avalon bus throws away the 2 least
974 * significant bits
975 */
976
Marek Vasut8e9d7d02015-07-26 10:57:06 +0200977 /* Start with memory RESET activated */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500978
979 /* tINIT = 200us */
980
981 /*
982 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
983 * If a and b are the number of iteration in 2 nested loops
984 * it takes the following number of cycles to complete the operation:
985 * number_of_cycles = ((2 + n) * a + 2) * b
986 * where n is the number of instruction in the inner loop
987 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
988 * b = 6A
989 */
Marek Vasut944fe712015-07-13 00:44:30 +0200990 rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
991 SEQ_TINIT_CNTR2_VAL,
992 RW_MGR_INIT_RESET_0_CKE_0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500993
Marek Vasut8e9d7d02015-07-26 10:57:06 +0200994 /* Indicate that memory is stable. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200995 writel(1, &phy_mgr_cfg->reset_mem_stbl);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500996
997 /*
998 * transition the RESET to high
999 * Wait for 500us
1000 */
1001
1002 /*
1003 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1004 * If a and b are the number of iteration in 2 nested loops
1005 * it takes the following number of cycles to complete the operation
1006 * number_of_cycles = ((2 + n) * a + 2) * b
1007 * where n is the number of instruction in the inner loop
1008 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1009 * b = FF
1010 */
Marek Vasut944fe712015-07-13 00:44:30 +02001011 rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1012 SEQ_TRESET_CNTR2_VAL,
1013 RW_MGR_INIT_RESET_1_CKE_0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001014
Marek Vasut8e9d7d02015-07-26 10:57:06 +02001015 /* Bring up clock enable. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05001016
1017 /* tXRP < 250 ck cycles */
1018 delay_for_n_mem_clocks(250);
1019
Marek Vasutecd23342015-07-13 00:51:05 +02001020 rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1021 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001022}
1023
1024/*
1025 * At the end of calibration we have to program the user settings in, and
1026 * USER hand off the memory to the user.
1027 */
1028static void rw_mgr_mem_handoff(void)
1029{
Marek Vasutecd23342015-07-13 00:51:05 +02001030 rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1031 /*
1032 * USER need to wait tMOD (12CK or 15ns) time before issuing
1033 * other commands, but we will have plenty of NIOS cycles before
1034 * actual handoff so its okay.
1035 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05001036}
1037
1038/*
1039 * performs a guaranteed read on the patterns we are going to use during a
1040 * read test to ensure memory works
1041 */
1042static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
1043 uint32_t group, uint32_t num_tries, uint32_t *bit_chk,
1044 uint32_t all_ranks)
1045{
1046 uint32_t r, vg;
1047 uint32_t correct_mask_vg;
1048 uint32_t tmp_bit_chk;
1049 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1050 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1051 uint32_t addr;
1052 uint32_t base_rw_mgr;
1053
1054 *bit_chk = param->read_correct_mask;
1055 correct_mask_vg = param->read_correct_mask_vg;
1056
1057 for (r = rank_bgn; r < rank_end; r++) {
1058 if (param->skip_ranks[r])
1059 /* request to skip the rank */
1060 continue;
1061
1062 /* set rank */
1063 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1064
1065 /* Load up a constant bursts of read commands */
Marek Vasut1273dd92015-07-12 21:05:08 +02001066 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1067 writel(RW_MGR_GUARANTEED_READ,
1068 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001069
Marek Vasut1273dd92015-07-12 21:05:08 +02001070 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1071 writel(RW_MGR_GUARANTEED_READ_CONT,
1072 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001073
1074 tmp_bit_chk = 0;
1075 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1076 /* reset the fifos to get pointers to known state */
1077
Marek Vasut1273dd92015-07-12 21:05:08 +02001078 writel(0, &phy_mgr_cmd->fifo_reset);
1079 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1080 RW_MGR_RESET_READ_DATAPATH_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001081
1082 tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1083 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1084
Marek Vasutc4815f72015-07-12 19:03:33 +02001085 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
Marek Vasut17fdc912015-07-12 20:05:54 +02001086 writel(RW_MGR_GUARANTEED_READ, addr +
Dinh Nguyen3da42852015-06-02 22:52:49 -05001087 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1088 vg) << 2));
1089
Marek Vasut1273dd92015-07-12 21:05:08 +02001090 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001091 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
1092
1093 if (vg == 0)
1094 break;
1095 }
1096 *bit_chk &= tmp_bit_chk;
1097 }
1098
Marek Vasutc4815f72015-07-12 19:03:33 +02001099 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
Marek Vasut17fdc912015-07-12 20:05:54 +02001100 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05001101
1102 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1103 debug_cond(DLEVEL == 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) =>\
1104 %lu\n", __func__, __LINE__, group, *bit_chk, param->read_correct_mask,
1105 (long unsigned int)(*bit_chk == param->read_correct_mask));
1106 return *bit_chk == param->read_correct_mask;
1107}
1108
1109static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks
1110 (uint32_t group, uint32_t num_tries, uint32_t *bit_chk)
1111{
1112 return rw_mgr_mem_calibrate_read_test_patterns(0, group,
1113 num_tries, bit_chk, 1);
1114}
1115
1116/* load up the patterns we are going to use during a read test */
1117static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,
1118 uint32_t all_ranks)
1119{
1120 uint32_t r;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001121 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1122 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1123
1124 debug("%s:%d\n", __func__, __LINE__);
1125 for (r = rank_bgn; r < rank_end; r++) {
1126 if (param->skip_ranks[r])
1127 /* request to skip the rank */
1128 continue;
1129
1130 /* set rank */
1131 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1132
1133 /* Load up a constant bursts */
Marek Vasut1273dd92015-07-12 21:05:08 +02001134 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001135
Marek Vasut1273dd92015-07-12 21:05:08 +02001136 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1137 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001138
Marek Vasut1273dd92015-07-12 21:05:08 +02001139 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001140
Marek Vasut1273dd92015-07-12 21:05:08 +02001141 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1142 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001143
Marek Vasut1273dd92015-07-12 21:05:08 +02001144 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001145
Marek Vasut1273dd92015-07-12 21:05:08 +02001146 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1147 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001148
Marek Vasut1273dd92015-07-12 21:05:08 +02001149 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001150
Marek Vasut1273dd92015-07-12 21:05:08 +02001151 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1152 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001153
Marek Vasut1273dd92015-07-12 21:05:08 +02001154 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1155 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001156 }
1157
1158 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1159}
1160
1161/*
1162 * try a read and see if it returns correct data back. has dummy reads
1163 * inserted into the mix used to align dqs enable. has more thorough checks
1164 * than the regular read test.
1165 */
1166static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1167 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1168 uint32_t all_groups, uint32_t all_ranks)
1169{
1170 uint32_t r, vg;
1171 uint32_t correct_mask_vg;
1172 uint32_t tmp_bit_chk;
1173 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1174 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1175 uint32_t addr;
1176 uint32_t base_rw_mgr;
1177
1178 *bit_chk = param->read_correct_mask;
1179 correct_mask_vg = param->read_correct_mask_vg;
1180
1181 uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1182 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1183
1184 for (r = rank_bgn; r < rank_end; r++) {
1185 if (param->skip_ranks[r])
1186 /* request to skip the rank */
1187 continue;
1188
1189 /* set rank */
1190 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1191
Marek Vasut1273dd92015-07-12 21:05:08 +02001192 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001193
Marek Vasut1273dd92015-07-12 21:05:08 +02001194 writel(RW_MGR_READ_B2B_WAIT1,
1195 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001196
Marek Vasut1273dd92015-07-12 21:05:08 +02001197 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1198 writel(RW_MGR_READ_B2B_WAIT2,
1199 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001200
Dinh Nguyen3da42852015-06-02 22:52:49 -05001201 if (quick_read_mode)
Marek Vasut1273dd92015-07-12 21:05:08 +02001202 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001203 /* need at least two (1+1) reads to capture failures */
1204 else if (all_groups)
Marek Vasut1273dd92015-07-12 21:05:08 +02001205 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001206 else
Marek Vasut1273dd92015-07-12 21:05:08 +02001207 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001208
Marek Vasut1273dd92015-07-12 21:05:08 +02001209 writel(RW_MGR_READ_B2B,
1210 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001211 if (all_groups)
1212 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1213 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
Marek Vasut1273dd92015-07-12 21:05:08 +02001214 &sdr_rw_load_mgr_regs->load_cntr3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001215 else
Marek Vasut1273dd92015-07-12 21:05:08 +02001216 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001217
Marek Vasut1273dd92015-07-12 21:05:08 +02001218 writel(RW_MGR_READ_B2B,
1219 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001220
1221 tmp_bit_chk = 0;
1222 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1223 /* reset the fifos to get pointers to known state */
Marek Vasut1273dd92015-07-12 21:05:08 +02001224 writel(0, &phy_mgr_cmd->fifo_reset);
1225 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1226 RW_MGR_RESET_READ_DATAPATH_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001227
1228 tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1229 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1230
Marek Vasutc4815f72015-07-12 19:03:33 +02001231 if (all_groups)
1232 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1233 else
1234 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1235
Marek Vasut17fdc912015-07-12 20:05:54 +02001236 writel(RW_MGR_READ_B2B, addr +
Dinh Nguyen3da42852015-06-02 22:52:49 -05001237 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1238 vg) << 2));
1239
Marek Vasut1273dd92015-07-12 21:05:08 +02001240 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001241 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1242
1243 if (vg == 0)
1244 break;
1245 }
1246 *bit_chk &= tmp_bit_chk;
1247 }
1248
Marek Vasutc4815f72015-07-12 19:03:33 +02001249 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
Marek Vasut17fdc912015-07-12 20:05:54 +02001250 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05001251
1252 if (all_correct) {
1253 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1254 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1255 (%u == %u) => %lu", __func__, __LINE__, group,
1256 all_groups, *bit_chk, param->read_correct_mask,
1257 (long unsigned int)(*bit_chk ==
1258 param->read_correct_mask));
1259 return *bit_chk == param->read_correct_mask;
1260 } else {
1261 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1262 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1263 (%u != %lu) => %lu\n", __func__, __LINE__,
1264 group, all_groups, *bit_chk, (long unsigned int)0,
1265 (long unsigned int)(*bit_chk != 0x00));
1266 return *bit_chk != 0x00;
1267 }
1268}
1269
1270static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1271 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1272 uint32_t all_groups)
1273{
1274 return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1275 bit_chk, all_groups, 1);
1276}
1277
1278static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
1279{
Marek Vasut1273dd92015-07-12 21:05:08 +02001280 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001281 (*v)++;
1282}
1283
1284static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
1285{
1286 uint32_t i;
1287
1288 for (i = 0; i < VFIFO_SIZE-1; i++)
1289 rw_mgr_incr_vfifo(grp, v);
1290}
1291
1292static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
1293{
1294 uint32_t v;
1295 uint32_t fail_cnt = 0;
1296 uint32_t test_status;
1297
1298 for (v = 0; v < VFIFO_SIZE; ) {
1299 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1300 __func__, __LINE__, v);
1301 test_status = rw_mgr_mem_calibrate_read_test_all_ranks
1302 (grp, 1, PASS_ONE_BIT, bit_chk, 0);
1303 if (!test_status) {
1304 fail_cnt++;
1305
1306 if (fail_cnt == 2)
1307 break;
1308 }
1309
1310 /* fiddle with FIFO */
1311 rw_mgr_incr_vfifo(grp, &v);
1312 }
1313
1314 if (v >= VFIFO_SIZE) {
1315 /* no failing read found!! Something must have gone wrong */
1316 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1317 __func__, __LINE__);
1318 return 0;
1319 } else {
1320 return v;
1321 }
1322}
1323
1324static int find_working_phase(uint32_t *grp, uint32_t *bit_chk,
1325 uint32_t dtaps_per_ptap, uint32_t *work_bgn,
1326 uint32_t *v, uint32_t *d, uint32_t *p,
1327 uint32_t *i, uint32_t *max_working_cnt)
1328{
1329 uint32_t found_begin = 0;
1330 uint32_t tmp_delay = 0;
1331 uint32_t test_status;
1332
1333 for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
1334 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1335 *work_bgn = tmp_delay;
1336 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1337
1338 for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
1339 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
1340 IO_DELAY_PER_OPA_TAP) {
1341 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1342
1343 test_status =
1344 rw_mgr_mem_calibrate_read_test_all_ranks
1345 (*grp, 1, PASS_ONE_BIT, bit_chk, 0);
1346
1347 if (test_status) {
1348 *max_working_cnt = 1;
1349 found_begin = 1;
1350 break;
1351 }
1352 }
1353
1354 if (found_begin)
1355 break;
1356
1357 if (*p > IO_DQS_EN_PHASE_MAX)
1358 /* fiddle with FIFO */
1359 rw_mgr_incr_vfifo(*grp, v);
1360 }
1361
1362 if (found_begin)
1363 break;
1364 }
1365
1366 if (*i >= VFIFO_SIZE) {
1367 /* cannot find working solution */
1368 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
1369 ptap/dtap\n", __func__, __LINE__);
1370 return 0;
1371 } else {
1372 return 1;
1373 }
1374}
1375
1376static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
1377 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1378 uint32_t *p, uint32_t *max_working_cnt)
1379{
1380 uint32_t found_begin = 0;
1381 uint32_t tmp_delay;
1382
1383 /* Special case code for backing up a phase */
1384 if (*p == 0) {
1385 *p = IO_DQS_EN_PHASE_MAX;
1386 rw_mgr_decr_vfifo(*grp, v);
1387 } else {
1388 (*p)--;
1389 }
1390 tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1391 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1392
1393 for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
1394 (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1395 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1396
1397 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1398 PASS_ONE_BIT,
1399 bit_chk, 0)) {
1400 found_begin = 1;
1401 *work_bgn = tmp_delay;
1402 break;
1403 }
1404 }
1405
1406 /* We have found a working dtap before the ptap found above */
1407 if (found_begin == 1)
1408 (*max_working_cnt)++;
1409
1410 /*
1411 * Restore VFIFO to old state before we decremented it
1412 * (if needed).
1413 */
1414 (*p)++;
1415 if (*p > IO_DQS_EN_PHASE_MAX) {
1416 *p = 0;
1417 rw_mgr_incr_vfifo(*grp, v);
1418 }
1419
1420 scc_mgr_set_dqs_en_delay_all_ranks(*grp, 0);
1421}
1422
1423static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
1424 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1425 uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
1426 uint32_t *work_end)
1427{
1428 uint32_t found_end = 0;
1429
1430 (*p)++;
1431 *work_end += IO_DELAY_PER_OPA_TAP;
1432 if (*p > IO_DQS_EN_PHASE_MAX) {
1433 /* fiddle with FIFO */
1434 *p = 0;
1435 rw_mgr_incr_vfifo(*grp, v);
1436 }
1437
1438 for (; *i < VFIFO_SIZE + 1; (*i)++) {
1439 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
1440 += IO_DELAY_PER_OPA_TAP) {
1441 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1442
1443 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1444 (*grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
1445 found_end = 1;
1446 break;
1447 } else {
1448 (*max_working_cnt)++;
1449 }
1450 }
1451
1452 if (found_end)
1453 break;
1454
1455 if (*p > IO_DQS_EN_PHASE_MAX) {
1456 /* fiddle with FIFO */
1457 rw_mgr_incr_vfifo(*grp, v);
1458 *p = 0;
1459 }
1460 }
1461
1462 if (*i >= VFIFO_SIZE + 1) {
1463 /* cannot see edge of failing read */
1464 debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
1465 failed\n", __func__, __LINE__);
1466 return 0;
1467 } else {
1468 return 1;
1469 }
1470}
1471
1472static int sdr_find_window_centre(uint32_t *grp, uint32_t *bit_chk,
1473 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1474 uint32_t *p, uint32_t *work_mid,
1475 uint32_t *work_end)
1476{
1477 int i;
1478 int tmp_delay = 0;
1479
1480 *work_mid = (*work_bgn + *work_end) / 2;
1481
1482 debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1483 *work_bgn, *work_end, *work_mid);
1484 /* Get the middle delay to be less than a VFIFO delay */
1485 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX;
1486 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1487 ;
1488 debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1489 while (*work_mid > tmp_delay)
1490 *work_mid -= tmp_delay;
1491 debug_cond(DLEVEL == 2, "new work_mid %d\n", *work_mid);
1492
1493 tmp_delay = 0;
1494 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX && tmp_delay < *work_mid;
1495 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1496 ;
1497 tmp_delay -= IO_DELAY_PER_OPA_TAP;
1498 debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", (*p) - 1, tmp_delay);
1499 for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_mid; (*d)++,
1500 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP)
1501 ;
1502 debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", *d, tmp_delay);
1503
1504 scc_mgr_set_dqs_en_phase_all_ranks(*grp, (*p) - 1);
1505 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1506
1507 /*
1508 * push vfifo until we can successfully calibrate. We can do this
1509 * because the largest possible margin in 1 VFIFO cycle.
1510 */
1511 for (i = 0; i < VFIFO_SIZE; i++) {
1512 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
1513 *v);
1514 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1515 PASS_ONE_BIT,
1516 bit_chk, 0)) {
1517 break;
1518 }
1519
1520 /* fiddle with FIFO */
1521 rw_mgr_incr_vfifo(*grp, v);
1522 }
1523
1524 if (i >= VFIFO_SIZE) {
1525 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center: \
1526 failed\n", __func__, __LINE__);
1527 return 0;
1528 } else {
1529 return 1;
1530 }
1531}
1532
1533/* find a good dqs enable to use */
1534static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
1535{
1536 uint32_t v, d, p, i;
1537 uint32_t max_working_cnt;
1538 uint32_t bit_chk;
1539 uint32_t dtaps_per_ptap;
1540 uint32_t work_bgn, work_mid, work_end;
1541 uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001542
1543 debug("%s:%d %u\n", __func__, __LINE__, grp);
1544
1545 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1546
1547 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1548 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1549
1550 /* ************************************************************** */
1551 /* * Step 0 : Determine number of delay taps for each phase tap * */
1552 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1553
1554 /* ********************************************************* */
1555 /* * Step 1 : First push vfifo until we get a failing read * */
1556 v = find_vfifo_read(grp, &bit_chk);
1557
1558 max_working_cnt = 0;
1559
1560 /* ******************************************************** */
1561 /* * step 2: find first working phase, increment in ptaps * */
1562 work_bgn = 0;
1563 if (find_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
1564 &p, &i, &max_working_cnt) == 0)
1565 return 0;
1566
1567 work_end = work_bgn;
1568
1569 /*
1570 * If d is 0 then the working window covers a phase tap and
1571 * we can follow the old procedure otherwise, we've found the beginning,
1572 * and we need to increment the dtaps until we find the end.
1573 */
1574 if (d == 0) {
1575 /* ********************************************************* */
1576 /* * step 3a: if we have room, back off by one and
1577 increment in dtaps * */
1578
1579 sdr_backup_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1580 &max_working_cnt);
1581
1582 /* ********************************************************* */
1583 /* * step 4a: go forward from working phase to non working
1584 phase, increment in ptaps * */
1585 if (sdr_nonworking_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1586 &i, &max_working_cnt, &work_end) == 0)
1587 return 0;
1588
1589 /* ********************************************************* */
1590 /* * step 5a: back off one from last, increment in dtaps * */
1591
1592 /* Special case code for backing up a phase */
1593 if (p == 0) {
1594 p = IO_DQS_EN_PHASE_MAX;
1595 rw_mgr_decr_vfifo(grp, &v);
1596 } else {
1597 p = p - 1;
1598 }
1599
1600 work_end -= IO_DELAY_PER_OPA_TAP;
1601 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1602
1603 /* * The actual increment of dtaps is done outside of
1604 the if/else loop to share code */
1605 d = 0;
1606
1607 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
1608 vfifo=%u ptap=%u\n", __func__, __LINE__,
1609 v, p);
1610 } else {
1611 /* ******************************************************* */
1612 /* * step 3-5b: Find the right edge of the window using
1613 delay taps * */
1614 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1615 ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
1616 v, p, d, work_bgn);
1617
1618 work_end = work_bgn;
1619
1620 /* * The actual increment of dtaps is done outside of the
1621 if/else loop to share code */
1622
1623 /* Only here to counterbalance a subtract later on which is
1624 not needed if this branch of the algorithm is taken */
1625 max_working_cnt++;
1626 }
1627
1628 /* The dtap increment to find the failing edge is done here */
1629 for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
1630 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1631 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1632 end-2: dtap=%u\n", __func__, __LINE__, d);
1633 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1634
1635 if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1636 PASS_ONE_BIT,
1637 &bit_chk, 0)) {
1638 break;
1639 }
1640 }
1641
1642 /* Go back to working dtap */
1643 if (d != 0)
1644 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1645
1646 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1647 ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
1648 v, p, d-1, work_end);
1649
1650 if (work_end < work_bgn) {
1651 /* nil range */
1652 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
1653 failed\n", __func__, __LINE__);
1654 return 0;
1655 }
1656
1657 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1658 __func__, __LINE__, work_bgn, work_end);
1659
1660 /* *************************************************************** */
1661 /*
1662 * * We need to calculate the number of dtaps that equal a ptap
1663 * * To do that we'll back up a ptap and re-find the edge of the
1664 * * window using dtaps
1665 */
1666
1667 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1668 for tracking\n", __func__, __LINE__);
1669
1670 /* Special case code for backing up a phase */
1671 if (p == 0) {
1672 p = IO_DQS_EN_PHASE_MAX;
1673 rw_mgr_decr_vfifo(grp, &v);
1674 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1675 cycle/phase: v=%u p=%u\n", __func__, __LINE__,
1676 v, p);
1677 } else {
1678 p = p - 1;
1679 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1680 phase only: v=%u p=%u", __func__, __LINE__,
1681 v, p);
1682 }
1683
1684 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1685
1686 /*
1687 * Increase dtap until we first see a passing read (in case the
1688 * window is smaller than a ptap),
1689 * and then a failing read to mark the edge of the window again
1690 */
1691
1692 /* Find a passing read */
1693 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
1694 __func__, __LINE__);
1695 found_passing_read = 0;
1696 found_failing_read = 0;
1697 initial_failing_dtap = d;
1698 for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1699 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
1700 read d=%u\n", __func__, __LINE__, d);
1701 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1702
1703 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1704 PASS_ONE_BIT,
1705 &bit_chk, 0)) {
1706 found_passing_read = 1;
1707 break;
1708 }
1709 }
1710
1711 if (found_passing_read) {
1712 /* Find a failing read */
1713 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
1714 read\n", __func__, __LINE__);
1715 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1716 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1717 testing read d=%u\n", __func__, __LINE__, d);
1718 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1719
1720 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1721 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1722 found_failing_read = 1;
1723 break;
1724 }
1725 }
1726 } else {
1727 debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
1728 calculate dtaps", __func__, __LINE__);
1729 debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
1730 }
1731
1732 /*
1733 * The dynamically calculated dtaps_per_ptap is only valid if we
1734 * found a passing/failing read. If we didn't, it means d hit the max
1735 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1736 * statically calculated value.
1737 */
1738 if (found_passing_read && found_failing_read)
1739 dtaps_per_ptap = d - initial_failing_dtap;
1740
Marek Vasut1273dd92015-07-12 21:05:08 +02001741 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001742 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1743 - %u = %u", __func__, __LINE__, d,
1744 initial_failing_dtap, dtaps_per_ptap);
1745
1746 /* ******************************************** */
1747 /* * step 6: Find the centre of the window * */
1748 if (sdr_find_window_centre(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1749 &work_mid, &work_end) == 0)
1750 return 0;
1751
1752 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center found: \
1753 vfifo=%u ptap=%u dtap=%u\n", __func__, __LINE__,
1754 v, p-1, d);
1755 return 1;
1756}
1757
1758/*
1759 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
1760 * dq_in_delay values
1761 */
1762static uint32_t
1763rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
1764(uint32_t write_group, uint32_t read_group, uint32_t test_bgn)
1765{
1766 uint32_t found;
1767 uint32_t i;
1768 uint32_t p;
1769 uint32_t d;
1770 uint32_t r;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001771
1772 const uint32_t delay_step = IO_IO_IN_DELAY_MAX /
1773 (RW_MGR_MEM_DQ_PER_READ_DQS-1);
1774 /* we start at zero, so have one less dq to devide among */
1775
1776 debug("%s:%d (%u,%u,%u)", __func__, __LINE__, write_group, read_group,
1777 test_bgn);
1778
1779 /* try different dq_in_delays since the dq path is shorter than dqs */
1780
1781 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1782 r += NUM_RANKS_PER_SHADOW_REG) {
Marek Vasut32675242015-07-17 06:07:13 +02001783 for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++, d += delay_step) {
Dinh Nguyen3da42852015-06-02 22:52:49 -05001784 debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_\
1785 vfifo_find_dqs_", __func__, __LINE__);
1786 debug_cond(DLEVEL == 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
1787 write_group, read_group);
1788 debug_cond(DLEVEL == 1, "r=%u, i=%u p=%u d=%u\n", r, i , p, d);
Marek Vasut07aee5b2015-07-12 22:07:33 +02001789 scc_mgr_set_dq_in_delay(p, d);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001790 scc_mgr_load_dq(p);
1791 }
Marek Vasut1273dd92015-07-12 21:05:08 +02001792 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001793 }
1794
1795 found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
1796
1797 debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_vfifo_find_dqs_\
1798 en_phase_sweep_dq", __func__, __LINE__);
1799 debug_cond(DLEVEL == 1, "_in_delay: g=%u/%u found=%u; Reseting delay \
1800 chain to zero\n", write_group, read_group, found);
1801
1802 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1803 r += NUM_RANKS_PER_SHADOW_REG) {
1804 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS;
1805 i++, p++) {
Marek Vasut07aee5b2015-07-12 22:07:33 +02001806 scc_mgr_set_dq_in_delay(p, 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001807 scc_mgr_load_dq(p);
1808 }
Marek Vasut1273dd92015-07-12 21:05:08 +02001809 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001810 }
1811
1812 return found;
1813}
1814
1815/* per-bit deskew DQ and center */
1816static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1817 uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1818 uint32_t use_read_test, uint32_t update_fom)
1819{
1820 uint32_t i, p, d, min_index;
1821 /*
1822 * Store these as signed since there are comparisons with
1823 * signed numbers.
1824 */
1825 uint32_t bit_chk;
1826 uint32_t sticky_bit_chk;
1827 int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1828 int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1829 int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1830 int32_t mid;
1831 int32_t orig_mid_min, mid_min;
1832 int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1833 final_dqs_en;
1834 int32_t dq_margin, dqs_margin;
1835 uint32_t stop;
1836 uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1837 uint32_t addr;
1838
1839 debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1840
Marek Vasutc4815f72015-07-12 19:03:33 +02001841 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
Marek Vasut17fdc912015-07-12 20:05:54 +02001842 start_dqs = readl(addr + (read_group << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05001843 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
Marek Vasut17fdc912015-07-12 20:05:54 +02001844 start_dqs_en = readl(addr + ((read_group << 2)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001845 - IO_DQS_EN_DELAY_OFFSET));
1846
1847 /* set the left and right edge of each bit to an illegal value */
1848 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1849 sticky_bit_chk = 0;
1850 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1851 left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1852 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1853 }
1854
Dinh Nguyen3da42852015-06-02 22:52:49 -05001855 /* Search for the left edge of the window for each bit */
1856 for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1857 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1858
Marek Vasut1273dd92015-07-12 21:05:08 +02001859 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001860
1861 /*
1862 * Stop searching when the read test doesn't pass AND when
1863 * we've seen a passing read on every bit.
1864 */
1865 if (use_read_test) {
1866 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1867 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1868 &bit_chk, 0, 0);
1869 } else {
1870 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1871 0, PASS_ONE_BIT,
1872 &bit_chk, 0);
1873 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1874 (read_group - (write_group *
1875 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1876 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1877 stop = (bit_chk == 0);
1878 }
1879 sticky_bit_chk = sticky_bit_chk | bit_chk;
1880 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1881 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1882 && %u", __func__, __LINE__, d,
1883 sticky_bit_chk,
1884 param->read_correct_mask, stop);
1885
1886 if (stop == 1) {
1887 break;
1888 } else {
1889 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1890 if (bit_chk & 1) {
1891 /* Remember a passing test as the
1892 left_edge */
1893 left_edge[i] = d;
1894 } else {
1895 /* If a left edge has not been seen yet,
1896 then a future passing test will mark
1897 this edge as the right edge */
1898 if (left_edge[i] ==
1899 IO_IO_IN_DELAY_MAX + 1) {
1900 right_edge[i] = -(d + 1);
1901 }
1902 }
1903 bit_chk = bit_chk >> 1;
1904 }
1905 }
1906 }
1907
1908 /* Reset DQ delay chains to 0 */
Marek Vasut32675242015-07-17 06:07:13 +02001909 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001910 sticky_bit_chk = 0;
1911 for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1912 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1913 %d right_edge[%u]: %d\n", __func__, __LINE__,
1914 i, left_edge[i], i, right_edge[i]);
1915
1916 /*
1917 * Check for cases where we haven't found the left edge,
1918 * which makes our assignment of the the right edge invalid.
1919 * Reset it to the illegal value.
1920 */
1921 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1922 right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1923 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1924 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1925 right_edge[%u]: %d\n", __func__, __LINE__,
1926 i, right_edge[i]);
1927 }
1928
1929 /*
1930 * Reset sticky bit (except for bits where we have seen
1931 * both the left and right edge).
1932 */
1933 sticky_bit_chk = sticky_bit_chk << 1;
1934 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1935 (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1936 sticky_bit_chk = sticky_bit_chk | 1;
1937 }
1938
1939 if (i == 0)
1940 break;
1941 }
1942
Dinh Nguyen3da42852015-06-02 22:52:49 -05001943 /* Search for the right edge of the window for each bit */
1944 for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1945 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1946 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1947 uint32_t delay = d + start_dqs_en;
1948 if (delay > IO_DQS_EN_DELAY_MAX)
1949 delay = IO_DQS_EN_DELAY_MAX;
1950 scc_mgr_set_dqs_en_delay(read_group, delay);
1951 }
1952 scc_mgr_load_dqs(read_group);
1953
Marek Vasut1273dd92015-07-12 21:05:08 +02001954 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001955
1956 /*
1957 * Stop searching when the read test doesn't pass AND when
1958 * we've seen a passing read on every bit.
1959 */
1960 if (use_read_test) {
1961 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1962 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1963 &bit_chk, 0, 0);
1964 } else {
1965 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1966 0, PASS_ONE_BIT,
1967 &bit_chk, 0);
1968 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1969 (read_group - (write_group *
1970 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1971 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1972 stop = (bit_chk == 0);
1973 }
1974 sticky_bit_chk = sticky_bit_chk | bit_chk;
1975 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1976
1977 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1978 %u && %u", __func__, __LINE__, d,
1979 sticky_bit_chk, param->read_correct_mask, stop);
1980
1981 if (stop == 1) {
1982 break;
1983 } else {
1984 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1985 if (bit_chk & 1) {
1986 /* Remember a passing test as
1987 the right_edge */
1988 right_edge[i] = d;
1989 } else {
1990 if (d != 0) {
1991 /* If a right edge has not been
1992 seen yet, then a future passing
1993 test will mark this edge as the
1994 left edge */
1995 if (right_edge[i] ==
1996 IO_IO_IN_DELAY_MAX + 1) {
1997 left_edge[i] = -(d + 1);
1998 }
1999 } else {
2000 /* d = 0 failed, but it passed
2001 when testing the left edge,
2002 so it must be marginal,
2003 set it to -1 */
2004 if (right_edge[i] ==
2005 IO_IO_IN_DELAY_MAX + 1 &&
2006 left_edge[i] !=
2007 IO_IO_IN_DELAY_MAX
2008 + 1) {
2009 right_edge[i] = -1;
2010 }
2011 /* If a right edge has not been
2012 seen yet, then a future passing
2013 test will mark this edge as the
2014 left edge */
2015 else if (right_edge[i] ==
2016 IO_IO_IN_DELAY_MAX +
2017 1) {
2018 left_edge[i] = -(d + 1);
2019 }
2020 }
2021 }
2022
2023 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
2024 d=%u]: ", __func__, __LINE__, d);
2025 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
2026 (int)(bit_chk & 1), i, left_edge[i]);
2027 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2028 right_edge[i]);
2029 bit_chk = bit_chk >> 1;
2030 }
2031 }
2032 }
2033
2034 /* Check that all bits have a window */
Dinh Nguyen3da42852015-06-02 22:52:49 -05002035 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2036 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
2037 %d right_edge[%u]: %d", __func__, __LINE__,
2038 i, left_edge[i], i, right_edge[i]);
2039 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
2040 == IO_IO_IN_DELAY_MAX + 1)) {
2041 /*
2042 * Restore delay chain settings before letting the loop
2043 * in rw_mgr_mem_calibrate_vfifo to retry different
2044 * dqs/ck relationships.
2045 */
2046 scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2047 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2048 scc_mgr_set_dqs_en_delay(read_group,
2049 start_dqs_en);
2050 }
2051 scc_mgr_load_dqs(read_group);
Marek Vasut1273dd92015-07-12 21:05:08 +02002052 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002053
2054 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2055 find edge [%u]: %d %d", __func__, __LINE__,
2056 i, left_edge[i], right_edge[i]);
2057 if (use_read_test) {
2058 set_failing_group_stage(read_group *
2059 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2060 CAL_STAGE_VFIFO,
2061 CAL_SUBSTAGE_VFIFO_CENTER);
2062 } else {
2063 set_failing_group_stage(read_group *
2064 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2065 CAL_STAGE_VFIFO_AFTER_WRITES,
2066 CAL_SUBSTAGE_VFIFO_CENTER);
2067 }
2068 return 0;
2069 }
2070 }
2071
2072 /* Find middle of window for each DQ bit */
2073 mid_min = left_edge[0] - right_edge[0];
2074 min_index = 0;
2075 for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2076 mid = left_edge[i] - right_edge[i];
2077 if (mid < mid_min) {
2078 mid_min = mid;
2079 min_index = i;
2080 }
2081 }
2082
2083 /*
2084 * -mid_min/2 represents the amount that we need to move DQS.
2085 * If mid_min is odd and positive we'll need to add one to
2086 * make sure the rounding in further calculations is correct
2087 * (always bias to the right), so just add 1 for all positive values.
2088 */
2089 if (mid_min > 0)
2090 mid_min++;
2091
2092 mid_min = mid_min / 2;
2093
2094 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2095 __func__, __LINE__, mid_min, min_index);
2096
2097 /* Determine the amount we can change DQS (which is -mid_min) */
2098 orig_mid_min = mid_min;
2099 new_dqs = start_dqs - mid_min;
2100 if (new_dqs > IO_DQS_IN_DELAY_MAX)
2101 new_dqs = IO_DQS_IN_DELAY_MAX;
2102 else if (new_dqs < 0)
2103 new_dqs = 0;
2104
2105 mid_min = start_dqs - new_dqs;
2106 debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2107 mid_min, new_dqs);
2108
2109 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2110 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2111 mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2112 else if (start_dqs_en - mid_min < 0)
2113 mid_min += start_dqs_en - mid_min;
2114 }
2115 new_dqs = start_dqs - mid_min;
2116
2117 debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2118 new_dqs=%d mid_min=%d\n", start_dqs,
2119 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2120 new_dqs, mid_min);
2121
2122 /* Initialize data for export structures */
2123 dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2124 dq_margin = IO_IO_IN_DELAY_MAX + 1;
2125
Dinh Nguyen3da42852015-06-02 22:52:49 -05002126 /* add delay to bring centre of all DQ windows to the same "level" */
2127 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2128 /* Use values before divide by 2 to reduce round off error */
2129 shift_dq = (left_edge[i] - right_edge[i] -
2130 (left_edge[min_index] - right_edge[min_index]))/2 +
2131 (orig_mid_min - mid_min);
2132
2133 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2134 shift_dq[%u]=%d\n", i, shift_dq);
2135
Marek Vasut1273dd92015-07-12 21:05:08 +02002136 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
Marek Vasut17fdc912015-07-12 20:05:54 +02002137 temp_dq_in_delay1 = readl(addr + (p << 2));
2138 temp_dq_in_delay2 = readl(addr + (i << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05002139
2140 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2141 (int32_t)IO_IO_IN_DELAY_MAX) {
2142 shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2143 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2144 shift_dq = -(int32_t)temp_dq_in_delay1;
2145 }
2146 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2147 shift_dq[%u]=%d\n", i, shift_dq);
2148 final_dq[i] = temp_dq_in_delay1 + shift_dq;
Marek Vasut07aee5b2015-07-12 22:07:33 +02002149 scc_mgr_set_dq_in_delay(p, final_dq[i]);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002150 scc_mgr_load_dq(p);
2151
2152 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2153 left_edge[i] - shift_dq + (-mid_min),
2154 right_edge[i] + shift_dq - (-mid_min));
2155 /* To determine values for export structures */
2156 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2157 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2158
2159 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2160 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2161 }
2162
2163 final_dqs = new_dqs;
2164 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2165 final_dqs_en = start_dqs_en - mid_min;
2166
2167 /* Move DQS-en */
2168 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2169 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2170 scc_mgr_load_dqs(read_group);
2171 }
2172
2173 /* Move DQS */
2174 scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2175 scc_mgr_load_dqs(read_group);
2176 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2177 dqs_margin=%d", __func__, __LINE__,
2178 dq_margin, dqs_margin);
2179
2180 /*
2181 * Do not remove this line as it makes sure all of our decisions
2182 * have been applied. Apply the update bit.
2183 */
Marek Vasut1273dd92015-07-12 21:05:08 +02002184 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002185
2186 return (dq_margin >= 0) && (dqs_margin >= 0);
2187}
2188
Marek Vasutbce24ef2015-07-17 03:16:45 +02002189/**
2190 * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2191 * @rw_group: Read/Write Group
2192 * @test_bgn: Rank at which the test begins
Dinh Nguyen3da42852015-06-02 22:52:49 -05002193 *
Marek Vasutbce24ef2015-07-17 03:16:45 +02002194 * Stage 1: Calibrate the read valid prediction FIFO.
2195 *
2196 * This function implements UniPHY calibration Stage 1, as explained in
2197 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2198 *
2199 * - read valid prediction will consist of finding:
2200 * - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2201 * - DQS input phase and DQS input delay (DQ/DQS Centering)
Dinh Nguyen3da42852015-06-02 22:52:49 -05002202 * - we also do a per-bit deskew on the DQ lines.
2203 */
2204static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
2205 uint32_t test_bgn)
2206{
2207 uint32_t p, d, rank_bgn, sr;
2208 uint32_t dtaps_per_ptap;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002209 uint32_t bit_chk;
2210 uint32_t grp_calibrated;
2211 uint32_t write_group, write_test_bgn;
2212 uint32_t failed_substage;
2213
Marek Vasut7ac40d22015-06-26 18:56:54 +02002214 debug("%s:%d: %u %u\n", __func__, __LINE__, read_group, test_bgn);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002215
2216 /* update info for sims */
2217 reg_file_set_stage(CAL_STAGE_VFIFO);
2218
2219 write_group = read_group;
2220 write_test_bgn = test_bgn;
2221
2222 /* USER Determine number of delay taps for each phase tap */
Marek Vasutd32badb2015-07-17 03:11:06 +02002223 dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2224 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002225
2226 /* update info for sims */
2227 reg_file_set_group(read_group);
2228
2229 grp_calibrated = 0;
2230
2231 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2232 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2233
2234 for (d = 0; d <= dtaps_per_ptap && grp_calibrated == 0; d += 2) {
2235 /*
2236 * In RLDRAMX we may be messing the delay of pins in
2237 * the same write group but outside of the current read
2238 * the group, but that's ok because we haven't
2239 * calibrated output side yet.
2240 */
2241 if (d > 0) {
Marek Vasutf51a7d32015-07-19 02:18:21 +02002242 scc_mgr_apply_group_all_out_delay_add_all_ranks(
2243 write_group, d);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002244 }
2245
2246 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0;
2247 p++) {
2248 /* set a particular dqdqs phase */
2249 scc_mgr_set_dqdqs_output_phase_all_ranks(read_group, p);
2250
2251 debug_cond(DLEVEL == 1, "%s:%d calibrate_vfifo: g=%u \
2252 p=%u d=%u\n", __func__, __LINE__,
2253 read_group, p, d);
2254
2255 /*
2256 * Load up the patterns used by read calibration
2257 * using current DQDQS phase.
2258 */
2259 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2260 if (!(gbl->phy_debug_mode_flags &
2261 PHY_DEBUG_DISABLE_GUARANTEED_READ)) {
2262 if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks
2263 (read_group, 1, &bit_chk)) {
2264 debug_cond(DLEVEL == 1, "%s:%d Guaranteed read test failed:",
2265 __func__, __LINE__);
2266 debug_cond(DLEVEL == 1, " g=%u p=%u d=%u\n",
2267 read_group, p, d);
2268 break;
2269 }
2270 }
2271
2272/* case:56390 */
2273 grp_calibrated = 1;
2274 if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
2275 (write_group, read_group, test_bgn)) {
2276 /*
2277 * USER Read per-bit deskew can be done on a
2278 * per shadow register basis.
2279 */
2280 for (rank_bgn = 0, sr = 0;
2281 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2282 rank_bgn += NUM_RANKS_PER_SHADOW_REG,
2283 ++sr) {
2284 /*
2285 * Determine if this set of ranks
2286 * should be skipped entirely.
2287 */
2288 if (!param->skip_shadow_regs[sr]) {
2289 /*
2290 * If doing read after write
2291 * calibration, do not update
2292 * FOM, now - do it then.
2293 */
2294 if (!rw_mgr_mem_calibrate_vfifo_center
2295 (rank_bgn, write_group,
2296 read_group, test_bgn, 1, 0)) {
2297 grp_calibrated = 0;
2298 failed_substage =
2299 CAL_SUBSTAGE_VFIFO_CENTER;
2300 }
2301 }
2302 }
2303 } else {
2304 grp_calibrated = 0;
2305 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2306 }
2307 }
2308 }
2309
2310 if (grp_calibrated == 0) {
2311 set_failing_group_stage(write_group, CAL_STAGE_VFIFO,
2312 failed_substage);
2313 return 0;
2314 }
2315
2316 /*
2317 * Reset the delay chains back to zero if they have moved > 1
2318 * (check for > 1 because loop will increase d even when pass in
2319 * first case).
2320 */
2321 if (d > 2)
Marek Vasutd41ea932015-07-20 08:41:04 +02002322 scc_mgr_zero_group(write_group, 1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002323
2324 return 1;
2325}
2326
2327/* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2328static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2329 uint32_t test_bgn)
2330{
2331 uint32_t rank_bgn, sr;
2332 uint32_t grp_calibrated;
2333 uint32_t write_group;
2334
2335 debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2336
2337 /* update info for sims */
2338
2339 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2340 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2341
2342 write_group = read_group;
2343
2344 /* update info for sims */
2345 reg_file_set_group(read_group);
2346
2347 grp_calibrated = 1;
2348 /* Read per-bit deskew can be done on a per shadow register basis */
2349 for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2350 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2351 /* Determine if this set of ranks should be skipped entirely */
2352 if (!param->skip_shadow_regs[sr]) {
2353 /* This is the last calibration round, update FOM here */
2354 if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2355 write_group,
2356 read_group,
2357 test_bgn, 0,
2358 1)) {
2359 grp_calibrated = 0;
2360 }
2361 }
2362 }
2363
2364
2365 if (grp_calibrated == 0) {
2366 set_failing_group_stage(write_group,
2367 CAL_STAGE_VFIFO_AFTER_WRITES,
2368 CAL_SUBSTAGE_VFIFO_CENTER);
2369 return 0;
2370 }
2371
2372 return 1;
2373}
2374
2375/* Calibrate LFIFO to find smallest read latency */
2376static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2377{
2378 uint32_t found_one;
2379 uint32_t bit_chk;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002380
2381 debug("%s:%d\n", __func__, __LINE__);
2382
2383 /* update info for sims */
2384 reg_file_set_stage(CAL_STAGE_LFIFO);
2385 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2386
2387 /* Load up the patterns used by read calibration for all ranks */
2388 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2389 found_one = 0;
2390
Dinh Nguyen3da42852015-06-02 22:52:49 -05002391 do {
Marek Vasut1273dd92015-07-12 21:05:08 +02002392 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002393 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2394 __func__, __LINE__, gbl->curr_read_lat);
2395
2396 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2397 NUM_READ_TESTS,
2398 PASS_ALL_BITS,
2399 &bit_chk, 1)) {
2400 break;
2401 }
2402
2403 found_one = 1;
2404 /* reduce read latency and see if things are working */
2405 /* correctly */
2406 gbl->curr_read_lat--;
2407 } while (gbl->curr_read_lat > 0);
2408
2409 /* reset the fifos to get pointers to known state */
2410
Marek Vasut1273dd92015-07-12 21:05:08 +02002411 writel(0, &phy_mgr_cmd->fifo_reset);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002412
2413 if (found_one) {
2414 /* add a fudge factor to the read latency that was determined */
2415 gbl->curr_read_lat += 2;
Marek Vasut1273dd92015-07-12 21:05:08 +02002416 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002417 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2418 read_lat=%u\n", __func__, __LINE__,
2419 gbl->curr_read_lat);
2420 return 1;
2421 } else {
2422 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2423 CAL_SUBSTAGE_READ_LATENCY);
2424
2425 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2426 read_lat=%u\n", __func__, __LINE__,
2427 gbl->curr_read_lat);
2428 return 0;
2429 }
2430}
2431
2432/*
2433 * issue write test command.
2434 * two variants are provided. one that just tests a write pattern and
2435 * another that tests datamask functionality.
2436 */
2437static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2438 uint32_t test_dm)
2439{
2440 uint32_t mcc_instruction;
2441 uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2442 ENABLE_SUPER_QUICK_CALIBRATION);
2443 uint32_t rw_wl_nop_cycles;
2444 uint32_t addr;
2445
2446 /*
2447 * Set counter and jump addresses for the right
2448 * number of NOP cycles.
2449 * The number of supported NOP cycles can range from -1 to infinity
2450 * Three different cases are handled:
2451 *
2452 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2453 * mechanism will be used to insert the right number of NOPs
2454 *
2455 * 2. For a number of NOP cycles equals to 0, the micro-instruction
2456 * issuing the write command will jump straight to the
2457 * micro-instruction that turns on DQS (for DDRx), or outputs write
2458 * data (for RLD), skipping
2459 * the NOP micro-instruction all together
2460 *
2461 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2462 * turned on in the same micro-instruction that issues the write
2463 * command. Then we need
2464 * to directly jump to the micro-instruction that sends out the data
2465 *
2466 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2467 * (2 and 3). One jump-counter (0) is used to perform multiple
2468 * write-read operations.
2469 * one counter left to issue this command in "multiple-group" mode
2470 */
2471
2472 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2473
2474 if (rw_wl_nop_cycles == -1) {
2475 /*
2476 * CNTR 2 - We want to execute the special write operation that
2477 * turns on DQS right away and then skip directly to the
2478 * instruction that sends out the data. We set the counter to a
2479 * large number so that the jump is always taken.
2480 */
Marek Vasut1273dd92015-07-12 21:05:08 +02002481 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002482
2483 /* CNTR 3 - Not used */
2484 if (test_dm) {
2485 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002486 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
Marek Vasut1273dd92015-07-12 21:05:08 +02002487 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002488 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
Marek Vasut1273dd92015-07-12 21:05:08 +02002489 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002490 } else {
2491 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
Marek Vasut1273dd92015-07-12 21:05:08 +02002492 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2493 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2494 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2495 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002496 }
2497 } else if (rw_wl_nop_cycles == 0) {
2498 /*
2499 * CNTR 2 - We want to skip the NOP operation and go straight
2500 * to the DQS enable instruction. We set the counter to a large
2501 * number so that the jump is always taken.
2502 */
Marek Vasut1273dd92015-07-12 21:05:08 +02002503 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002504
2505 /* CNTR 3 - Not used */
2506 if (test_dm) {
2507 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002508 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
Marek Vasut1273dd92015-07-12 21:05:08 +02002509 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002510 } else {
2511 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
Marek Vasut1273dd92015-07-12 21:05:08 +02002512 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2513 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002514 }
2515 } else {
2516 /*
2517 * CNTR 2 - In this case we want to execute the next instruction
2518 * and NOT take the jump. So we set the counter to 0. The jump
2519 * address doesn't count.
2520 */
Marek Vasut1273dd92015-07-12 21:05:08 +02002521 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2522 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002523
2524 /*
2525 * CNTR 3 - Set the nop counter to the number of cycles we
2526 * need to loop for, minus 1.
2527 */
Marek Vasut1273dd92015-07-12 21:05:08 +02002528 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002529 if (test_dm) {
2530 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
Marek Vasut1273dd92015-07-12 21:05:08 +02002531 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2532 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002533 } else {
2534 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
Marek Vasut1273dd92015-07-12 21:05:08 +02002535 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2536 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002537 }
2538 }
2539
Marek Vasut1273dd92015-07-12 21:05:08 +02002540 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2541 RW_MGR_RESET_READ_DATAPATH_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002542
Dinh Nguyen3da42852015-06-02 22:52:49 -05002543 if (quick_write_mode)
Marek Vasut1273dd92015-07-12 21:05:08 +02002544 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002545 else
Marek Vasut1273dd92015-07-12 21:05:08 +02002546 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002547
Marek Vasut1273dd92015-07-12 21:05:08 +02002548 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002549
2550 /*
2551 * CNTR 1 - This is used to ensure enough time elapses
2552 * for read data to come back.
2553 */
Marek Vasut1273dd92015-07-12 21:05:08 +02002554 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002555
Dinh Nguyen3da42852015-06-02 22:52:49 -05002556 if (test_dm) {
Marek Vasut1273dd92015-07-12 21:05:08 +02002557 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2558 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002559 } else {
Marek Vasut1273dd92015-07-12 21:05:08 +02002560 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2561 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002562 }
2563
Marek Vasutc4815f72015-07-12 19:03:33 +02002564 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
Marek Vasut17fdc912015-07-12 20:05:54 +02002565 writel(mcc_instruction, addr + (group << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05002566}
2567
2568/* Test writes, can check for a single bit pass or multiple bit pass */
2569static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2570 uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2571 uint32_t *bit_chk, uint32_t all_ranks)
2572{
Dinh Nguyen3da42852015-06-02 22:52:49 -05002573 uint32_t r;
2574 uint32_t correct_mask_vg;
2575 uint32_t tmp_bit_chk;
2576 uint32_t vg;
2577 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2578 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2579 uint32_t addr_rw_mgr;
2580 uint32_t base_rw_mgr;
2581
2582 *bit_chk = param->write_correct_mask;
2583 correct_mask_vg = param->write_correct_mask_vg;
2584
2585 for (r = rank_bgn; r < rank_end; r++) {
2586 if (param->skip_ranks[r]) {
2587 /* request to skip the rank */
2588 continue;
2589 }
2590
2591 /* set rank */
2592 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2593
2594 tmp_bit_chk = 0;
Marek Vasuta4bfa462015-07-12 17:52:36 +02002595 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002596 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2597 /* reset the fifos to get pointers to known state */
Marek Vasut1273dd92015-07-12 21:05:08 +02002598 writel(0, &phy_mgr_cmd->fifo_reset);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002599
2600 tmp_bit_chk = tmp_bit_chk <<
2601 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2602 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2603 rw_mgr_mem_calibrate_write_test_issue(write_group *
2604 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2605 use_dm);
2606
Marek Vasut17fdc912015-07-12 20:05:54 +02002607 base_rw_mgr = readl(addr_rw_mgr);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002608 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2609 if (vg == 0)
2610 break;
2611 }
2612 *bit_chk &= tmp_bit_chk;
2613 }
2614
2615 if (all_correct) {
2616 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2617 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2618 %u => %lu", write_group, use_dm,
2619 *bit_chk, param->write_correct_mask,
2620 (long unsigned int)(*bit_chk ==
2621 param->write_correct_mask));
2622 return *bit_chk == param->write_correct_mask;
2623 } else {
2624 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2625 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2626 write_group, use_dm, *bit_chk);
2627 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2628 (long unsigned int)(*bit_chk != 0));
2629 return *bit_chk != 0x00;
2630 }
2631}
2632
2633/*
2634 * center all windows. do per-bit-deskew to possibly increase size of
2635 * certain windows.
2636 */
2637static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2638 uint32_t write_group, uint32_t test_bgn)
2639{
2640 uint32_t i, p, min_index;
2641 int32_t d;
2642 /*
2643 * Store these as signed since there are comparisons with
2644 * signed numbers.
2645 */
2646 uint32_t bit_chk;
2647 uint32_t sticky_bit_chk;
2648 int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2649 int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2650 int32_t mid;
2651 int32_t mid_min, orig_mid_min;
2652 int32_t new_dqs, start_dqs, shift_dq;
2653 int32_t dq_margin, dqs_margin, dm_margin;
2654 uint32_t stop;
2655 uint32_t temp_dq_out1_delay;
2656 uint32_t addr;
2657
2658 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2659
2660 dm_margin = 0;
2661
Marek Vasutc4815f72015-07-12 19:03:33 +02002662 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
Marek Vasut17fdc912015-07-12 20:05:54 +02002663 start_dqs = readl(addr +
Dinh Nguyen3da42852015-06-02 22:52:49 -05002664 (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2665
2666 /* per-bit deskew */
2667
2668 /*
2669 * set the left and right edge of each bit to an illegal value
2670 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2671 */
2672 sticky_bit_chk = 0;
2673 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2674 left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2675 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2676 }
2677
2678 /* Search for the left edge of the window for each bit */
Dinh Nguyen3da42852015-06-02 22:52:49 -05002679 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
Marek Vasut300c2e62015-07-17 05:42:49 +02002680 scc_mgr_apply_group_dq_out1_delay(write_group, d);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002681
Marek Vasut1273dd92015-07-12 21:05:08 +02002682 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002683
2684 /*
2685 * Stop searching when the read test doesn't pass AND when
2686 * we've seen a passing read on every bit.
2687 */
2688 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2689 0, PASS_ONE_BIT, &bit_chk, 0);
2690 sticky_bit_chk = sticky_bit_chk | bit_chk;
2691 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2692 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2693 == %u && %u [bit_chk= %u ]\n",
2694 d, sticky_bit_chk, param->write_correct_mask,
2695 stop, bit_chk);
2696
2697 if (stop == 1) {
2698 break;
2699 } else {
2700 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2701 if (bit_chk & 1) {
2702 /*
2703 * Remember a passing test as the
2704 * left_edge.
2705 */
2706 left_edge[i] = d;
2707 } else {
2708 /*
2709 * If a left edge has not been seen
2710 * yet, then a future passing test will
2711 * mark this edge as the right edge.
2712 */
2713 if (left_edge[i] ==
2714 IO_IO_OUT1_DELAY_MAX + 1) {
2715 right_edge[i] = -(d + 1);
2716 }
2717 }
2718 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2719 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2720 (int)(bit_chk & 1), i, left_edge[i]);
2721 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2722 right_edge[i]);
2723 bit_chk = bit_chk >> 1;
2724 }
2725 }
2726 }
2727
2728 /* Reset DQ delay chains to 0 */
Marek Vasut32675242015-07-17 06:07:13 +02002729 scc_mgr_apply_group_dq_out1_delay(0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002730 sticky_bit_chk = 0;
2731 for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2732 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2733 %d right_edge[%u]: %d\n", __func__, __LINE__,
2734 i, left_edge[i], i, right_edge[i]);
2735
2736 /*
2737 * Check for cases where we haven't found the left edge,
2738 * which makes our assignment of the the right edge invalid.
2739 * Reset it to the illegal value.
2740 */
2741 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2742 (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2743 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2744 debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2745 right_edge[%u]: %d\n", __func__, __LINE__,
2746 i, right_edge[i]);
2747 }
2748
2749 /*
2750 * Reset sticky bit (except for bits where we have
2751 * seen the left edge).
2752 */
2753 sticky_bit_chk = sticky_bit_chk << 1;
2754 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2755 sticky_bit_chk = sticky_bit_chk | 1;
2756
2757 if (i == 0)
2758 break;
2759 }
2760
2761 /* Search for the right edge of the window for each bit */
Dinh Nguyen3da42852015-06-02 22:52:49 -05002762 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2763 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2764 d + start_dqs);
2765
Marek Vasut1273dd92015-07-12 21:05:08 +02002766 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002767
2768 /*
2769 * Stop searching when the read test doesn't pass AND when
2770 * we've seen a passing read on every bit.
2771 */
2772 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2773 0, PASS_ONE_BIT, &bit_chk, 0);
2774
2775 sticky_bit_chk = sticky_bit_chk | bit_chk;
2776 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2777
2778 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2779 %u && %u\n", d, sticky_bit_chk,
2780 param->write_correct_mask, stop);
2781
2782 if (stop == 1) {
2783 if (d == 0) {
2784 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2785 i++) {
2786 /* d = 0 failed, but it passed when
2787 testing the left edge, so it must be
2788 marginal, set it to -1 */
2789 if (right_edge[i] ==
2790 IO_IO_OUT1_DELAY_MAX + 1 &&
2791 left_edge[i] !=
2792 IO_IO_OUT1_DELAY_MAX + 1) {
2793 right_edge[i] = -1;
2794 }
2795 }
2796 }
2797 break;
2798 } else {
2799 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2800 if (bit_chk & 1) {
2801 /*
2802 * Remember a passing test as
2803 * the right_edge.
2804 */
2805 right_edge[i] = d;
2806 } else {
2807 if (d != 0) {
2808 /*
2809 * If a right edge has not
2810 * been seen yet, then a future
2811 * passing test will mark this
2812 * edge as the left edge.
2813 */
2814 if (right_edge[i] ==
2815 IO_IO_OUT1_DELAY_MAX + 1)
2816 left_edge[i] = -(d + 1);
2817 } else {
2818 /*
2819 * d = 0 failed, but it passed
2820 * when testing the left edge,
2821 * so it must be marginal, set
2822 * it to -1.
2823 */
2824 if (right_edge[i] ==
2825 IO_IO_OUT1_DELAY_MAX + 1 &&
2826 left_edge[i] !=
2827 IO_IO_OUT1_DELAY_MAX + 1)
2828 right_edge[i] = -1;
2829 /*
2830 * If a right edge has not been
2831 * seen yet, then a future
2832 * passing test will mark this
2833 * edge as the left edge.
2834 */
2835 else if (right_edge[i] ==
2836 IO_IO_OUT1_DELAY_MAX +
2837 1)
2838 left_edge[i] = -(d + 1);
2839 }
2840 }
2841 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2842 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2843 (int)(bit_chk & 1), i, left_edge[i]);
2844 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2845 right_edge[i]);
2846 bit_chk = bit_chk >> 1;
2847 }
2848 }
2849 }
2850
2851 /* Check that all bits have a window */
2852 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2853 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2854 %d right_edge[%u]: %d", __func__, __LINE__,
2855 i, left_edge[i], i, right_edge[i]);
2856 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2857 (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2858 set_failing_group_stage(test_bgn + i,
2859 CAL_STAGE_WRITES,
2860 CAL_SUBSTAGE_WRITES_CENTER);
2861 return 0;
2862 }
2863 }
2864
2865 /* Find middle of window for each DQ bit */
2866 mid_min = left_edge[0] - right_edge[0];
2867 min_index = 0;
2868 for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2869 mid = left_edge[i] - right_edge[i];
2870 if (mid < mid_min) {
2871 mid_min = mid;
2872 min_index = i;
2873 }
2874 }
2875
2876 /*
2877 * -mid_min/2 represents the amount that we need to move DQS.
2878 * If mid_min is odd and positive we'll need to add one to
2879 * make sure the rounding in further calculations is correct
2880 * (always bias to the right), so just add 1 for all positive values.
2881 */
2882 if (mid_min > 0)
2883 mid_min++;
2884 mid_min = mid_min / 2;
2885 debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2886 __LINE__, mid_min);
2887
2888 /* Determine the amount we can change DQS (which is -mid_min) */
2889 orig_mid_min = mid_min;
2890 new_dqs = start_dqs;
2891 mid_min = 0;
2892 debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2893 mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2894 /* Initialize data for export structures */
2895 dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2896 dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
2897
2898 /* add delay to bring centre of all DQ windows to the same "level" */
Dinh Nguyen3da42852015-06-02 22:52:49 -05002899 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2900 /* Use values before divide by 2 to reduce round off error */
2901 shift_dq = (left_edge[i] - right_edge[i] -
2902 (left_edge[min_index] - right_edge[min_index]))/2 +
2903 (orig_mid_min - mid_min);
2904
2905 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2906 [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2907
Marek Vasut1273dd92015-07-12 21:05:08 +02002908 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
Marek Vasut17fdc912015-07-12 20:05:54 +02002909 temp_dq_out1_delay = readl(addr + (i << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05002910 if (shift_dq + (int32_t)temp_dq_out1_delay >
2911 (int32_t)IO_IO_OUT1_DELAY_MAX) {
2912 shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2913 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2914 shift_dq = -(int32_t)temp_dq_out1_delay;
2915 }
2916 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2917 i, shift_dq);
Marek Vasut07aee5b2015-07-12 22:07:33 +02002918 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002919 scc_mgr_load_dq(i);
2920
2921 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2922 left_edge[i] - shift_dq + (-mid_min),
2923 right_edge[i] + shift_dq - (-mid_min));
2924 /* To determine values for export structures */
2925 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2926 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2927
2928 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2929 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2930 }
2931
2932 /* Move DQS */
2933 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
Marek Vasut1273dd92015-07-12 21:05:08 +02002934 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002935
2936 /* Centre DM */
2937 debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
2938
2939 /*
2940 * set the left and right edge of each bit to an illegal value,
2941 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
2942 */
2943 left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2944 right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2945 int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2946 int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2947 int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
2948 int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
2949 int32_t win_best = 0;
2950
2951 /* Search for the/part of the window with DM shift */
Dinh Nguyen3da42852015-06-02 22:52:49 -05002952 for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
Marek Vasut32675242015-07-17 06:07:13 +02002953 scc_mgr_apply_group_dm_out1_delay(d);
Marek Vasut1273dd92015-07-12 21:05:08 +02002954 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002955
2956 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
2957 PASS_ALL_BITS, &bit_chk,
2958 0)) {
2959 /* USE Set current end of the window */
2960 end_curr = -d;
2961 /*
2962 * If a starting edge of our window has not been seen
2963 * this is our current start of the DM window.
2964 */
2965 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
2966 bgn_curr = -d;
2967
2968 /*
2969 * If current window is bigger than best seen.
2970 * Set best seen to be current window.
2971 */
2972 if ((end_curr-bgn_curr+1) > win_best) {
2973 win_best = end_curr-bgn_curr+1;
2974 bgn_best = bgn_curr;
2975 end_best = end_curr;
2976 }
2977 } else {
2978 /* We just saw a failing test. Reset temp edge */
2979 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2980 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2981 }
2982 }
2983
2984
2985 /* Reset DM delay chains to 0 */
Marek Vasut32675242015-07-17 06:07:13 +02002986 scc_mgr_apply_group_dm_out1_delay(0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002987
2988 /*
2989 * Check to see if the current window nudges up aganist 0 delay.
2990 * If so we need to continue the search by shifting DQS otherwise DQS
2991 * search begins as a new search. */
2992 if (end_curr != 0) {
2993 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2994 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2995 }
2996
2997 /* Search for the/part of the window with DQS shifts */
Dinh Nguyen3da42852015-06-02 22:52:49 -05002998 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
2999 /*
3000 * Note: This only shifts DQS, so are we limiting ourselve to
3001 * width of DQ unnecessarily.
3002 */
3003 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3004 d + new_dqs);
3005
Marek Vasut1273dd92015-07-12 21:05:08 +02003006 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003007 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3008 PASS_ALL_BITS, &bit_chk,
3009 0)) {
3010 /* USE Set current end of the window */
3011 end_curr = d;
3012 /*
3013 * If a beginning edge of our window has not been seen
3014 * this is our current begin of the DM window.
3015 */
3016 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3017 bgn_curr = d;
3018
3019 /*
3020 * If current window is bigger than best seen. Set best
3021 * seen to be current window.
3022 */
3023 if ((end_curr-bgn_curr+1) > win_best) {
3024 win_best = end_curr-bgn_curr+1;
3025 bgn_best = bgn_curr;
3026 end_best = end_curr;
3027 }
3028 } else {
3029 /* We just saw a failing test. Reset temp edge */
3030 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3031 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3032
3033 /* Early exit optimization: if ther remaining delay
3034 chain space is less than already seen largest window
3035 we can exit */
3036 if ((win_best-1) >
3037 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3038 break;
3039 }
3040 }
3041 }
3042
3043 /* assign left and right edge for cal and reporting; */
3044 left_edge[0] = -1*bgn_best;
3045 right_edge[0] = end_best;
3046
3047 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3048 __LINE__, left_edge[0], right_edge[0]);
3049
3050 /* Move DQS (back to orig) */
3051 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3052
3053 /* Move DM */
3054
3055 /* Find middle of window for the DM bit */
3056 mid = (left_edge[0] - right_edge[0]) / 2;
3057
3058 /* only move right, since we are not moving DQS/DQ */
3059 if (mid < 0)
3060 mid = 0;
3061
3062 /* dm_marign should fail if we never find a window */
3063 if (win_best == 0)
3064 dm_margin = -1;
3065 else
3066 dm_margin = left_edge[0] - mid;
3067
Marek Vasut32675242015-07-17 06:07:13 +02003068 scc_mgr_apply_group_dm_out1_delay(mid);
Marek Vasut1273dd92015-07-12 21:05:08 +02003069 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003070
3071 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3072 dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3073 right_edge[0], mid, dm_margin);
3074 /* Export values */
3075 gbl->fom_out += dq_margin + dqs_margin;
3076
3077 debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3078 dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3079 dq_margin, dqs_margin, dm_margin);
3080
3081 /*
3082 * Do not remove this line as it makes sure all of our
3083 * decisions have been applied.
3084 */
Marek Vasut1273dd92015-07-12 21:05:08 +02003085 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003086 return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3087}
3088
3089/* calibrate the write operations */
3090static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3091 uint32_t test_bgn)
3092{
3093 /* update info for sims */
3094 debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3095
3096 reg_file_set_stage(CAL_STAGE_WRITES);
3097 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3098
3099 reg_file_set_group(g);
3100
3101 if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3102 set_failing_group_stage(g, CAL_STAGE_WRITES,
3103 CAL_SUBSTAGE_WRITES_CENTER);
3104 return 0;
3105 }
3106
3107 return 1;
3108}
3109
Marek Vasut4b0ac262015-07-20 07:33:33 +02003110/**
3111 * mem_precharge_and_activate() - Precharge all banks and activate
3112 *
3113 * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3114 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003115static void mem_precharge_and_activate(void)
3116{
Marek Vasut4b0ac262015-07-20 07:33:33 +02003117 int r;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003118
3119 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
Marek Vasut4b0ac262015-07-20 07:33:33 +02003120 /* Test if the rank should be skipped. */
3121 if (param->skip_ranks[r])
Dinh Nguyen3da42852015-06-02 22:52:49 -05003122 continue;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003123
Marek Vasut4b0ac262015-07-20 07:33:33 +02003124 /* Set rank. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003125 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3126
Marek Vasut4b0ac262015-07-20 07:33:33 +02003127 /* Precharge all banks. */
Marek Vasut1273dd92015-07-12 21:05:08 +02003128 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3129 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003130
Marek Vasut1273dd92015-07-12 21:05:08 +02003131 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3132 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3133 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003134
Marek Vasut1273dd92015-07-12 21:05:08 +02003135 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3136 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3137 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003138
Marek Vasut4b0ac262015-07-20 07:33:33 +02003139 /* Activate rows. */
Marek Vasut1273dd92015-07-12 21:05:08 +02003140 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3141 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003142 }
3143}
3144
Marek Vasut16502a02015-07-17 01:57:41 +02003145/**
3146 * mem_init_latency() - Configure memory RLAT and WLAT settings
3147 *
3148 * Configure memory RLAT and WLAT parameters.
3149 */
3150static void mem_init_latency(void)
Dinh Nguyen3da42852015-06-02 22:52:49 -05003151{
Marek Vasut16502a02015-07-17 01:57:41 +02003152 /*
3153 * For AV/CV, LFIFO is hardened and always runs at full rate
3154 * so max latency in AFI clocks, used here, is correspondingly
3155 * smaller.
3156 */
3157 const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3158 u32 rlat, wlat;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003159
3160 debug("%s:%d\n", __func__, __LINE__);
Marek Vasut16502a02015-07-17 01:57:41 +02003161
3162 /*
3163 * Read in write latency.
3164 * WL for Hard PHY does not include additive latency.
3165 */
Marek Vasut1273dd92015-07-12 21:05:08 +02003166 wlat = readl(&data_mgr->t_wl_add);
3167 wlat += readl(&data_mgr->mem_t_add);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003168
Marek Vasut16502a02015-07-17 01:57:41 +02003169 gbl->rw_wl_nop_cycles = wlat - 1;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003170
Marek Vasut16502a02015-07-17 01:57:41 +02003171 /* Read in readl latency. */
Marek Vasut1273dd92015-07-12 21:05:08 +02003172 rlat = readl(&data_mgr->t_rl_add);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003173
Marek Vasut16502a02015-07-17 01:57:41 +02003174 /* Set a pretty high read latency initially. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003175 gbl->curr_read_lat = rlat + 16;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003176 if (gbl->curr_read_lat > max_latency)
3177 gbl->curr_read_lat = max_latency;
3178
Marek Vasut1273dd92015-07-12 21:05:08 +02003179 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003180
Marek Vasut16502a02015-07-17 01:57:41 +02003181 /* Advertise write latency. */
3182 writel(wlat, &phy_mgr_cfg->afi_wlat);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003183}
3184
Marek Vasut51cea0b2015-07-26 10:54:15 +02003185/**
3186 * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3187 *
3188 * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3189 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003190static void mem_skip_calibrate(void)
3191{
3192 uint32_t vfifo_offset;
3193 uint32_t i, j, r;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003194
3195 debug("%s:%d\n", __func__, __LINE__);
3196 /* Need to update every shadow register set used by the interface */
3197 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
Marek Vasut51cea0b2015-07-26 10:54:15 +02003198 r += NUM_RANKS_PER_SHADOW_REG) {
Dinh Nguyen3da42852015-06-02 22:52:49 -05003199 /*
3200 * Set output phase alignment settings appropriate for
3201 * skip calibration.
3202 */
3203 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3204 scc_mgr_set_dqs_en_phase(i, 0);
3205#if IO_DLL_CHAIN_LENGTH == 6
3206 scc_mgr_set_dqdqs_output_phase(i, 6);
3207#else
3208 scc_mgr_set_dqdqs_output_phase(i, 7);
3209#endif
3210 /*
3211 * Case:33398
3212 *
3213 * Write data arrives to the I/O two cycles before write
3214 * latency is reached (720 deg).
3215 * -> due to bit-slip in a/c bus
3216 * -> to allow board skew where dqs is longer than ck
3217 * -> how often can this happen!?
3218 * -> can claim back some ptaps for high freq
3219 * support if we can relax this, but i digress...
3220 *
3221 * The write_clk leads mem_ck by 90 deg
3222 * The minimum ptap of the OPA is 180 deg
3223 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3224 * The write_clk is always delayed by 2 ptaps
3225 *
3226 * Hence, to make DQS aligned to CK, we need to delay
3227 * DQS by:
3228 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3229 *
3230 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3231 * gives us the number of ptaps, which simplies to:
3232 *
3233 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3234 */
Marek Vasut51cea0b2015-07-26 10:54:15 +02003235 scc_mgr_set_dqdqs_output_phase(i,
3236 1.25 * IO_DLL_CHAIN_LENGTH - 2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003237 }
Marek Vasut1273dd92015-07-12 21:05:08 +02003238 writel(0xff, &sdr_scc_mgr->dqs_ena);
3239 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003240
Dinh Nguyen3da42852015-06-02 22:52:49 -05003241 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
Marek Vasut1273dd92015-07-12 21:05:08 +02003242 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3243 SCC_MGR_GROUP_COUNTER_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003244 }
Marek Vasut1273dd92015-07-12 21:05:08 +02003245 writel(0xff, &sdr_scc_mgr->dq_ena);
3246 writel(0xff, &sdr_scc_mgr->dm_ena);
3247 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003248 }
3249
3250 /* Compensate for simulation model behaviour */
3251 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3252 scc_mgr_set_dqs_bus_in_delay(i, 10);
3253 scc_mgr_load_dqs(i);
3254 }
Marek Vasut1273dd92015-07-12 21:05:08 +02003255 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003256
3257 /*
3258 * ArriaV has hard FIFOs that can only be initialized by incrementing
3259 * in sequencer.
3260 */
3261 vfifo_offset = CALIB_VFIFO_OFFSET;
Marek Vasut51cea0b2015-07-26 10:54:15 +02003262 for (j = 0; j < vfifo_offset; j++)
Marek Vasut1273dd92015-07-12 21:05:08 +02003263 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
Marek Vasut1273dd92015-07-12 21:05:08 +02003264 writel(0, &phy_mgr_cmd->fifo_reset);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003265
3266 /*
Marek Vasut51cea0b2015-07-26 10:54:15 +02003267 * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3268 * setting from generation-time constant.
Dinh Nguyen3da42852015-06-02 22:52:49 -05003269 */
3270 gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
Marek Vasut1273dd92015-07-12 21:05:08 +02003271 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003272}
3273
Marek Vasut3589fbf2015-07-20 04:34:51 +02003274/**
3275 * mem_calibrate() - Memory calibration entry point.
3276 *
3277 * Perform memory calibration.
3278 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003279static uint32_t mem_calibrate(void)
3280{
3281 uint32_t i;
3282 uint32_t rank_bgn, sr;
3283 uint32_t write_group, write_test_bgn;
3284 uint32_t read_group, read_test_bgn;
3285 uint32_t run_groups, current_run;
3286 uint32_t failing_groups = 0;
3287 uint32_t group_failed = 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003288
Marek Vasut33c42bb2015-07-17 02:21:47 +02003289 const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3290 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3291
Dinh Nguyen3da42852015-06-02 22:52:49 -05003292 debug("%s:%d\n", __func__, __LINE__);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003293
Marek Vasut16502a02015-07-17 01:57:41 +02003294 /* Initialize the data settings */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003295 gbl->error_substage = CAL_SUBSTAGE_NIL;
3296 gbl->error_stage = CAL_STAGE_NIL;
3297 gbl->error_group = 0xff;
3298 gbl->fom_in = 0;
3299 gbl->fom_out = 0;
3300
Marek Vasut16502a02015-07-17 01:57:41 +02003301 /* Initialize WLAT and RLAT. */
3302 mem_init_latency();
3303
3304 /* Initialize bit slips. */
3305 mem_precharge_and_activate();
Dinh Nguyen3da42852015-06-02 22:52:49 -05003306
Dinh Nguyen3da42852015-06-02 22:52:49 -05003307 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
Marek Vasut1273dd92015-07-12 21:05:08 +02003308 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3309 SCC_MGR_GROUP_COUNTER_OFFSET);
Marek Vasutfa5d8212015-07-19 01:34:43 +02003310 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3311 if (i == 0)
3312 scc_mgr_set_hhp_extras();
3313
Marek Vasutc5c5f532015-07-17 02:06:20 +02003314 scc_set_bypass_mode(i);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003315 }
3316
Marek Vasut722c9682015-07-17 02:07:12 +02003317 /* Calibration is skipped. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003318 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3319 /*
3320 * Set VFIFO and LFIFO to instant-on settings in skip
3321 * calibration mode.
3322 */
3323 mem_skip_calibrate();
Dinh Nguyen3da42852015-06-02 22:52:49 -05003324
Marek Vasut722c9682015-07-17 02:07:12 +02003325 /*
3326 * Do not remove this line as it makes sure all of our
3327 * decisions have been applied.
3328 */
3329 writel(0, &sdr_scc_mgr->update);
3330 return 1;
3331 }
Dinh Nguyen3da42852015-06-02 22:52:49 -05003332
Marek Vasut722c9682015-07-17 02:07:12 +02003333 /* Calibration is not skipped. */
3334 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3335 /*
3336 * Zero all delay chain/phase settings for all
3337 * groups and all shadow register sets.
3338 */
3339 scc_mgr_zero_all();
Dinh Nguyen3da42852015-06-02 22:52:49 -05003340
Marek Vasut722c9682015-07-17 02:07:12 +02003341 run_groups = ~param->skip_groups;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003342
Marek Vasut722c9682015-07-17 02:07:12 +02003343 for (write_group = 0, write_test_bgn = 0; write_group
3344 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3345 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
Marek Vasutc452dcd2015-07-17 02:50:56 +02003346
3347 /* Initialize the group failure */
Marek Vasut722c9682015-07-17 02:07:12 +02003348 group_failed = 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003349
Marek Vasut722c9682015-07-17 02:07:12 +02003350 current_run = run_groups & ((1 <<
3351 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3352 run_groups = run_groups >>
3353 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003354
Marek Vasut722c9682015-07-17 02:07:12 +02003355 if (current_run == 0)
3356 continue;
3357
3358 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3359 SCC_MGR_GROUP_COUNTER_OFFSET);
3360 scc_mgr_zero_group(write_group, 0);
3361
Marek Vasut33c42bb2015-07-17 02:21:47 +02003362 for (read_group = write_group * rwdqs_ratio,
3363 read_test_bgn = 0;
Marek Vasutc452dcd2015-07-17 02:50:56 +02003364 read_group < (write_group + 1) * rwdqs_ratio;
Marek Vasut33c42bb2015-07-17 02:21:47 +02003365 read_group++,
3366 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3367 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3368 continue;
Marek Vasut722c9682015-07-17 02:07:12 +02003369
Marek Vasut33c42bb2015-07-17 02:21:47 +02003370 /* Calibrate the VFIFO */
3371 if (rw_mgr_mem_calibrate_vfifo(read_group,
3372 read_test_bgn))
3373 continue;
3374
Marek Vasutc452dcd2015-07-17 02:50:56 +02003375 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3376 return 0;
3377
3378 /* The group failed, we're done. */
3379 goto grp_failed;
3380 }
3381
3382 /* Calibrate the output side */
3383 for (rank_bgn = 0, sr = 0;
3384 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3385 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3386 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3387 continue;
3388
3389 /* Not needed in quick mode! */
3390 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3391 continue;
3392
3393 /*
3394 * Determine if this set of ranks
3395 * should be skipped entirely.
3396 */
3397 if (param->skip_shadow_regs[sr])
3398 continue;
3399
3400 /* Calibrate WRITEs */
3401 if (rw_mgr_mem_calibrate_writes(rank_bgn,
3402 write_group, write_test_bgn))
3403 continue;
3404
Marek Vasut33c42bb2015-07-17 02:21:47 +02003405 group_failed = 1;
3406 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3407 return 0;
Marek Vasut722c9682015-07-17 02:07:12 +02003408 }
3409
Marek Vasutc452dcd2015-07-17 02:50:56 +02003410 /* Some group failed, we're done. */
3411 if (group_failed)
3412 goto grp_failed;
Marek Vasut4ac21612015-07-17 02:31:04 +02003413
Marek Vasutc452dcd2015-07-17 02:50:56 +02003414 for (read_group = write_group * rwdqs_ratio,
3415 read_test_bgn = 0;
3416 read_group < (write_group + 1) * rwdqs_ratio;
3417 read_group++,
3418 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3419 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3420 continue;
Marek Vasut4ac21612015-07-17 02:31:04 +02003421
Marek Vasutc452dcd2015-07-17 02:50:56 +02003422 if (rw_mgr_mem_calibrate_vfifo_end(read_group,
3423 read_test_bgn))
3424 continue;
Marek Vasut4ac21612015-07-17 02:31:04 +02003425
Marek Vasutc452dcd2015-07-17 02:50:56 +02003426 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3427 return 0;
Marek Vasut4ac21612015-07-17 02:31:04 +02003428
Marek Vasutc452dcd2015-07-17 02:50:56 +02003429 /* The group failed, we're done. */
3430 goto grp_failed;
Marek Vasut722c9682015-07-17 02:07:12 +02003431 }
3432
Marek Vasutc452dcd2015-07-17 02:50:56 +02003433 /* No group failed, continue as usual. */
3434 continue;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003435
Marek Vasutc452dcd2015-07-17 02:50:56 +02003436grp_failed: /* A group failed, increment the counter. */
3437 failing_groups++;
Marek Vasut722c9682015-07-17 02:07:12 +02003438 }
Dinh Nguyen3da42852015-06-02 22:52:49 -05003439
Marek Vasut722c9682015-07-17 02:07:12 +02003440 /*
3441 * USER If there are any failing groups then report
3442 * the failure.
3443 */
3444 if (failing_groups != 0)
3445 return 0;
3446
Marek Vasutc50ae302015-07-17 02:40:21 +02003447 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3448 continue;
3449
3450 /*
3451 * If we're skipping groups as part of debug,
3452 * don't calibrate LFIFO.
3453 */
3454 if (param->skip_groups != 0)
3455 continue;
3456
Marek Vasut722c9682015-07-17 02:07:12 +02003457 /* Calibrate the LFIFO */
Marek Vasutc50ae302015-07-17 02:40:21 +02003458 if (!rw_mgr_mem_calibrate_lfifo())
3459 return 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003460 }
3461
3462 /*
3463 * Do not remove this line as it makes sure all of our decisions
3464 * have been applied.
3465 */
Marek Vasut1273dd92015-07-12 21:05:08 +02003466 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003467 return 1;
3468}
3469
Marek Vasut23a040c2015-07-17 01:20:21 +02003470/**
3471 * run_mem_calibrate() - Perform memory calibration
3472 *
3473 * This function triggers the entire memory calibration procedure.
3474 */
3475static int run_mem_calibrate(void)
Dinh Nguyen3da42852015-06-02 22:52:49 -05003476{
Marek Vasut23a040c2015-07-17 01:20:21 +02003477 int pass;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003478
3479 debug("%s:%d\n", __func__, __LINE__);
3480
3481 /* Reset pass/fail status shown on afi_cal_success/fail */
Marek Vasut1273dd92015-07-12 21:05:08 +02003482 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003483
Marek Vasut23a040c2015-07-17 01:20:21 +02003484 /* Stop tracking manager. */
3485 clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003486
Marek Vasut9fa9c902015-07-17 01:12:07 +02003487 phy_mgr_initialize();
Dinh Nguyen3da42852015-06-02 22:52:49 -05003488 rw_mgr_mem_initialize();
3489
Marek Vasut23a040c2015-07-17 01:20:21 +02003490 /* Perform the actual memory calibration. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003491 pass = mem_calibrate();
3492
3493 mem_precharge_and_activate();
Marek Vasut1273dd92015-07-12 21:05:08 +02003494 writel(0, &phy_mgr_cmd->fifo_reset);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003495
Marek Vasut23a040c2015-07-17 01:20:21 +02003496 /* Handoff. */
3497 rw_mgr_mem_handoff();
Dinh Nguyen3da42852015-06-02 22:52:49 -05003498 /*
Marek Vasut23a040c2015-07-17 01:20:21 +02003499 * In Hard PHY this is a 2-bit control:
3500 * 0: AFI Mux Select
3501 * 1: DDIO Mux Select
Dinh Nguyen3da42852015-06-02 22:52:49 -05003502 */
Marek Vasut23a040c2015-07-17 01:20:21 +02003503 writel(0x2, &phy_mgr_cfg->mux_sel);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003504
Marek Vasut23a040c2015-07-17 01:20:21 +02003505 /* Start tracking manager. */
3506 setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3507
3508 return pass;
3509}
3510
3511/**
3512 * debug_mem_calibrate() - Report result of memory calibration
3513 * @pass: Value indicating whether calibration passed or failed
3514 *
3515 * This function reports the results of the memory calibration
3516 * and writes debug information into the register file.
3517 */
3518static void debug_mem_calibrate(int pass)
3519{
3520 uint32_t debug_info;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003521
3522 if (pass) {
3523 printf("%s: CALIBRATION PASSED\n", __FILE__);
3524
3525 gbl->fom_in /= 2;
3526 gbl->fom_out /= 2;
3527
3528 if (gbl->fom_in > 0xff)
3529 gbl->fom_in = 0xff;
3530
3531 if (gbl->fom_out > 0xff)
3532 gbl->fom_out = 0xff;
3533
3534 /* Update the FOM in the register file */
3535 debug_info = gbl->fom_in;
3536 debug_info |= gbl->fom_out << 8;
Marek Vasut1273dd92015-07-12 21:05:08 +02003537 writel(debug_info, &sdr_reg_file->fom);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003538
Marek Vasut1273dd92015-07-12 21:05:08 +02003539 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3540 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003541 } else {
3542 printf("%s: CALIBRATION FAILED\n", __FILE__);
3543
3544 debug_info = gbl->error_stage;
3545 debug_info |= gbl->error_substage << 8;
3546 debug_info |= gbl->error_group << 16;
3547
Marek Vasut1273dd92015-07-12 21:05:08 +02003548 writel(debug_info, &sdr_reg_file->failing_stage);
3549 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3550 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003551
3552 /* Update the failing group/stage in the register file */
3553 debug_info = gbl->error_stage;
3554 debug_info |= gbl->error_substage << 8;
3555 debug_info |= gbl->error_group << 16;
Marek Vasut1273dd92015-07-12 21:05:08 +02003556 writel(debug_info, &sdr_reg_file->failing_stage);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003557 }
3558
Marek Vasut23a040c2015-07-17 01:20:21 +02003559 printf("%s: Calibration complete\n", __FILE__);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003560}
3561
Marek Vasutbb064342015-07-19 06:12:42 +02003562/**
3563 * hc_initialize_rom_data() - Initialize ROM data
3564 *
3565 * Initialize ROM data.
3566 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003567static void hc_initialize_rom_data(void)
3568{
Marek Vasutbb064342015-07-19 06:12:42 +02003569 u32 i, addr;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003570
Marek Vasutc4815f72015-07-12 19:03:33 +02003571 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
Marek Vasutbb064342015-07-19 06:12:42 +02003572 for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3573 writel(inst_rom_init[i], addr + (i << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05003574
Marek Vasutc4815f72015-07-12 19:03:33 +02003575 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
Marek Vasutbb064342015-07-19 06:12:42 +02003576 for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3577 writel(ac_rom_init[i], addr + (i << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05003578}
3579
Marek Vasut9c1ab2c2015-07-19 06:13:37 +02003580/**
3581 * initialize_reg_file() - Initialize SDR register file
3582 *
3583 * Initialize SDR register file.
3584 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003585static void initialize_reg_file(void)
3586{
Dinh Nguyen3da42852015-06-02 22:52:49 -05003587 /* Initialize the register file with the correct data */
Marek Vasut1273dd92015-07-12 21:05:08 +02003588 writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3589 writel(0, &sdr_reg_file->debug_data_addr);
3590 writel(0, &sdr_reg_file->cur_stage);
3591 writel(0, &sdr_reg_file->fom);
3592 writel(0, &sdr_reg_file->failing_stage);
3593 writel(0, &sdr_reg_file->debug1);
3594 writel(0, &sdr_reg_file->debug2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003595}
3596
Marek Vasut2ca151f2015-07-19 06:14:04 +02003597/**
3598 * initialize_hps_phy() - Initialize HPS PHY
3599 *
3600 * Initialize HPS PHY.
3601 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003602static void initialize_hps_phy(void)
3603{
3604 uint32_t reg;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003605 /*
3606 * Tracking also gets configured here because it's in the
3607 * same register.
3608 */
3609 uint32_t trk_sample_count = 7500;
3610 uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3611 /*
3612 * Format is number of outer loops in the 16 MSB, sample
3613 * count in 16 LSB.
3614 */
3615
3616 reg = 0;
3617 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3618 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3619 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3620 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3621 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3622 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3623 /*
3624 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3625 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3626 */
3627 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3628 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3629 trk_sample_count);
Marek Vasut6cb9f162015-07-12 20:49:39 +02003630 writel(reg, &sdr_ctrl->phy_ctrl0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003631
3632 reg = 0;
3633 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3634 trk_sample_count >>
3635 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3636 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3637 trk_long_idle_sample_count);
Marek Vasut6cb9f162015-07-12 20:49:39 +02003638 writel(reg, &sdr_ctrl->phy_ctrl1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003639
3640 reg = 0;
3641 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3642 trk_long_idle_sample_count >>
3643 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
Marek Vasut6cb9f162015-07-12 20:49:39 +02003644 writel(reg, &sdr_ctrl->phy_ctrl2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003645}
3646
Marek Vasut880e46f2015-07-17 00:45:11 +02003647/**
3648 * initialize_tracking() - Initialize tracking
3649 *
3650 * Initialize the register file with usable initial data.
3651 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003652static void initialize_tracking(void)
3653{
Marek Vasut880e46f2015-07-17 00:45:11 +02003654 /*
3655 * Initialize the register file with the correct data.
3656 * Compute usable version of value in case we skip full
3657 * computation later.
3658 */
3659 writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3660 &sdr_reg_file->dtaps_per_ptap);
3661
3662 /* trk_sample_count */
3663 writel(7500, &sdr_reg_file->trk_sample_count);
3664
3665 /* longidle outer loop [15:0] */
3666 writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003667
3668 /*
Marek Vasut880e46f2015-07-17 00:45:11 +02003669 * longidle sample count [31:24]
3670 * trfc, worst case of 933Mhz 4Gb [23:16]
3671 * trcd, worst case [15:8]
3672 * vfifo wait [7:0]
Dinh Nguyen3da42852015-06-02 22:52:49 -05003673 */
Marek Vasut880e46f2015-07-17 00:45:11 +02003674 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3675 &sdr_reg_file->delays);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003676
Marek Vasut880e46f2015-07-17 00:45:11 +02003677 /* mux delay */
3678 writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3679 (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3680 &sdr_reg_file->trk_rw_mgr_addr);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003681
Marek Vasut880e46f2015-07-17 00:45:11 +02003682 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3683 &sdr_reg_file->trk_read_dqs_width);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003684
Marek Vasut880e46f2015-07-17 00:45:11 +02003685 /* trefi [7:0] */
3686 writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3687 &sdr_reg_file->trk_rfsh);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003688}
3689
3690int sdram_calibration_full(void)
3691{
3692 struct param_type my_param;
3693 struct gbl_type my_gbl;
3694 uint32_t pass;
Marek Vasut84e0b0c2015-07-17 01:05:36 +02003695
3696 memset(&my_param, 0, sizeof(my_param));
3697 memset(&my_gbl, 0, sizeof(my_gbl));
Dinh Nguyen3da42852015-06-02 22:52:49 -05003698
3699 param = &my_param;
3700 gbl = &my_gbl;
3701
Dinh Nguyen3da42852015-06-02 22:52:49 -05003702 /* Set the calibration enabled by default */
3703 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3704 /*
3705 * Only sweep all groups (regardless of fail state) by default
3706 * Set enabled read test by default.
3707 */
3708#if DISABLE_GUARANTEED_READ
3709 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3710#endif
3711 /* Initialize the register file */
3712 initialize_reg_file();
3713
3714 /* Initialize any PHY CSR */
3715 initialize_hps_phy();
3716
3717 scc_mgr_initialize();
3718
3719 initialize_tracking();
3720
Dinh Nguyen3da42852015-06-02 22:52:49 -05003721 printf("%s: Preparing to start memory calibration\n", __FILE__);
3722
3723 debug("%s:%d\n", __func__, __LINE__);
Marek Vasut23f62b32015-07-13 01:05:27 +02003724 debug_cond(DLEVEL == 1,
3725 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3726 RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3727 RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3728 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3729 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3730 debug_cond(DLEVEL == 1,
3731 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3732 RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3733 RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3734 IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3735 debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3736 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3737 debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3738 IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3739 IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3740 debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3741 IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3742 IO_IO_OUT2_DELAY_MAX);
3743 debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3744 IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003745
3746 hc_initialize_rom_data();
3747
3748 /* update info for sims */
3749 reg_file_set_stage(CAL_STAGE_NIL);
3750 reg_file_set_group(0);
3751
3752 /*
3753 * Load global needed for those actions that require
3754 * some dynamic calibration support.
3755 */
3756 dyn_calib_steps = STATIC_CALIB_STEPS;
3757 /*
3758 * Load global to allow dynamic selection of delay loop settings
3759 * based on calibration mode.
3760 */
3761 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3762 skip_delay_mask = 0xff;
3763 else
3764 skip_delay_mask = 0x0;
3765
3766 pass = run_mem_calibrate();
Marek Vasut23a040c2015-07-17 01:20:21 +02003767 debug_mem_calibrate(pass);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003768 return pass;
3769}