blob: c53bdce0ceb0cb1247f23f36aba0dd84575e0912 [file] [log] [blame]
Tom Rini855ff8e2018-05-18 17:54:39 -04001// SPDX-License-Identifier: GPL-2.0+
Jagan Teki1494cc82018-05-07 11:21:34 +05302/*
3 * Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it>
4 * Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it>
5 * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki1494cc82018-05-07 11:21:34 +05306 */
7
8#include <common.h>
9#include <spl.h>
10
11#include <asm/io.h>
12#include <linux/sizes.h>
13
14#include <asm/arch/clock.h>
15#include <asm/arch/crm_regs.h>
16#include <asm/arch/iomux.h>
17#include <asm/arch/mx6-ddr.h>
18#include <asm/arch/mx6-pins.h>
19#include <asm/arch/sys_proto.h>
20
21DECLARE_GLOBAL_DATA_PTR;
22
23#define IMX6SDL_DRIVE_STRENGTH 0x28
24#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
25 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
26
27static iomux_v3_cfg_t const uart3_pads[] = {
28 IOMUX_PADS(PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
29 IOMUX_PADS(PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
30};
31
Jagan Teki9e759ce2018-05-07 11:21:39 +053032#ifdef CONFIG_SPL_OS_BOOT
33int spl_start_uboot(void)
34{
35 /* break into full u-boot on 'c' */
36 if (serial_tstc() && serial_getc() == 'c')
37 return 1;
38
39 return 0;
40}
41#endif
42
Jagan Teki1494cc82018-05-07 11:21:34 +053043struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
44 .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
45 .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
46 .dram_cas = IMX6SDL_DRIVE_STRENGTH,
47 .dram_ras = IMX6SDL_DRIVE_STRENGTH,
48 .dram_reset = IMX6SDL_DRIVE_STRENGTH,
49 .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
50 .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
51 .dram_sdba2 = 0x00000000,
52 .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
53 .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
54 .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
55 .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
56 .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
57 .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
58 .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
59 .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
60 .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
61 .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
62 .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
63 .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
64 .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
65 .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
66 .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
67 .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
68 .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
69 .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
70};
71
72struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
73 .grp_ddr_type = 0x000c0000,
74 .grp_ddrmode_ctl = 0x00020000,
75 .grp_ddrpke = 0x00000000,
76 .grp_addds = IMX6SDL_DRIVE_STRENGTH,
77 .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
78 .grp_ddrmode = 0x00020000,
79 .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
80 .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
81 .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
82 .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
83 .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
84 .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
85 .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
86 .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
87};
88
89static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
90 .mem_speed = 1600,
91 .density = 4,
92 .width = 32,
93 .banks = 8,
94 .rowaddr = 14,
95 .coladdr = 10,
96 .pagesz = 2,
97 .trcd = 1375,
98 .trcmin = 4875,
99 .trasmin = 3500,
100 .SRT = 0,
101};
102
103static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
104 .p0_mpwldectrl0 = 0x0042004b,
105 .p0_mpwldectrl1 = 0x0038003c,
106 .p0_mpdgctrl0 = 0x42340230,
107 .p0_mpdgctrl1 = 0x0228022c,
108 .p0_mprddlctl = 0x42444646,
109 .p0_mpwrdlctl = 0x38382e2e,
110};
111
112static struct mx6_ddr_sysinfo mem_dl = {
113 .dsize = 1,
114 .cs1_mirror = 0,
115 /* config for full 4GB range so that get_mem_size() works */
116 .cs_density = 32,
117 .ncs = 1,
118 .bi_on = 1,
119 .rtt_nom = 1,
120 .rtt_wr = 1,
121 .ralat = 5,
122 .walat = 0,
123 .mif3_mode = 3,
124 .rst_to_cke = 0x23,
125 .sde_to_rst = 0x10,
126 .refsel = 1,
127 .refr = 7,
128};
129
130static void spl_dram_init(void)
131{
132 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
133 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41k128m16jt_125);
134
135 udelay(100);
136}
137
138static void ccgr_init(void)
139{
140 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
141
142 writel(0x00003f3f, &ccm->CCGR0);
143 writel(0x0030fc00, &ccm->CCGR1);
144 writel(0x000fc000, &ccm->CCGR2);
145 writel(0x3f300000, &ccm->CCGR3);
146 writel(0xff00f300, &ccm->CCGR4);
147 writel(0x0f0000c3, &ccm->CCGR5);
148 writel(0x000003cc, &ccm->CCGR6);
149}
150
151void board_init_f(ulong dummy)
152{
153 ccgr_init();
154
155 /* setup AIPS and disable watchdog */
156 arch_cpu_init();
157
158 gpr_init();
159
160 /* iomux */
161 SETUP_IOMUX_PADS(uart3_pads);
162
163 /* setup GP timer */
164 timer_init();
165
166 /* UART clocks enabled and gd valid - init serial console */
167 preloader_console_init();
168
169 /* DDR initialization */
170 spl_dram_init();
171}