| Vagrant Cascadian | 59a1df0 | 2019-04-29 16:12:29 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ |
| 4 | * |
| 5 | * Author: Robert Nelson <robertcnelson@gmail.com> |
| 6 | */ |
| 7 | |
| 8 | / { |
| 9 | cpus { |
| 10 | cpu@0 { |
| 11 | cpu0-supply = <&dcdc2_reg>; |
| 12 | }; |
| 13 | }; |
| 14 | |
| 15 | memory@80000000 { |
| 16 | device_type = "memory"; |
| 17 | reg = <0x80000000 0x20000000>; /* 512 MB */ |
| 18 | }; |
| 19 | }; |
| 20 | |
| 21 | &cpu0_opp_table { |
| 22 | /* |
| 23 | * Octavo Systems: |
| 24 | * The EFUSE_SMA register is not programmed for any of the AM335x wafers |
| 25 | * we get and we are not programming them during our production test. |
| 26 | * Therefore, from a DEVICE_ID revision point of view, the silicon looks |
| 27 | * like it is Revision 2.1. However, from an EFUSE_SMA point of view for |
| 28 | * the HW OPP table, the silicon looks like it is Revision 1.0 (ie the |
| 29 | * EFUSE_SMA register reads as all zeros). |
| 30 | */ |
| 31 | oppnitro-1000000000 { |
| 32 | opp-supported-hw = <0x06 0x0100>; |
| 33 | }; |
| 34 | }; |
| 35 | |
| 36 | &am33xx_pinmux { |
| 37 | i2c0_pins: pinmux-i2c0-pins { |
| 38 | pinctrl-single,pins = < |
| 39 | AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */ |
| 40 | AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */ |
| 41 | >; |
| 42 | }; |
| 43 | }; |
| 44 | |
| 45 | &i2c0 { |
| 46 | pinctrl-names = "default"; |
| 47 | pinctrl-0 = <&i2c0_pins>; |
| 48 | |
| 49 | status = "okay"; |
| 50 | clock-frequency = <400000>; |
| 51 | |
| 52 | tps: tps@24 { |
| 53 | reg = <0x24>; |
| 54 | }; |
| 55 | }; |
| 56 | |
| 57 | /include/ "tps65217.dtsi" |
| 58 | |
| 59 | &tps { |
| 60 | interrupts = <7>; /* NMI */ |
| 61 | interrupt-parent = <&intc>; |
| 62 | |
| 63 | ti,pmic-shutdown-controller; |
| 64 | |
| 65 | pwrbutton { |
| 66 | interrupts = <2>; |
| 67 | status = "okay"; |
| 68 | }; |
| 69 | |
| 70 | regulators { |
| 71 | dcdc1_reg: regulator@0 { |
| 72 | regulator-name = "vdds_dpr"; |
| 73 | regulator-always-on; |
| 74 | }; |
| 75 | |
| 76 | dcdc2_reg: regulator@1 { |
| 77 | /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ |
| 78 | regulator-name = "vdd_mpu"; |
| 79 | regulator-min-microvolt = <925000>; |
| 80 | regulator-max-microvolt = <1351500>; |
| 81 | regulator-boot-on; |
| 82 | regulator-always-on; |
| 83 | }; |
| 84 | |
| 85 | dcdc3_reg: regulator@2 { |
| 86 | /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ |
| 87 | regulator-name = "vdd_core"; |
| 88 | regulator-min-microvolt = <925000>; |
| 89 | regulator-max-microvolt = <1150000>; |
| 90 | regulator-boot-on; |
| 91 | regulator-always-on; |
| 92 | }; |
| 93 | |
| 94 | ldo1_reg: regulator@3 { |
| 95 | regulator-name = "vio,vrtc,vdds"; |
| 96 | regulator-always-on; |
| 97 | }; |
| 98 | |
| 99 | ldo2_reg: regulator@4 { |
| 100 | regulator-name = "vdd_3v3aux"; |
| 101 | regulator-always-on; |
| 102 | }; |
| 103 | |
| 104 | ldo3_reg: regulator@5 { |
| 105 | regulator-name = "vdd_1v8"; |
| 106 | regulator-min-microvolt = <1800000>; |
| 107 | regulator-max-microvolt = <1800000>; |
| 108 | regulator-always-on; |
| 109 | }; |
| 110 | |
| 111 | ldo4_reg: regulator@6 { |
| 112 | regulator-name = "vdd_3v3a"; |
| 113 | regulator-always-on; |
| 114 | }; |
| 115 | }; |
| 116 | }; |
| 117 | |
| 118 | &aes { |
| 119 | status = "okay"; |
| 120 | }; |
| 121 | |
| 122 | &sham { |
| 123 | status = "okay"; |
| 124 | }; |
| Dario Binacchi | 62af440 | 2021-06-02 22:38:03 +0200 | [diff] [blame] | 125 | |
| 126 | &rtc { |
| 127 | clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; |
| 128 | clock-names = "ext-clk", "int-clk"; |
| 129 | system-power-controller; |
| 130 | }; |