| Mike Frysinger | d9a5d11 | 2008-10-12 20:59:12 -0400 | [diff] [blame] | 1 | /* |
| 2 | * U-boot - Configuration file for BF537 STAMP board |
| 3 | */ |
| 4 | |
| 5 | #ifndef __CONFIG_BF527_EZKIT_H__ |
| 6 | #define __CONFIG_BF527_EZKIT_H__ |
| 7 | |
| 8 | #include <asm/blackfin-config-pre.h> |
| 9 | |
| 10 | |
| 11 | /* |
| 12 | * Processor Settings |
| 13 | */ |
| 14 | #define CONFIG_BFIN_CPU bf527-0.0 |
| 15 | #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA |
| 16 | |
| 17 | |
| 18 | /* |
| 19 | * Clock Settings |
| 20 | * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV |
| 21 | * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV |
| 22 | */ |
| 23 | /* CONFIG_CLKIN_HZ is any value in Hz */ |
| 24 | #define CONFIG_CLKIN_HZ 25000000 |
| 25 | /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ |
| 26 | /* 1 = CLKIN / 2 */ |
| 27 | #define CONFIG_CLKIN_HALF 0 |
| 28 | /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ |
| 29 | /* 1 = bypass PLL */ |
| 30 | #define CONFIG_PLL_BYPASS 0 |
| 31 | /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ |
| 32 | /* Values can range from 0-63 (where 0 means 64) */ |
| 33 | #define CONFIG_VCO_MULT 21 |
| 34 | /* CCLK_DIV controls the core clock divider */ |
| 35 | /* Values can be 1, 2, 4, or 8 ONLY */ |
| 36 | #define CONFIG_CCLK_DIV 1 |
| 37 | /* SCLK_DIV controls the system clock divider */ |
| 38 | /* Values can range from 1-15 */ |
| 39 | #define CONFIG_SCLK_DIV 4 |
| 40 | |
| 41 | |
| 42 | /* |
| 43 | * Memory Settings |
| 44 | */ |
| 45 | #define CONFIG_MEM_ADD_WDTH 10 |
| 46 | #define CONFIG_MEM_SIZE 64 |
| 47 | |
| 48 | #define CONFIG_EBIU_SDRRC_VAL 0x03F6 |
| 49 | #define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS) |
| 50 | |
| 51 | #define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) |
| 52 | #define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) |
| 53 | #define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) |
| 54 | |
| 55 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| 56 | #define CONFIG_SYS_MALLOC_LEN (640 * 1024) |
| 57 | |
| 58 | |
| 59 | /* |
| 60 | * NAND Settings |
| 61 | * (can't be used same time as ethernet) |
| 62 | */ |
| 63 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) |
| 64 | #define CONFIG_BFIN_NFC |
| 65 | #endif |
| 66 | #ifdef CONFIG_BFIN_NFC |
| 67 | #define CONFIG_BFIN_NFC_CTL_VAL 0x0033 |
| 68 | #define CONFIG_DRIVER_NAND_BFIN |
| 69 | #define CONFIG_SYS_NAND_BASE 0 /* not actually used */ |
| 70 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 71 | #define NAND_MAX_CHIPS 1 |
| 72 | #define CONFIG_CMD_NAND |
| 73 | #endif |
| 74 | |
| 75 | |
| 76 | /* |
| 77 | * Network Settings |
| 78 | */ |
| 79 | #if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \ |
| 80 | !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC) |
| 81 | #define ADI_CMDS_NETWORK 1 |
| 82 | #define CONFIG_BFIN_MAC |
| 83 | #define CONFIG_RMII |
| 84 | #define CONFIG_NETCONSOLE 1 |
| 85 | #define CONFIG_NET_MULTI 1 |
| 86 | #endif |
| 87 | #define CONFIG_HOSTNAME bf527-ezkit |
| 88 | /* Uncomment next line to use fixed MAC address */ |
| 89 | /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ |
| 90 | |
| 91 | |
| 92 | /* |
| 93 | * Flash Settings |
| 94 | */ |
| 95 | #define CONFIG_FLASH_CFI_DRIVER |
| 96 | #define CONFIG_SYS_FLASH_BASE 0x20000000 |
| 97 | #define CONFIG_SYS_FLASH_CFI |
| 98 | #define CONFIG_SYS_FLASH_PROTECTION |
| 99 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 100 | #define CONFIG_SYS_MAX_FLASH_SECT 259 |
| 101 | |
| 102 | |
| 103 | /* |
| 104 | * SPI Settings |
| 105 | */ |
| 106 | #define CONFIG_BFIN_SPI |
| 107 | #define CONFIG_ENV_SPI_MAX_HZ 30000000 |
| 108 | #define CONFIG_SF_DEFAULT_HZ 30000000 |
| 109 | #define CONFIG_SPI_FLASH |
| 110 | #define CONFIG_SPI_FLASH_STMICRO |
| 111 | |
| 112 | |
| 113 | /* |
| 114 | * Env Storage Settings |
| 115 | */ |
| 116 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) |
| 117 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 118 | #define CONFIG_ENV_OFFSET 0x4000 |
| 119 | #define CONFIG_ENV_SIZE 0x2000 |
| 120 | #define CONFIG_ENV_SECT_SIZE 0x2000 |
| 121 | #else |
| 122 | #define CONFIG_ENV_IS_IN_FLASH |
| 123 | #define CONFIG_ENV_OFFSET 0x4000 |
| 124 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) |
| 125 | #define CONFIG_ENV_SIZE 0x2000 |
| 126 | #define CONFIG_ENV_SECT_SIZE 0x2000 |
| 127 | #endif |
| 128 | #define ENV_IS_EMBEDDED_CUSTOM |
| 129 | |
| 130 | |
| 131 | /* |
| 132 | * I2C Settings |
| 133 | */ |
| 134 | #define CONFIG_BFIN_TWI_I2C 1 |
| 135 | #define CONFIG_HARD_I2C 1 |
| 136 | #define CONFIG_SYS_I2C_SPEED 50000 |
| 137 | #define CONFIG_SYS_I2C_SLAVE 0 |
| 138 | |
| 139 | |
| 140 | /* |
| 141 | * USB Settings |
| 142 | */ |
| 143 | #if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) |
| 144 | #define CONFIG_USB |
| 145 | #define CONFIG_MUSB_HCD |
| 146 | #define CONFIG_USB_BLACKFIN |
| 147 | #define CONFIG_USB_STORAGE |
| 148 | #define CONFIG_MUSB_TIMEOUT 100000 |
| 149 | #endif |
| 150 | |
| 151 | |
| 152 | /* |
| 153 | * Misc Settings |
| 154 | */ |
| 155 | #define CONFIG_MISC_INIT_R |
| 156 | #define CONFIG_RTC_BFIN |
| 157 | #define CONFIG_UART_CONSOLE 1 |
| 158 | |
| 159 | /* Don't waste time transferring a logo over the UART */ |
| 160 | #if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART) |
| 161 | # define CONFIG_VIDEO |
| 162 | #endif |
| 163 | |
| 164 | |
| 165 | /* |
| 166 | * Pull in common ADI header for remaining command/environment setup |
| 167 | */ |
| 168 | #include <configs/bfin_adi_common.h> |
| 169 | |
| 170 | #include <asm/blackfin-config-post.h> |
| 171 | |
| 172 | #endif |