Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2009 |
| 3 | * Marvell Semiconductor <www.marvell.com> |
| 4 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
| 5 | * |
| 6 | * (C) Copyright 2003 |
| 7 | * Ingo Assmus <ingo.assmus@keymile.com> |
| 8 | * |
| 9 | * based on - Driver for MV64360X ethernet ports |
| 10 | * Copyright (C) 2002 rabeeh@galileo.co.il |
| 11 | * |
| 12 | * See file CREDITS for list of people who contributed to this |
| 13 | * project. |
| 14 | * |
| 15 | * This program is free software; you can redistribute it and/or |
| 16 | * modify it under the terms of the GNU General Public License as |
| 17 | * published by the Free Software Foundation; either version 2 of |
| 18 | * the License, or (at your option) any later version. |
| 19 | * |
| 20 | * This program is distributed in the hope that it will be useful, |
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 23 | * GNU General Public License for more details. |
| 24 | * |
| 25 | * You should have received a copy of the GNU General Public License |
| 26 | * along with this program; if not, write to the Free Software |
| 27 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
| 28 | * MA 02110-1301 USA |
| 29 | */ |
| 30 | |
| 31 | #include <common.h> |
| 32 | #include <net.h> |
| 33 | #include <malloc.h> |
| 34 | #include <miiphy.h> |
| 35 | #include <asm/errno.h> |
| 36 | #include <asm/types.h> |
| 37 | #include <asm/byteorder.h> |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 38 | |
| 39 | #if defined(CONFIG_KIRKWOOD) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 40 | #include <asm/arch/kirkwood.h> |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 41 | #endif |
| 42 | |
Albert Aribaud | 9b6bcdc | 2010-07-12 22:24:27 +0200 | [diff] [blame] | 43 | #include "mvgbe.h" |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 44 | |
Albert Aribaud | 49fa6ed | 2010-07-05 20:15:25 +0200 | [diff] [blame] | 45 | DECLARE_GLOBAL_DATA_PTR; |
| 46 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 47 | #define MV_PHY_ADR_REQUEST 0xee |
| 48 | #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi) |
Simon Kagstrom | bb1ca3b | 2009-08-20 10:12:28 +0200 | [diff] [blame] | 49 | |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 50 | /* |
| 51 | * smi_reg_read - miiphy_read callback function. |
| 52 | * |
| 53 | * Returns 16bit phy register value, or 0xffff on error |
| 54 | */ |
| 55 | static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data) |
| 56 | { |
| 57 | struct eth_device *dev = eth_get_dev_by_name(devname); |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 58 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
| 59 | struct mvgbe_registers *regs = dmvgbe->regs; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 60 | u32 smi_reg; |
Simon Kagstrom | 7b05f5e | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 61 | u32 timeout; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 62 | |
| 63 | /* Phyadr read request */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 64 | if (phy_adr == MV_PHY_ADR_REQUEST && |
| 65 | reg_ofs == MV_PHY_ADR_REQUEST) { |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 66 | /* */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 67 | *data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 68 | return 0; |
| 69 | } |
| 70 | /* check parameters */ |
| 71 | if (phy_adr > PHYADR_MASK) { |
| 72 | printf("Err..(%s) Invalid PHY address %d\n", |
| 73 | __FUNCTION__, phy_adr); |
| 74 | return -EFAULT; |
| 75 | } |
| 76 | if (reg_ofs > PHYREG_MASK) { |
| 77 | printf("Err..(%s) Invalid register offset %d\n", |
| 78 | __FUNCTION__, reg_ofs); |
| 79 | return -EFAULT; |
| 80 | } |
| 81 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 82 | timeout = MVGBE_PHY_SMI_TIMEOUT; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 83 | /* wait till the SMI is not busy */ |
| 84 | do { |
| 85 | /* read smi register */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 86 | smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 87 | if (timeout-- == 0) { |
| 88 | printf("Err..(%s) SMI busy timeout\n", __FUNCTION__); |
| 89 | return -EFAULT; |
| 90 | } |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 91 | } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 92 | |
| 93 | /* fill the phy address and regiser offset and read opcode */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 94 | smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS) |
| 95 | | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS) |
| 96 | | MVGBE_PHY_SMI_OPCODE_READ; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 97 | |
| 98 | /* write the smi register */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 99 | MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 100 | |
| 101 | /*wait till read value is ready */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 102 | timeout = MVGBE_PHY_SMI_TIMEOUT; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 103 | |
| 104 | do { |
| 105 | /* read smi register */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 106 | smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 107 | if (timeout-- == 0) { |
| 108 | printf("Err..(%s) SMI read ready timeout\n", |
| 109 | __FUNCTION__); |
| 110 | return -EFAULT; |
| 111 | } |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 112 | } while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK)); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 113 | |
| 114 | /* Wait for the data to update in the SMI register */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 115 | for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++) |
| 116 | ; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 117 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 118 | *data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 119 | |
| 120 | debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr, |
| 121 | reg_ofs, *data); |
| 122 | |
| 123 | return 0; |
| 124 | } |
| 125 | |
| 126 | /* |
| 127 | * smi_reg_write - imiiphy_write callback function. |
| 128 | * |
| 129 | * Returns 0 if write succeed, -EINVAL on bad parameters |
| 130 | * -ETIME on timeout |
| 131 | */ |
| 132 | static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data) |
| 133 | { |
| 134 | struct eth_device *dev = eth_get_dev_by_name(devname); |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 135 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
| 136 | struct mvgbe_registers *regs = dmvgbe->regs; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 137 | u32 smi_reg; |
Simon Kagstrom | 7b05f5e | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 138 | u32 timeout; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 139 | |
| 140 | /* Phyadr write request*/ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 141 | if (phy_adr == MV_PHY_ADR_REQUEST && |
| 142 | reg_ofs == MV_PHY_ADR_REQUEST) { |
| 143 | MVGBE_REG_WR(regs->phyadr, data); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 144 | return 0; |
| 145 | } |
| 146 | |
| 147 | /* check parameters */ |
| 148 | if (phy_adr > PHYADR_MASK) { |
| 149 | printf("Err..(%s) Invalid phy address\n", __FUNCTION__); |
| 150 | return -EINVAL; |
| 151 | } |
| 152 | if (reg_ofs > PHYREG_MASK) { |
| 153 | printf("Err..(%s) Invalid register offset\n", __FUNCTION__); |
| 154 | return -EINVAL; |
| 155 | } |
| 156 | |
| 157 | /* wait till the SMI is not busy */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 158 | timeout = MVGBE_PHY_SMI_TIMEOUT; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 159 | do { |
| 160 | /* read smi register */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 161 | smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 162 | if (timeout-- == 0) { |
| 163 | printf("Err..(%s) SMI busy timeout\n", __FUNCTION__); |
| 164 | return -ETIME; |
| 165 | } |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 166 | } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 167 | |
| 168 | /* fill the phy addr and reg offset and write opcode and data */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 169 | smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS); |
| 170 | smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS) |
| 171 | | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS); |
| 172 | smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 173 | |
| 174 | /* write the smi register */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 175 | MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 176 | |
| 177 | return 0; |
| 178 | } |
| 179 | |
| 180 | /* Stop and checks all queues */ |
| 181 | static void stop_queue(u32 * qreg) |
| 182 | { |
| 183 | u32 reg_data; |
| 184 | |
| 185 | reg_data = readl(qreg); |
| 186 | |
| 187 | if (reg_data & 0xFF) { |
| 188 | /* Issue stop command for active channels only */ |
| 189 | writel((reg_data << 8), qreg); |
| 190 | |
| 191 | /* Wait for all queue activity to terminate. */ |
| 192 | do { |
| 193 | /* |
| 194 | * Check port cause register that all queues |
| 195 | * are stopped |
| 196 | */ |
| 197 | reg_data = readl(qreg); |
| 198 | } |
| 199 | while (reg_data & 0xFF); |
| 200 | } |
| 201 | } |
| 202 | |
| 203 | /* |
| 204 | * set_access_control - Config address decode parameters for Ethernet unit |
| 205 | * |
| 206 | * This function configures the address decode parameters for the Gigabit |
| 207 | * Ethernet Controller according the given parameters struct. |
| 208 | * |
| 209 | * @regs Register struct pointer. |
| 210 | * @param Address decode parameter struct. |
| 211 | */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 212 | static void set_access_control(struct mvgbe_registers *regs, |
| 213 | struct mvgbe_winparam *param) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 214 | { |
| 215 | u32 access_prot_reg; |
| 216 | |
| 217 | /* Set access control register */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 218 | access_prot_reg = MVGBE_REG_RD(regs->epap); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 219 | /* clear window permission */ |
| 220 | access_prot_reg &= (~(3 << (param->win * 2))); |
| 221 | access_prot_reg |= (param->access_ctrl << (param->win * 2)); |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 222 | MVGBE_REG_WR(regs->epap, access_prot_reg); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 223 | |
| 224 | /* Set window Size reg (SR) */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 225 | MVGBE_REG_WR(regs->barsz[param->win].size, |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 226 | (((param->size / 0x10000) - 1) << 16)); |
| 227 | |
| 228 | /* Set window Base address reg (BA) */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 229 | MVGBE_REG_WR(regs->barsz[param->win].bar, |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 230 | (param->target | param->attrib | param->base_addr)); |
| 231 | /* High address remap reg (HARR) */ |
| 232 | if (param->win < 4) |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 233 | MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 234 | |
| 235 | /* Base address enable reg (BARER) */ |
| 236 | if (param->enable == 1) |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 237 | MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win)); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 238 | else |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 239 | MVGBE_REG_BITS_SET(regs->bare, (1 << param->win)); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 240 | } |
| 241 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 242 | static void set_dram_access(struct mvgbe_registers *regs) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 243 | { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 244 | struct mvgbe_winparam win_param; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 245 | int i; |
| 246 | |
| 247 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { |
| 248 | /* Set access parameters for DRAM bank i */ |
| 249 | win_param.win = i; /* Use Ethernet window i */ |
| 250 | /* Window target - DDR */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 251 | win_param.target = MVGBE_TARGET_DRAM; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 252 | /* Enable full access */ |
| 253 | win_param.access_ctrl = EWIN_ACCESS_FULL; |
| 254 | win_param.high_addr = 0; |
Albert Aribaud | 49fa6ed | 2010-07-05 20:15:25 +0200 | [diff] [blame] | 255 | /* Get bank base and size */ |
| 256 | win_param.base_addr = gd->bd->bi_dram[i].start; |
| 257 | win_param.size = gd->bd->bi_dram[i].size; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 258 | if (win_param.size == 0) |
| 259 | win_param.enable = 0; |
| 260 | else |
| 261 | win_param.enable = 1; /* Enable the access */ |
| 262 | |
| 263 | /* Enable DRAM bank */ |
| 264 | switch (i) { |
| 265 | case 0: |
| 266 | win_param.attrib = EBAR_DRAM_CS0; |
| 267 | break; |
| 268 | case 1: |
| 269 | win_param.attrib = EBAR_DRAM_CS1; |
| 270 | break; |
| 271 | case 2: |
| 272 | win_param.attrib = EBAR_DRAM_CS2; |
| 273 | break; |
| 274 | case 3: |
| 275 | win_param.attrib = EBAR_DRAM_CS3; |
| 276 | break; |
| 277 | default: |
Albert Aribaud | 49fa6ed | 2010-07-05 20:15:25 +0200 | [diff] [blame] | 278 | /* invalid bank, disable access */ |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 279 | win_param.enable = 0; |
| 280 | win_param.attrib = 0; |
| 281 | break; |
| 282 | } |
| 283 | /* Set the access control for address window(EPAPR) RD/WR */ |
| 284 | set_access_control(regs, &win_param); |
| 285 | } |
| 286 | } |
| 287 | |
| 288 | /* |
| 289 | * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables |
| 290 | * |
| 291 | * Go through all the DA filter tables (Unicast, Special Multicast & Other |
| 292 | * Multicast) and set each entry to 0. |
| 293 | */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 294 | static void port_init_mac_tables(struct mvgbe_registers *regs) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 295 | { |
| 296 | int table_index; |
| 297 | |
| 298 | /* Clear DA filter unicast table (Ex_dFUT) */ |
| 299 | for (table_index = 0; table_index < 4; ++table_index) |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 300 | MVGBE_REG_WR(regs->dfut[table_index], 0); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 301 | |
| 302 | for (table_index = 0; table_index < 64; ++table_index) { |
| 303 | /* Clear DA filter special multicast table (Ex_dFSMT) */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 304 | MVGBE_REG_WR(regs->dfsmt[table_index], 0); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 305 | /* Clear DA filter other multicast table (Ex_dFOMT) */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 306 | MVGBE_REG_WR(regs->dfomt[table_index], 0); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 307 | } |
| 308 | } |
| 309 | |
| 310 | /* |
| 311 | * port_uc_addr - This function Set the port unicast address table |
| 312 | * |
| 313 | * This function locates the proper entry in the Unicast table for the |
| 314 | * specified MAC nibble and sets its properties according to function |
| 315 | * parameters. |
| 316 | * This function add/removes MAC addresses from the port unicast address |
| 317 | * table. |
| 318 | * |
| 319 | * @uc_nibble Unicast MAC Address last nibble. |
| 320 | * @option 0 = Add, 1 = remove address. |
| 321 | * |
| 322 | * RETURN: 1 if output succeeded. 0 if option parameter is invalid. |
| 323 | */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 324 | static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble, |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 325 | int option) |
| 326 | { |
| 327 | u32 unicast_reg; |
| 328 | u32 tbl_offset; |
| 329 | u32 reg_offset; |
| 330 | |
| 331 | /* Locate the Unicast table entry */ |
| 332 | uc_nibble = (0xf & uc_nibble); |
| 333 | /* Register offset from unicast table base */ |
| 334 | tbl_offset = (uc_nibble / 4); |
| 335 | /* Entry offset within the above register */ |
| 336 | reg_offset = uc_nibble % 4; |
| 337 | |
| 338 | switch (option) { |
| 339 | case REJECT_MAC_ADDR: |
| 340 | /* |
| 341 | * Clear accepts frame bit at specified unicast |
| 342 | * DA table entry |
| 343 | */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 344 | unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 345 | unicast_reg &= (0xFF << (8 * reg_offset)); |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 346 | MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 347 | break; |
| 348 | case ACCEPT_MAC_ADDR: |
| 349 | /* Set accepts frame bit at unicast DA filter table entry */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 350 | unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 351 | unicast_reg &= (0xFF << (8 * reg_offset)); |
| 352 | unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset)); |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 353 | MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 354 | break; |
| 355 | default: |
| 356 | return 0; |
| 357 | } |
| 358 | return 1; |
| 359 | } |
| 360 | |
| 361 | /* |
| 362 | * port_uc_addr_set - This function Set the port Unicast address. |
| 363 | */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 364 | static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 365 | { |
| 366 | u32 mac_h; |
| 367 | u32 mac_l; |
| 368 | |
| 369 | mac_l = (p_addr[4] << 8) | (p_addr[5]); |
| 370 | mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | |
| 371 | (p_addr[3] << 0); |
| 372 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 373 | MVGBE_REG_WR(regs->macal, mac_l); |
| 374 | MVGBE_REG_WR(regs->macah, mac_h); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 375 | |
| 376 | /* Accept frames of this address */ |
| 377 | port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR); |
| 378 | } |
| 379 | |
| 380 | /* |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 381 | * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 382 | */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 383 | static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 384 | { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 385 | struct mvgbe_rxdesc *p_rx_desc; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 386 | int i; |
| 387 | |
| 388 | /* initialize the Rx descriptors ring */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 389 | p_rx_desc = dmvgbe->p_rxdesc; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 390 | for (i = 0; i < RINGSZ; i++) { |
| 391 | p_rx_desc->cmd_sts = |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 392 | MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 393 | p_rx_desc->buf_size = PKTSIZE_ALIGN; |
| 394 | p_rx_desc->byte_cnt = 0; |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 395 | p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 396 | if (i == (RINGSZ - 1)) |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 397 | p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 398 | else { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 399 | p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *) |
| 400 | ((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 401 | p_rx_desc = p_rx_desc->nxtdesc_p; |
| 402 | } |
| 403 | } |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 404 | dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 405 | } |
| 406 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 407 | static int mvgbe_init(struct eth_device *dev) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 408 | { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 409 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
| 410 | struct mvgbe_registers *regs = dmvgbe->regs; |
Prafulla Wadaskar | aba8237 | 2009-09-09 15:59:19 +0530 | [diff] [blame] | 411 | #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \ |
| 412 | && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN) |
Simon Kagstrom | cad713b | 2009-08-20 10:13:06 +0200 | [diff] [blame] | 413 | int i; |
Prafulla Wadaskar | aba8237 | 2009-09-09 15:59:19 +0530 | [diff] [blame] | 414 | #endif |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 415 | /* setup RX rings */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 416 | mvgbe_init_rx_desc_ring(dmvgbe); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 417 | |
| 418 | /* Clear the ethernet port interrupts */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 419 | MVGBE_REG_WR(regs->ic, 0); |
| 420 | MVGBE_REG_WR(regs->ice, 0); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 421 | /* Unmask RX buffer and TX end interrupt */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 422 | MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 423 | /* Unmask phy and link status changes interrupts */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 424 | MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 425 | |
| 426 | set_dram_access(regs); |
| 427 | port_init_mac_tables(regs); |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 428 | port_uc_addr_set(regs, dmvgbe->dev.enetaddr); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 429 | |
| 430 | /* Assign port configuration and command. */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 431 | MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL); |
| 432 | MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE); |
| 433 | MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 434 | |
| 435 | /* Assign port SDMA configuration */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 436 | MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE); |
| 437 | MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL); |
| 438 | MVGBE_REG_WR(regs->tqx[0].tqxtbc, |
| 439 | (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 440 | /* Turn off the port/RXUQ bandwidth limitation */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 441 | MVGBE_REG_WR(regs->pmtu, 0); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 442 | |
| 443 | /* Set maximum receive buffer to 9700 bytes */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 444 | MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE |
| 445 | | (MVGBE_REG_RD(regs->psc0) & MRU_MASK)); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 446 | |
Prafulla Wadaskar | f0588fd | 2010-04-06 21:33:08 +0530 | [diff] [blame] | 447 | /* Enable port initially */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 448 | MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN); |
Prafulla Wadaskar | f0588fd | 2010-04-06 21:33:08 +0530 | [diff] [blame] | 449 | |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 450 | /* |
| 451 | * Set ethernet MTU for leaky bucket mechanism to 0 - this will |
| 452 | * disable the leaky bucket mechanism . |
| 453 | */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 454 | MVGBE_REG_WR(regs->pmtu, 0); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 455 | |
| 456 | /* Assignment of Rx CRDB of given RXUQ */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 457 | MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr); |
Albert Aribaud | c19a20d | 2010-07-10 15:41:29 +0200 | [diff] [blame] | 458 | /* ensure previous write is done before enabling Rx DMA */ |
| 459 | isb(); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 460 | /* Enable port Rx. */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 461 | MVGBE_REG_WR(regs->rqc, (1 << RXUQ)); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 462 | |
| 463 | #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \ |
| 464 | && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN) |
Simon Kagstrom | cad713b | 2009-08-20 10:13:06 +0200 | [diff] [blame] | 465 | /* Wait up to 5s for the link status */ |
| 466 | for (i = 0; i < 5; i++) { |
| 467 | u16 phyadr; |
| 468 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 469 | miiphy_read(dev->name, MV_PHY_ADR_REQUEST, |
| 470 | MV_PHY_ADR_REQUEST, &phyadr); |
Simon Kagstrom | cad713b | 2009-08-20 10:13:06 +0200 | [diff] [blame] | 471 | /* Return if we get link up */ |
| 472 | if (miiphy_link(dev->name, phyadr)) |
| 473 | return 0; |
| 474 | udelay(1000000); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 475 | } |
Simon Kagstrom | cad713b | 2009-08-20 10:13:06 +0200 | [diff] [blame] | 476 | |
| 477 | printf("No link on %s\n", dev->name); |
| 478 | return -1; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 479 | #endif |
| 480 | return 0; |
| 481 | } |
| 482 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 483 | static int mvgbe_halt(struct eth_device *dev) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 484 | { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 485 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
| 486 | struct mvgbe_registers *regs = dmvgbe->regs; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 487 | |
| 488 | /* Disable all gigE address decoder */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 489 | MVGBE_REG_WR(regs->bare, 0x3f); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 490 | |
| 491 | stop_queue(®s->tqc); |
| 492 | stop_queue(®s->rqc); |
| 493 | |
Prafulla Wadaskar | f0588fd | 2010-04-06 21:33:08 +0530 | [diff] [blame] | 494 | /* Disable port */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 495 | MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 496 | /* Set port is not reset */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 497 | MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 498 | #ifdef CONFIG_SYS_MII_MODE |
| 499 | /* Set MMI interface up */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 500 | MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 501 | #endif |
| 502 | /* Disable & mask ethernet port interrupts */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 503 | MVGBE_REG_WR(regs->ic, 0); |
| 504 | MVGBE_REG_WR(regs->ice, 0); |
| 505 | MVGBE_REG_WR(regs->pim, 0); |
| 506 | MVGBE_REG_WR(regs->peim, 0); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 507 | |
| 508 | return 0; |
| 509 | } |
| 510 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 511 | static int mvgbe_write_hwaddr(struct eth_device *dev) |
Prafulla Wadaskar | b5ce63e | 2010-04-06 22:21:33 +0530 | [diff] [blame] | 512 | { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 513 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
| 514 | struct mvgbe_registers *regs = dmvgbe->regs; |
Prafulla Wadaskar | b5ce63e | 2010-04-06 22:21:33 +0530 | [diff] [blame] | 515 | |
| 516 | /* Programs net device MAC address after initialization */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 517 | port_uc_addr_set(regs, dmvgbe->dev.enetaddr); |
Prafulla Wadaskar | b5ce63e | 2010-04-06 22:21:33 +0530 | [diff] [blame] | 518 | return 0; |
| 519 | } |
| 520 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 521 | static int mvgbe_send(struct eth_device *dev, void *dataptr, |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 522 | int datasize) |
| 523 | { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 524 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
| 525 | struct mvgbe_registers *regs = dmvgbe->regs; |
| 526 | struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc; |
Simon Kagstrom | 477fa63 | 2009-08-20 10:14:11 +0200 | [diff] [blame] | 527 | void *p = (void *)dataptr; |
Simon Kagstrom | 7b05f5e | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 528 | u32 cmd_sts; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 529 | |
Simon Kagstrom | 477fa63 | 2009-08-20 10:14:11 +0200 | [diff] [blame] | 530 | /* Copy buffer if it's misaligned */ |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 531 | if ((u32) dataptr & 0x07) { |
Simon Kagstrom | 477fa63 | 2009-08-20 10:14:11 +0200 | [diff] [blame] | 532 | if (datasize > PKTSIZE_ALIGN) { |
| 533 | printf("Non-aligned data too large (%d)\n", |
| 534 | datasize); |
| 535 | return -1; |
| 536 | } |
| 537 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 538 | memcpy(dmvgbe->p_aligned_txbuf, p, datasize); |
| 539 | p = dmvgbe->p_aligned_txbuf; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 540 | } |
Simon Kagstrom | 477fa63 | 2009-08-20 10:14:11 +0200 | [diff] [blame] | 541 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 542 | p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC; |
| 543 | p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC; |
| 544 | p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA; |
| 545 | p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT; |
Simon Kagstrom | 477fa63 | 2009-08-20 10:14:11 +0200 | [diff] [blame] | 546 | p_txdesc->buf_ptr = (u8 *) p; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 547 | p_txdesc->byte_cnt = datasize; |
| 548 | |
Albert Aribaud | c19a20d | 2010-07-10 15:41:29 +0200 | [diff] [blame] | 549 | /* Set this tc desc as zeroth TXUQ */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 550 | MVGBE_REG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc); |
Albert Aribaud | c19a20d | 2010-07-10 15:41:29 +0200 | [diff] [blame] | 551 | |
| 552 | /* ensure tx desc writes above are performed before we start Tx DMA */ |
| 553 | isb(); |
| 554 | |
| 555 | /* Apply send command using zeroth TXUQ */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 556 | MVGBE_REG_WR(regs->tqc, (1 << TXUQ)); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 557 | |
| 558 | /* |
| 559 | * wait for packet xmit completion |
| 560 | */ |
Simon Kagstrom | 7b05f5e | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 561 | cmd_sts = readl(&p_txdesc->cmd_sts); |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 562 | while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) { |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 563 | /* return fail if error is detected */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 564 | if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) == |
| 565 | (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) && |
| 566 | cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) { |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 567 | printf("Err..(%s) in xmit packet\n", __FUNCTION__); |
| 568 | return -1; |
| 569 | } |
Simon Kagstrom | 7b05f5e | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 570 | cmd_sts = readl(&p_txdesc->cmd_sts); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 571 | }; |
| 572 | return 0; |
| 573 | } |
| 574 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 575 | static int mvgbe_recv(struct eth_device *dev) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 576 | { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 577 | struct mvgbe_device *dmvgbe = to_mvgbe(dev); |
| 578 | struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr; |
Simon Kagstrom | 7b05f5e | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 579 | u32 cmd_sts; |
| 580 | u32 timeout = 0; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 581 | |
| 582 | /* wait untill rx packet available or timeout */ |
| 583 | do { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 584 | if (timeout < MVGBE_PHY_SMI_TIMEOUT) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 585 | timeout++; |
| 586 | else { |
| 587 | debug("%s time out...\n", __FUNCTION__); |
| 588 | return -1; |
| 589 | } |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 590 | } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 591 | |
| 592 | if (p_rxdesc_curr->byte_cnt != 0) { |
| 593 | debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n", |
| 594 | __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt, |
| 595 | (u32) p_rxdesc_curr->buf_ptr, |
| 596 | (u32) p_rxdesc_curr->cmd_sts); |
| 597 | } |
| 598 | |
| 599 | /* |
| 600 | * In case received a packet without first/last bits on |
| 601 | * OR the error summary bit is on, |
| 602 | * the packets needs to be dropeed. |
| 603 | */ |
Simon Kagstrom | 7b05f5e | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 604 | cmd_sts = readl(&p_rxdesc_curr->cmd_sts); |
| 605 | |
| 606 | if ((cmd_sts & |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 607 | (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) |
| 608 | != (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) { |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 609 | |
| 610 | printf("Err..(%s) Dropping packet spread on" |
| 611 | " multiple descriptors\n", __FUNCTION__); |
| 612 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 613 | } else if (cmd_sts & MVGBE_ERROR_SUMMARY) { |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 614 | |
| 615 | printf("Err..(%s) Dropping packet with errors\n", |
| 616 | __FUNCTION__); |
| 617 | |
| 618 | } else { |
| 619 | /* !!! call higher layer processing */ |
| 620 | debug("%s: Sending Received packet to" |
| 621 | " upper layer (NetReceive)\n", __FUNCTION__); |
| 622 | |
| 623 | /* let the upper layer handle the packet */ |
| 624 | NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET), |
| 625 | (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET)); |
| 626 | } |
| 627 | /* |
| 628 | * free these descriptors and point next in the ring |
| 629 | */ |
| 630 | p_rxdesc_curr->cmd_sts = |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 631 | MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 632 | p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; |
| 633 | p_rxdesc_curr->byte_cnt = 0; |
| 634 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 635 | writel((unsigned)p_rxdesc_curr->nxtdesc_p, |
| 636 | (u32) &dmvgbe->p_rxdesc_curr); |
Simon Kagstrom | 7b05f5e | 2009-07-08 13:03:18 +0200 | [diff] [blame] | 637 | |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 638 | return 0; |
| 639 | } |
| 640 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 641 | int mvgbe_initialize(bd_t *bis) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 642 | { |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 643 | struct mvgbe_device *dmvgbe; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 644 | struct eth_device *dev; |
| 645 | int devnum; |
Prafulla Wadaskar | 9fd38a0 | 2009-08-10 19:43:06 +0530 | [diff] [blame] | 646 | char *s; |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 647 | u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 648 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 649 | for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) { |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 650 | /*skip if port is configured not to use */ |
| 651 | if (used_ports[devnum] == 0) |
| 652 | continue; |
| 653 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 654 | dmvgbe = malloc(sizeof(struct mvgbe_device)); |
| 655 | |
| 656 | if (!dmvgbe) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 657 | goto error1; |
| 658 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 659 | memset(dmvgbe, 0, sizeof(struct mvgbe_device)); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 660 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 661 | dmvgbe->p_rxdesc = |
| 662 | (struct mvgbe_rxdesc *)memalign(PKTALIGN, |
| 663 | MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1); |
| 664 | |
| 665 | if (!dmvgbe->p_rxdesc) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 666 | goto error2; |
| 667 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 668 | dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, |
| 669 | RINGSZ*PKTSIZE_ALIGN + 1); |
| 670 | |
| 671 | if (!dmvgbe->p_rxbuf) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 672 | goto error3; |
| 673 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 674 | dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN); |
| 675 | |
| 676 | if (!dmvgbe->p_aligned_txbuf) |
Simon Kagstrom | 477fa63 | 2009-08-20 10:14:11 +0200 | [diff] [blame] | 677 | goto error4; |
| 678 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 679 | dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign( |
| 680 | PKTALIGN, sizeof(struct mvgbe_txdesc) + 1); |
| 681 | |
| 682 | if (!dmvgbe->p_txdesc) { |
| 683 | free(dmvgbe->p_aligned_txbuf); |
| 684 | error4: |
| 685 | free(dmvgbe->p_rxbuf); |
| 686 | error3: |
| 687 | free(dmvgbe->p_rxdesc); |
| 688 | error2: |
| 689 | free(dmvgbe); |
| 690 | error1: |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 691 | printf("Err.. %s Failed to allocate memory\n", |
| 692 | __FUNCTION__); |
| 693 | return -1; |
| 694 | } |
| 695 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 696 | dev = &dmvgbe->dev; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 697 | |
| 698 | /* must be less than NAMESIZE (16) */ |
| 699 | sprintf(dev->name, "egiga%d", devnum); |
| 700 | |
| 701 | /* Extract the MAC address from the environment */ |
| 702 | switch (devnum) { |
| 703 | case 0: |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 704 | dmvgbe->regs = (void *)MVGBE0_BASE; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 705 | s = "ethaddr"; |
| 706 | break; |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 707 | #if defined(MVGBE1_BASE) |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 708 | case 1: |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 709 | dmvgbe->regs = (void *)MVGBE1_BASE; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 710 | s = "eth1addr"; |
| 711 | break; |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 712 | #endif |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 713 | default: /* this should never happen */ |
| 714 | printf("Err..(%s) Invalid device number %d\n", |
| 715 | __FUNCTION__, devnum); |
| 716 | return -1; |
| 717 | } |
| 718 | |
| 719 | while (!eth_getenv_enetaddr(s, dev->enetaddr)) { |
Albert Aribaud | c67e2cc | 2010-07-12 11:03:33 +0200 | [diff] [blame] | 720 | /* Generate Private MAC addr if not set */ |
Prafulla Wadaskar | 9fd38a0 | 2009-08-10 19:43:06 +0530 | [diff] [blame] | 721 | dev->enetaddr[0] = 0x02; |
| 722 | dev->enetaddr[1] = 0x50; |
| 723 | dev->enetaddr[2] = 0x43; |
Albert Aribaud | c67e2cc | 2010-07-12 11:03:33 +0200 | [diff] [blame] | 724 | #if defined (CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION) |
| 725 | /* Generate fixed lower MAC half using devnum */ |
| 726 | dev->enetaddr[3] = 0; |
| 727 | dev->enetaddr[4] = 0; |
| 728 | dev->enetaddr[5] = devnum; |
| 729 | #else |
| 730 | /* Generate random lower MAC half */ |
Prafulla Wadaskar | 9fd38a0 | 2009-08-10 19:43:06 +0530 | [diff] [blame] | 731 | dev->enetaddr[3] = get_random_hex(); |
| 732 | dev->enetaddr[4] = get_random_hex(); |
| 733 | dev->enetaddr[5] = get_random_hex(); |
Albert Aribaud | c67e2cc | 2010-07-12 11:03:33 +0200 | [diff] [blame] | 734 | #endif |
Prafulla Wadaskar | 9fd38a0 | 2009-08-10 19:43:06 +0530 | [diff] [blame] | 735 | eth_setenv_enetaddr(s, dev->enetaddr); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 736 | } |
| 737 | |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 738 | dev->init = (void *)mvgbe_init; |
| 739 | dev->halt = (void *)mvgbe_halt; |
| 740 | dev->send = (void *)mvgbe_send; |
| 741 | dev->recv = (void *)mvgbe_recv; |
| 742 | dev->write_hwaddr = (void *)mvgbe_write_hwaddr; |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 743 | |
| 744 | eth_register(dev); |
| 745 | |
| 746 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
| 747 | miiphy_register(dev->name, smi_reg_read, smi_reg_write); |
| 748 | /* Set phy address of the port */ |
Albert Aribaud | d44265a | 2010-07-12 22:24:28 +0200 | [diff] [blame^] | 749 | miiphy_write(dev->name, MV_PHY_ADR_REQUEST, |
| 750 | MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum); |
Prafulla Wadaskar | 9131589 | 2009-06-14 22:33:46 +0530 | [diff] [blame] | 751 | #endif |
| 752 | } |
| 753 | return 0; |
Prafulla Wadaskar | 0b785dd | 2009-07-01 20:34:51 +0200 | [diff] [blame] | 754 | } |