Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / d45ffb79376a9ab28ddfd2a61111a1732541289a / . / arch / arm / dts / imx8mm-verdin.dts
blob: 2980053e82bf83ea01dc95fac2724ce64626be64 [file] [log] [blame]
Igor Opaniuk14d5aef2020-01-28 14:42:25 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright 2020 Toradex
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/usb/pd.h>
9#include "imx8mm.dtsi"
10
11/ {
12 model = "Toradex Verdin iMX8M Mini Quad/DualLite";
13 compatible = "toradex,verdin-imx8mm", "fsl,imx8mm";
14
15 chosen {
16 stdout-path = &uart1;
17 };
18
19 /* fixed clock dedicated to SPI CAN controller */
20 clk20m: oscillator {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <20000000>;
24 };
25
26 reg_ethphy: regulator-ethphy {
27 compatible = "regulator-fixed";
28 enable-active-high;
29 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
30 off-on-delay = <500000>;
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_reg_eth>;
33 regulator-boot-on;
34 regulator-max-microvolt = <3300000>;
35 regulator-min-microvolt = <3300000>;
36 regulator-name = "V3.3_ETH";
37 startup-delay-us = <200000>;
38 };
39
40 reg_usb_otg1_vbus: regulator-usb-otg1 {
41 compatible = "regulator-fixed";
42 enable-active-high;
43 /* Verdin USB1_EN */
44 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_reg_usb1_en>;
47 regulator-name = "usb_otg1_vbus";
48 regulator-min-microvolt = <5000000>;
49 regulator-max-microvolt = <5000000>;
50 };
51
52 reg_usb_otg2_vbus: regulator-usb-otg2 {
53 compatible = "regulator-fixed";
54 enable-active-high;
55 /* Verdin USB2_EN */
56 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_reg_usb2_en>;
59 regulator-name = "usb_otg2_vbus";
60 regulator-min-microvolt = <5000000>;
61 regulator-max-microvolt = <5000000>;
62 };
63
64 reg_usdhc2_vmmc: regulator-usdhc2 {
65 compatible = "regulator-fixed";
66 enable-active-high;
67 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
70 regulator-name = "V3.3_SD";
71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>;
73 startup-delay-us = <2000>;
74 };
75
76 reg_wifi_en: regulator-wifi-en {
77 compatible = "regulator-fixed";
78 enable-active-high;
79 gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_wifi_pwr_en>;
82 regulator-name = "V3.3_WI-FI";
83 regulator-min-microvolt = <3300000>;
84 regulator-max-microvolt = <3300000>;
85 startup-delay-us = <2000>;
86 };
87};
88
89&A53_0 {
90 arm-supply = <&buck2_reg>;
91};
92
93&clk {
94 assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>, <&clk IMX8MM_AUDIO_PLL2>;
95 assigned-clock-rates = <786432000>, <722534400>;
96};
97
98/* Verdin SPI_1 */
99&ecspi2 {
100 #address-cells = <1>;
101 #size-cells = <0>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_ecspi2>;
104 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
105 status = "okay";
106
107 spidev20: spidev@0 {
108 compatible = "toradex,evalspi";
109 reg = <0>;
110 spi-max-frequency = <10000000>;
111 status = "okay";
112 };
113};
114
115/* On-module CAN controller 1 & 2 */
116&ecspi3 {
117 #address-cells = <1>;
118 #size-cells = <0>;
119 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>,
120 <&gpio1 5 GPIO_ACTIVE_LOW>;
121 /* This property is required, even if marked as obsolete in the doku */
122 fsl,spi-num-chipselects = <2>;
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_ecspi3>;
125 status = "okay";
126
127 can1: can@0 {
128 compatible = "microchip,mcp2517fd";
129 clocks = <&clk20m>;
130 gpio-controller;
131 interrupt-parent = <&gpio1>;
132 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
133 microchip,clock-allways-on;
134 microchip,clock-out-div = <1>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_can1_int>;
137 reg = <0>;
138 spi-max-frequency = <2000000>;
139 };
140
141 can2: can@1 {
142 compatible = "microchip,mcp2517fd";
143 clocks = <&clk20m>;
144 gpio-controller;
145 interrupt-parent = <&gpio1>;
146 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_can2_int>;
149 reg = <1>;
150 spi-max-frequency = <2000000>;
151 };
152};
153
154&fec1 {
155 fsl,magic-packet;
156 fsl,rgmii_rxc_dly;
157 fsl,rgmii_txc_dly;
158 phy-handle = <&ethphy0>;
159 phy-mode = "rgmii";
160 phy-supply = <&reg_ethphy>;
161 pinctrl-names = "default", "sleep";
162 pinctrl-0 = <&pinctrl_fec1>;
163 pinctrl-1 = <&pinctrl_fec1_sleep>;
164 status = "okay";
165
166 mdio {
167 #address-cells = <1>;
168 #size-cells = <0>;
169
170 ethphy0: ethernet-phy@7 {
171 compatible = "ethernet-phy-ieee802.3-c22";
172 interrupt-parent = <&gpio1>;
173 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
174 micrel,led-mode = <0>;
175 reg = <7>;
176 };
177 };
178};
179
180&gpio4 {
181 /*
182 * The SE050 security element may be driven via I2C from user space.
183 * The element itself is enabled here as it has no kernel driver.
184 */
185 se050_ena {
186 gpio-hog;
187 gpios = <19 GPIO_ACTIVE_HIGH>;
188 line-name = "SE050_ENABLE";
189 output-high;
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_se050_ena>;
192 };
193};
194
195/* On-module I2C */
196&i2c1 {
197 clock-frequency = <400000>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_i2c1>;
200 status = "okay";
201
202 pmic@4b {
203 compatible = "rohm,bd71840", "rohm,bd71837";
204 bd71837,pmic-buck2-uses-i2c-dvs;
205 bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
206 gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
207 /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */
208 pinctrl-0 = <&pinctrl_pmic>;
209 reg = <0x4b>;
210
211 gpo {
212 rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */
213 };
214
215 regulators {
216 buck1_reg: BUCK1 {
217 regulator-always-on;
218 regulator-boot-on;
219 regulator-compatible = "buck1";
220 regulator-max-microvolt = <1300000>;
221 regulator-min-microvolt = <700000>;
222 regulator-ramp-delay = <1250>;
223 };
224
225 buck2_reg: BUCK2 {
226 regulator-always-on;
227 regulator-boot-on;
228 regulator-compatible = "buck2";
229 regulator-max-microvolt = <1300000>;
230 regulator-min-microvolt = <700000>;
231 regulator-ramp-delay = <1250>;
232 };
233
234 buck5_reg: BUCK5 {
235 regulator-always-on;
236 regulator-boot-on;
237 regulator-compatible = "buck5";
238 regulator-max-microvolt = <1350000>;
239 regulator-min-microvolt = <700000>;
240 };
241
242 buck6_reg: BUCK6 {
243 regulator-always-on;
244 regulator-boot-on;
245 regulator-compatible = "buck6";
246 regulator-max-microvolt = <3300000>;
247 regulator-min-microvolt = <3000000>;
248 };
249
250 buck7_reg: BUCK7 {
251 regulator-always-on;
252 regulator-boot-on;
253 regulator-compatible = "buck7";
254 regulator-max-microvolt = <1995000>;
255 regulator-min-microvolt = <1605000>;
256 };
257
258 buck8_reg: BUCK8 {
259 regulator-always-on;
260 regulator-boot-on;
261 regulator-compatible = "buck8";
262 regulator-max-microvolt = <1400000>;
263 regulator-min-microvolt = <800000>;
264 };
265
266 ldo1_reg: LDO1 {
267 regulator-always-on;
268 regulator-boot-on;
269 regulator-compatible = "ldo1";
270 regulator-max-microvolt = <3300000>;
271 regulator-min-microvolt = <3000000>;
272 };
273
274 ldo2_reg: LDO2 {
275 regulator-always-on;
276 regulator-boot-on;
277 regulator-compatible = "ldo2";
278 regulator-max-microvolt = <900000>;
279 regulator-min-microvolt = <900000>;
280 };
281
282 ldo3_reg: LDO3 {
283 regulator-always-on;
284 regulator-boot-on;
285 regulator-compatible = "ldo3";
286 regulator-max-microvolt = <3300000>;
287 regulator-min-microvolt = <1800000>;
288 };
289
290 ldo4_reg: LDO4 {
291 regulator-always-on;
292 regulator-boot-on;
293 regulator-compatible = "ldo4";
294 regulator-max-microvolt = <1800000>;
295 regulator-min-microvolt = <900000>;
296 };
297
298 ldo5_reg: LDO5 {
299 regulator-compatible = "ldo5";
300 regulator-max-microvolt = <3300000>;
301 regulator-min-microvolt = <3300000>;
302 };
303
304 ldo6_reg: LDO6 {
305 regulator-always-on;
306 regulator-boot-on;
307 regulator-compatible = "ldo6";
308 regulator-max-microvolt = <1800000>;
309 regulator-min-microvolt = <900000>;
310 };
311 };
312 };
313
314 /* Epson RX8130 real time clock on carrier board */
315 rtc@32 {
316 compatible = "epson,rx8130";
317 reg = <0x32>;
318 };
319
320 adc@34 {
321 compatible = "maxim,max11607";
322 reg = <0x34>;
323 vcc-supply = <&ldo5_reg>;
324 };
325
326 eeprom@50 {
327 compatible = "st,24c02";
328 pagesize = <16>;
329 reg = <0x50>;
330 };
331};
332
333/* Verdin I2C_2_DSI */
334&i2c2 {
335 clock-frequency = <10000>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_i2c2>;
338 status = "okay";
339};
340
341/* Verdin I2C_3_HDMI N/A */
342
343/* Verdin I2C_4_CSI */
344&i2c3 {
345 clock-frequency = <400000>;
346 pinctrl-names = "default";
347 pinctrl-0 = <&pinctrl_i2c3>;
348 status = "okay";
349};
350
351/* Verdin I2C_1 */
352&i2c4 {
353 clock-frequency = <400000>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&pinctrl_i2c4>;
356 status = "okay";
357
358 /* Audio Codec */
359 wm8904_1a: codec@1a {
360 compatible = "wlf,wm8904";
361 #sound-dai-cells = <0>;
362 clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
363 clock-names = "mclk";
364 reg = <0x1a>;
365 };
366
367 gpio_expander_21: gpio-expander@21 {
368 compatible = "nxp,pcal6416";
369 #gpio-cells = <2>;
370 gpio-controller;
371 reg = <0x21>;
372 };
373
374 /* Current measurement into module VCC */
375 hwmon@40 {
376 compatible = "ti,ina219";
377 reg = <0x40>;
378 shunt-resistor = <10000>;
379 status = "okay";
380 };
381
382 /* EEPROM on MIPI-DSI to HDMI adapter */
383 eeprom_50: eeprom@50 {
384 compatible = "st,24c02";
385 pagesize = <16>;
386 reg = <0x50>;
387 };
388
389 /* EEPROM on Verdin Development board */
390 eeprom_57: eeprom@57 {
391 compatible = "st,24c02";
392 pagesize = <16>;
393 reg = <0x57>;
394 };
395};
396
397/* Verdin PWM_3_DSI */
398&pwm1 {
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_pwm_1>;
401 #pwm-cells = <3>;
402 status = "okay";
403};
404
405/* Verdin PWM_1 */
406&pwm2 {
407 pinctrl-names = "default";
408 pinctrl-0 = <&pinctrl_pwm_2>;
409 #pwm-cells = <3>;
410 status = "okay";
411};
412
413/* Verdin PWM_2 */
414&pwm3 {
415 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_pwm_3>;
417 #pwm-cells = <3>;
418 status = "okay";
419};
420
421/* Verdin UART_3, Console/Debug UART */
422&uart1 {
423 fsl,uart-has-rtscts;
424 pinctrl-names = "default";
425 pinctrl-0 = <&pinctrl_uart1>;
426 status = "okay";
427};
428
429/* Verdin UART_1 */
430&uart2 {
431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_uart2>;
433 fsl,uart-has-rtscts;
434 status = "okay";
435};
436
437/* Verdin UART_2 */
438&uart3 {
439 pinctrl-names = "default";
440 pinctrl-0 = <&pinctrl_uart3>;
441 fsl,uart-has-rtscts;
442 status = "okay";
443};
444
445/* Verdin UART_4 */
446/*
447 * resource allocated to M4 by default, must not be accessed from A-35 or you
448 * get an OOPS
449 */
450&uart4 {
451 pinctrl-names = "default";
452 pinctrl-0 = <&pinctrl_uart4>;
453 status = "disabled";
454};
455
456/* Verdin USB_1 */
457&usbotg1 {
458 dr_mode = "otg";
459 picophy,dc-vol-level-adjust = <7>;
460 picophy,pre-emp-curr-control = <3>;
461 vbus-supply = <&reg_usb_otg1_vbus>;
462 status = "okay";
463};
464
465/* Verdin USB_2 */
466&usbotg2 {
467 dr_mode = "host";
468 picophy,dc-vol-level-adjust = <7>;
469 picophy,pre-emp-curr-control = <3>;
470 vbus-supply = <&reg_usb_otg2_vbus>;
471 status = "okay";
472};
473
474/* On-module eMMC */
475&usdhc1 {
476 bus-width = <8>;
477 keep-power-in-suspend;
478 non-removable;
479 pinctrl-names = "default", "state_100mhz", "state_200mhz";
480 pinctrl-0 = <&pinctrl_usdhc1>;
481 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
482 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
483 pm-ignore-notify;
484 status = "okay";
485 /* TODO Strobe */
486};
487
488/* Verdin SD_1 */
489&usdhc2 {
490 bus-width = <4>;
491 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
492 pinctrl-names = "default", "state_100mhz", "state_200mhz";
493 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
494 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
495 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
496 vmmc-supply = <&reg_usdhc2_vmmc>;
497 status = "okay";
498};
499
500/* On-module Wi-Fi */
501&usdhc3 {
502 bus-width = <4>;
503 non-removable;
504 pinctrl-names = "default", "state_100mhz", "state_200mhz";
505 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>;
506 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>;
507 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>;
508 vmmc-supply = <&reg_wifi_en>;
509 status = "okay";
510};
511
512&wdog1 {
513 fsl,ext-reset-output;
514 pinctrl-names = "default";
515 pinctrl-0 = <&pinctrl_wdog>;
516 status = "okay";
517};
518
519&iomuxc {
520 pinctrl-names = "default";
521 pinctrl-0 = <&pinctrl_dsi_bkl_en>, <&pinctrl_gpio1>, <&pinctrl_gpio2>,
522 <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio5>,
523 <&pinctrl_gpio6>, <&pinctrl_gpio7>, <&pinctrl_gpio8>,
524 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>,
525 <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hpd>;
526
527 pinctrl_can1_int: can1intgrp {
528 fsl,pins = <
529 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x1c4
530 >;
531 };
532
533 pinctrl_can2_int: can2intgrp {
534 fsl,pins = <
535 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x1c4
536 >;
537 };
538
539 pinctrl_ctrl_force_off_moci: ctrlforceoffgrp {
540 fsl,pins = <
541 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1c4 /* SODIMM 250 */
542 >;
543 };
544
545 pinctrl_dsi_bkl_en: dsi_bkl_en {
546 fsl,pins = <
547 MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x1c4 /* SODIMM 21 */
548 >;
549 };
550
551 pinctrl_ecspi2: ecspi2grp {
552 fsl,pins = <
553 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x1c4 /* SODIMM 198 */
554 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x4 /* SODIMM 200 */
555 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x4 /* SODIMM 196 */
556 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x1c4 /* SODIMM 202 */
557 >;
558 };
559
560 pinctrl_ecspi3: ecspi3grp {
561 fsl,pins = <
562 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c4
563 MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x4
564 MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x4
565 MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x1c4
566 MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x1c4
567 >;
568 };
569
570 pinctrl_fec1: fec1grp {
571 fsl,pins = <
572 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
573 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
574 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
575 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
576 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
577 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
578 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
579 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
580 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
581 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
582 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
583 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
584 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
585 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
586 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c4
587 >;
588 };
589
590 pinctrl_fec1_sleep: fec1-sleepgrp {
591 fsl,pins = <
592 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
593 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
594 MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f
595 MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f
596 MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f
597 MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f
598 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
599 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
600 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
601 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
602 MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f
603 MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f
604 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
605 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
606 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x184
607 >;
608 };
609
610 pinctrl_flexspi0: flexspi0grp {
611 fsl,pins = <
612 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 /* SODIMM 52 */
613 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 /* SODIMM 54 */
614 MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82 /* SODIMM 64 */
615 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 /* SODIMM 56 */
616 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 /* SODIMM 58 */
617 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 /* SODIMM 60 */
618 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 /* SODIMM 62 */
619 MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82 /* SODIMM 66 */
620 >;
621 };
622
623 /* (MEZ_)GPIO_1 shared with (MEZ_)DSI_1_INT# on Verdin Development Board */
624 pinctrl_gpio1: gpio1grp {
625 fsl,pins = <
626 MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x184 /* SODIMM 206 */
627 >;
628 };
629
630 pinctrl_gpio2: gpio2grp {
631 fsl,pins = <
632 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x184 /* SODIMM 208 */
633 >;
634 };
635
636 pinctrl_gpio3: gpio3grp {
637 fsl,pins = <
638 MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x184 /* SODIMM 210 */
639 >;
640 };
641
642 pinctrl_gpio4: gpio4grp {
643 fsl,pins = <
644 MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x184 /* SODIMM 212 */
645 >;
646 };
647
648 pinctrl_gpio5: gpio5grp {
649 fsl,pins = <
650 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x184 /* SODIMM 216 */
651 >;
652 };
653
654 pinctrl_gpio6: gpio6grp {
655 fsl,pins = <
656 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x184 /* SODIMM 218 */
657 >;
658 };
659
660 pinctrl_gpio7: gpio7grp {
661 fsl,pins = <
662 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x184 /* SODIMM 220 */
663 >;
664 };
665
666 pinctrl_gpio8: gpio8grp {
667 fsl,pins = <
668 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184 /* SODIMM 222 */
669 >;
670 };
671
672 pinctrl_gpio_hog1: gpiohog1grp {
673 fsl,pins = <
674 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4 /* SODIMM 88 */
675 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4 /* SODIMM 90 */
676 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4 /* SODIMM 92 */
677 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4 /* SODIMM 94 */
678 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4 /* SODIMM 96 */
679 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4 /* SODIMM 100 */
680 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4 /* SODIMM 102 */
681 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4 /* SODIMM 104 */
682 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4 /* SODIMM 106 */
683 MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4 /* SODIMM 108 */
684 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4 /* SODIMM 112 */
685 MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4 /* SODIMM 114 */
686 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4 /* SODIMM 116 */
687 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4 /* SODIMM 118 */
688 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4 /* SODIMM 120 */
689 >;
690 };
691
692 pinctrl_gpio_hog2: gpiohog2grp {
693 fsl,pins = <
694 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1c4 /* SODIMM 91 */
695 >;
696 };
697
698 pinctrl_gpio_hog3: gpiohog3grp {
699 fsl,pins = <
700 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x1c4 /* SODIMM 157 */
701 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 /* SODIMM 187 */
702 >;
703 };
704
705 /* (MEZ_)DSI_1_INT# shared with (MEZ_)GPIO_1 on Verdin Development Board */
706 pinctrl_gpio_hpd: gpiohpdgrp {
707 fsl,pins = <
708 MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x184 /* SODIMM 17 */
709 >;
710 };
711
712 /* On-module I2C */
713 pinctrl_i2c1: i2c1grp {
714 fsl,pins = <
715 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c6
716 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c6
717 >;
718 };
719
720 /* Verdin I2C_4_CSI */
721 pinctrl_i2c2: i2c2grp {
722 fsl,pins = <
723 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c6 /* SODIMM 55 */
724 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c6 /* SODIMM 53 */
725 >;
726 };
727
728 /* Verdin I2C_2_DSI */
729 pinctrl_i2c3: i2c3grp {
730 fsl,pins = <
731 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c6 /* SODIMM 95 */
732 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c6 /* SODIMM 93 */
733 >;
734 };
735
736 /* Verdin I2C_1 */
737 pinctrl_i2c4: i2c4grp {
738 fsl,pins = <
739 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c6 /* SODIMM 14 */
740 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c6 /* SODIMM 12 */
741 >;
742 };
743
744 pinctrl_pcie0: pcie0grp {
745 fsl,pins = <
746 MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6 /* SODIMM 244 */
747 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6 /* PMIC_EN_PCIe_CLK */
748 >;
749 };
750
751 pinctrl_pmic: pmicirqgrp {
752 fsl,pins = <
753 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
754 >;
755 };
756
757 pinctrl_pwm_1: pwm1grp {
758 fsl,pins = <
759 MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* SODIMM 19 */
760 >;
761 };
762
763 pinctrl_pwm_2: pwm2grp {
764 fsl,pins = <
765 MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6 /* SODIMM 15 */
766 >;
767 };
768
769 pinctrl_pwm_3: pwm3grp {
770 fsl,pins = <
771 MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6 /* SODIMM 16 */
772 >;
773 };
774
775 pinctrl_reg_eth: regethgrp {
776 fsl,pins = <
777 MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x184
778 >;
779 };
780
781 pinctrl_reg_usb1_en: regusb1engrp {
782 fsl,pins = <
783 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x184 /* SODIMM 155 */
784 >;
785 };
786
787 pinctrl_reg_usb2_en: regusb2engrp {
788 fsl,pins = <
789 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x184 /* SODIMM 185 */
790 >;
791 };
792
793 pinctrl_sai2: sai2grp {
794 fsl,pins = <
795 MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 /* SODIMM 38 */
796 MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 /* SODIMM 36 */
797 MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 /* SODIMM 30 */
798 MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 /* SODIMM 34 */
799 MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 /* SODIMM 32 */
800 >;
801 };
802
803 pinctrl_sai5: sai5grp {
804 fsl,pins = <
805 MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 /* SODIMM 48 */
806 MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 /* SODIMM 44 */
807 MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 /* SODIMM 42 */
808 MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 /* SODIMM 46 */
809 >;
810 };
811
812 pinctrl_se050_ena: se050enagrp {
813 fsl,pins = <
814 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x184
815 >;
816 };
817
818 pinctrl_uart1: uart1grp {
819 fsl,pins = <
820 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4 /* SODIMM 147 */
821 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4 /* SODIMM 149 */
822 >;
823 };
824
825 pinctrl_uart2: uart2grp {
826 fsl,pins = <
827 MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1c4 /* SODIMM 133 */
828 MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1c4 /* SODIMM 135 */
829 MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1c4 /* SODIMM 131 */
830 MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1c4 /* SODIMM 129 */
831 >;
832 };
833
834 pinctrl_uart3: uart3grp {
835 fsl,pins = <
836 MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1c4 /* SODIMM 141 */
837 MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1c4 /* SODIMM 139 */
838 MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1c4 /* SODIMM 137 */
839 MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x1c4 /* SODIMM 143 */
840 >;
841 };
842
843 pinctrl_uart4: uart4grp {
844 fsl,pins = <
845 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x1c4 /* SODIMM 151 */
846 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x1c4 /* SODIMM 153 */
847 >;
848 };
849
850 pinctrl_usdhc1: usdhc1grp {
851 fsl,pins = <
852 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
853 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
854 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
855 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
856 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
857 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
858 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
859 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
860 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
861 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
862 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
863 >;
864 };
865
866 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
867 fsl,pins = <
868 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
869 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
870 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
871 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
872 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
873 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
874 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
875 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
876 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
877 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
878 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
879 >;
880 };
881
882 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
883 fsl,pins = <
884 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
885 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
886 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
887 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
888 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
889 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
890 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
891 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
892 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
893 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
894 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
895 >;
896 };
897
898 pinctrl_usdhc2_cd: usdhc2cdgrp {
899 fsl,pins = <
900 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 /* SODIMM 84 */
901 >;
902 };
903
904 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
905 fsl,pins = <
906 MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x184 /* SODIMM 76 */
907 >;
908 };
909
910 pinctrl_usdhc2: usdhc2grp {
911 fsl,pins = <
912 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
913 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 /* SODIMM 78 */
914 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 /* SODIMM 74 */
915 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 /* SODIMM 80 */
916 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SODIMM 82 */
917 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SODIMM 70 */
918 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SODIMM 72 */
919 >;
920 };
921
922 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
923 fsl,pins = <
924 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
925 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
926 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
927 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
928 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
929 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
930 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
931 >;
932 };
933
934 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
935 fsl,pins = <
936 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
937 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
938 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
939 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
940 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
941 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
942 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
943 >;
944 };
945
946 pinctrl_usdhc3: usdhc3grp {
947 fsl,pins = <
948 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
949 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
950 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
951 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
952 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
953 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
954 >;
955 };
956
957 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
958 fsl,pins = <
959 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
960 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
961 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
962 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
963 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
964 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
965 >;
966 };
967
968 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
969 fsl,pins = <
970 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
971 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
972 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
973 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
974 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
975 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
976 >;
977 };
978
979 pinctrl_wdog: wdoggrp {
980 fsl,pins = <
981 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
982 >;
983 };
984
985 pinctrl_wifi_ctrl: wifictrlgrp {
986 fsl,pins = <
987 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x1c4 /* WIFI_WKUP_BT */
988 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x1c4 /* WIFI_W_WKUP_HOST */
989 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x1c4 /* WIFI_WKUP_WLAN */
990 >;
991 };
992
993 pinctrl_wifi_i2s: wifii2sgrp {
994 fsl,pins = <
995 MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0xd6
996 MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0xd6
997 MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0xd6
998 MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0xd6
999 >;
1000 };
1001
1002 pinctrl_wifi_pwr_en: wifipwrengrp {
1003 fsl,pins = <
1004 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x184 /* PMIC_EN_WIFI */
1005 >;
1006 };
1007};