Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. |
| 4 | * Terry Lv <r65388@freescale.com> |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Simon Glass | 0f07df4 | 2017-07-29 11:35:08 -0600 | [diff] [blame] | 7 | #include <common.h> |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 8 | #include <ahci.h> |
Simon Glass | c893f1e | 2017-07-29 11:35:16 -0600 | [diff] [blame] | 9 | #include <dm.h> |
| 10 | #include <dwc_ahsata.h> |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 11 | #include <fis.h> |
Simon Glass | 0f07df4 | 2017-07-29 11:35:08 -0600 | [diff] [blame] | 12 | #include <libata.h> |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 13 | #include <malloc.h> |
Simon Glass | 752126a | 2017-07-29 11:35:12 -0600 | [diff] [blame] | 14 | #include <memalign.h> |
Simon Glass | 0f07df4 | 2017-07-29 11:35:08 -0600 | [diff] [blame] | 15 | #include <sata.h> |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 16 | #include <asm/io.h> |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 17 | #include <asm/arch/clock.h> |
Tim Harvey | ca84d72 | 2014-05-07 22:23:35 -0700 | [diff] [blame] | 18 | #include <asm/arch/sys_proto.h> |
Simon Glass | 0f07df4 | 2017-07-29 11:35:08 -0600 | [diff] [blame] | 19 | #include <linux/bitops.h> |
| 20 | #include <linux/ctype.h> |
| 21 | #include <linux/errno.h> |
Simon Glass | 90abb28 | 2017-07-29 11:35:09 -0600 | [diff] [blame] | 22 | #include "dwc_ahsata_priv.h" |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 23 | |
| 24 | struct sata_port_regs { |
| 25 | u32 clb; |
| 26 | u32 clbu; |
| 27 | u32 fb; |
| 28 | u32 fbu; |
| 29 | u32 is; |
| 30 | u32 ie; |
| 31 | u32 cmd; |
| 32 | u32 res1[1]; |
| 33 | u32 tfd; |
| 34 | u32 sig; |
| 35 | u32 ssts; |
| 36 | u32 sctl; |
| 37 | u32 serr; |
| 38 | u32 sact; |
| 39 | u32 ci; |
| 40 | u32 sntf; |
| 41 | u32 res2[1]; |
| 42 | u32 dmacr; |
| 43 | u32 res3[1]; |
| 44 | u32 phycr; |
| 45 | u32 physr; |
| 46 | }; |
| 47 | |
| 48 | struct sata_host_regs { |
| 49 | u32 cap; |
| 50 | u32 ghc; |
| 51 | u32 is; |
| 52 | u32 pi; |
| 53 | u32 vs; |
| 54 | u32 ccc_ctl; |
| 55 | u32 ccc_ports; |
| 56 | u32 res1[2]; |
| 57 | u32 cap2; |
| 58 | u32 res2[30]; |
| 59 | u32 bistafr; |
| 60 | u32 bistcr; |
| 61 | u32 bistfctr; |
| 62 | u32 bistsr; |
| 63 | u32 bistdecr; |
| 64 | u32 res3[2]; |
| 65 | u32 oobr; |
| 66 | u32 res4[8]; |
| 67 | u32 timer1ms; |
| 68 | u32 res5[1]; |
| 69 | u32 gparam1r; |
| 70 | u32 gparam2r; |
| 71 | u32 pparamr; |
| 72 | u32 testr; |
| 73 | u32 versionr; |
| 74 | u32 idr; |
| 75 | }; |
| 76 | |
| 77 | #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024) |
| 78 | #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG) |
| 79 | |
| 80 | #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0) |
| 81 | |
Tang Yuantian | fa31377 | 2015-07-09 14:37:30 +0800 | [diff] [blame] | 82 | static inline void __iomem *ahci_port_base(void __iomem *base, u32 port) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 83 | { |
| 84 | return base + 0x100 + (port * 0x80); |
| 85 | } |
| 86 | |
| 87 | static int waiting_for_cmd_completed(u8 *offset, |
| 88 | int timeout_msec, |
| 89 | u32 sign) |
| 90 | { |
| 91 | int i; |
| 92 | u32 status; |
| 93 | |
| 94 | for (i = 0; |
| 95 | ((status = readl(offset)) & sign) && i < timeout_msec; |
| 96 | ++i) |
| 97 | mdelay(1); |
| 98 | |
| 99 | return (i < timeout_msec) ? 0 : -1; |
| 100 | } |
| 101 | |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 102 | static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 103 | { |
Simon Glass | 4b640db | 2017-07-29 11:35:05 -0600 | [diff] [blame] | 104 | struct sata_host_regs *host_mmio = uc_priv->mmio_base; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 105 | |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 106 | writel(SATA_HOST_OOBR_WE, &host_mmio->oobr); |
| 107 | writel(0x02060b14, &host_mmio->oobr); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 108 | |
| 109 | return 0; |
| 110 | } |
| 111 | |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 112 | static int ahci_host_init(struct ahci_uc_priv *uc_priv) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 113 | { |
| 114 | u32 tmp, cap_save, num_ports; |
| 115 | int i, j, timeout = 1000; |
| 116 | struct sata_port_regs *port_mmio = NULL; |
Simon Glass | 4b640db | 2017-07-29 11:35:05 -0600 | [diff] [blame] | 117 | struct sata_host_regs *host_mmio = uc_priv->mmio_base; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 118 | int clk = mxc_get_clock(MXC_SATA_CLK); |
| 119 | |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 120 | cap_save = readl(&host_mmio->cap); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 121 | cap_save |= SATA_HOST_CAP_SSS; |
| 122 | |
| 123 | /* global controller reset */ |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 124 | tmp = readl(&host_mmio->ghc); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 125 | if ((tmp & SATA_HOST_GHC_HR) == 0) |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 126 | writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 127 | |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 128 | while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 129 | ; |
| 130 | |
| 131 | if (timeout <= 0) { |
| 132 | debug("controller reset failed (0x%x)\n", tmp); |
| 133 | return -1; |
| 134 | } |
| 135 | |
| 136 | /* Set timer 1ms */ |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 137 | writel(clk / 1000, &host_mmio->timer1ms); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 138 | |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 139 | ahci_setup_oobr(uc_priv, 0); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 140 | |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 141 | writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc); |
| 142 | writel(cap_save, &host_mmio->cap); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 143 | num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1; |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 144 | writel_with_flush((1 << num_ports) - 1, &host_mmio->pi); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 145 | |
| 146 | /* |
| 147 | * Determine which Ports are implemented by the DWC_ahsata, |
| 148 | * by reading the PI register. This bit map value aids the |
| 149 | * software to determine how many Ports are available and |
| 150 | * which Port registers need to be initialized. |
| 151 | */ |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 152 | uc_priv->cap = readl(&host_mmio->cap); |
| 153 | uc_priv->port_map = readl(&host_mmio->pi); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 154 | |
| 155 | /* Determine how many command slots the HBA supports */ |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 156 | uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 157 | |
| 158 | debug("cap 0x%x port_map 0x%x n_ports %d\n", |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 159 | uc_priv->cap, uc_priv->port_map, uc_priv->n_ports); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 160 | |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 161 | for (i = 0; i < uc_priv->n_ports; i++) { |
| 162 | uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i); |
Simon Glass | 4b640db | 2017-07-29 11:35:05 -0600 | [diff] [blame] | 163 | port_mmio = uc_priv->port[i].port_mmio; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 164 | |
| 165 | /* Ensure that the DWC_ahsata is in idle state */ |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 166 | tmp = readl(&port_mmio->cmd); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 167 | |
| 168 | /* |
| 169 | * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR |
| 170 | * are all cleared, the Port is in an idle state. |
| 171 | */ |
| 172 | if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR | |
| 173 | SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) { |
| 174 | |
| 175 | /* |
| 176 | * System software places a Port into the idle state by |
| 177 | * clearing P#CMD.ST and waiting for P#CMD.CR to return |
| 178 | * 0 when read. |
| 179 | */ |
| 180 | tmp &= ~SATA_PORT_CMD_ST; |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 181 | writel_with_flush(tmp, &port_mmio->cmd); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 182 | |
| 183 | /* |
| 184 | * spec says 500 msecs for each bit, so |
| 185 | * this is slightly incorrect. |
| 186 | */ |
| 187 | mdelay(500); |
| 188 | |
| 189 | timeout = 1000; |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 190 | while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 191 | && --timeout) |
| 192 | ; |
| 193 | |
| 194 | if (timeout <= 0) { |
| 195 | debug("port reset failed (0x%x)\n", tmp); |
| 196 | return -1; |
| 197 | } |
| 198 | } |
| 199 | |
| 200 | /* Spin-up device */ |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 201 | tmp = readl(&port_mmio->cmd); |
| 202 | writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 203 | |
| 204 | /* Wait for spin-up to finish */ |
| 205 | timeout = 1000; |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 206 | while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 207 | && --timeout) |
| 208 | ; |
| 209 | if (timeout <= 0) { |
| 210 | debug("Spin-Up can't finish!\n"); |
| 211 | return -1; |
| 212 | } |
| 213 | |
| 214 | for (j = 0; j < 100; ++j) { |
| 215 | mdelay(10); |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 216 | tmp = readl(&port_mmio->ssts); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 217 | if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) || |
| 218 | ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1)) |
| 219 | break; |
| 220 | } |
| 221 | |
| 222 | /* Wait for COMINIT bit 26 (DIAG_X) in SERR */ |
| 223 | timeout = 1000; |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 224 | while (!(readl(&port_mmio->serr) | SATA_PORT_SERR_DIAG_X) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 225 | && --timeout) |
| 226 | ; |
| 227 | if (timeout <= 0) { |
| 228 | debug("Can't find DIAG_X set!\n"); |
| 229 | return -1; |
| 230 | } |
| 231 | |
| 232 | /* |
| 233 | * For each implemented Port, clear the P#SERR |
| 234 | * register, by writing ones to each implemented\ |
| 235 | * bit location. |
| 236 | */ |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 237 | tmp = readl(&port_mmio->serr); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 238 | debug("P#SERR 0x%x\n", |
| 239 | tmp); |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 240 | writel(tmp, &port_mmio->serr); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 241 | |
| 242 | /* Ack any pending irq events for this port */ |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 243 | tmp = readl(&host_mmio->is); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 244 | debug("IS 0x%x\n", tmp); |
| 245 | if (tmp) |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 246 | writel(tmp, &host_mmio->is); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 247 | |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 248 | writel(1 << i, &host_mmio->is); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 249 | |
| 250 | /* set irq mask (enables interrupts) */ |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 251 | writel(DEF_PORT_IRQ, &port_mmio->ie); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 252 | |
| 253 | /* register linkup ports */ |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 254 | tmp = readl(&port_mmio->ssts); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 255 | debug("Port %d status: 0x%x\n", i, tmp); |
| 256 | if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03) |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 257 | uc_priv->link_port_map |= (0x01 << i); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 258 | } |
| 259 | |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 260 | tmp = readl(&host_mmio->ghc); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 261 | debug("GHC 0x%x\n", tmp); |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 262 | writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc); |
| 263 | tmp = readl(&host_mmio->ghc); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 264 | debug("GHC 0x%x\n", tmp); |
| 265 | |
| 266 | return 0; |
| 267 | } |
| 268 | |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 269 | static void ahci_print_info(struct ahci_uc_priv *uc_priv) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 270 | { |
Simon Glass | 4b640db | 2017-07-29 11:35:05 -0600 | [diff] [blame] | 271 | struct sata_host_regs *host_mmio = uc_priv->mmio_base; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 272 | u32 vers, cap, impl, speed; |
| 273 | const char *speed_s; |
| 274 | const char *scc_s; |
| 275 | |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 276 | vers = readl(&host_mmio->vs); |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 277 | cap = uc_priv->cap; |
| 278 | impl = uc_priv->port_map; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 279 | |
| 280 | speed = (cap & SATA_HOST_CAP_ISS_MASK) |
| 281 | >> SATA_HOST_CAP_ISS_OFFSET; |
| 282 | if (speed == 1) |
| 283 | speed_s = "1.5"; |
| 284 | else if (speed == 2) |
| 285 | speed_s = "3"; |
| 286 | else |
| 287 | speed_s = "?"; |
| 288 | |
| 289 | scc_s = "SATA"; |
| 290 | |
| 291 | printf("AHCI %02x%02x.%02x%02x " |
| 292 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n", |
| 293 | (vers >> 24) & 0xff, |
| 294 | (vers >> 16) & 0xff, |
| 295 | (vers >> 8) & 0xff, |
| 296 | vers & 0xff, |
| 297 | ((cap >> 8) & 0x1f) + 1, |
| 298 | (cap & 0x1f) + 1, |
| 299 | speed_s, |
| 300 | impl, |
| 301 | scc_s); |
| 302 | |
| 303 | printf("flags: " |
| 304 | "%s%s%s%s%s%s" |
| 305 | "%s%s%s%s%s%s%s\n", |
| 306 | cap & (1 << 31) ? "64bit " : "", |
| 307 | cap & (1 << 30) ? "ncq " : "", |
| 308 | cap & (1 << 28) ? "ilck " : "", |
| 309 | cap & (1 << 27) ? "stag " : "", |
| 310 | cap & (1 << 26) ? "pm " : "", |
| 311 | cap & (1 << 25) ? "led " : "", |
| 312 | cap & (1 << 24) ? "clo " : "", |
| 313 | cap & (1 << 19) ? "nz " : "", |
| 314 | cap & (1 << 18) ? "only " : "", |
| 315 | cap & (1 << 17) ? "pmp " : "", |
| 316 | cap & (1 << 15) ? "pio " : "", |
| 317 | cap & (1 << 14) ? "slum " : "", |
| 318 | cap & (1 << 13) ? "part " : ""); |
| 319 | } |
| 320 | |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 321 | static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, |
| 322 | unsigned char *buf, int buf_len) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 323 | { |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 324 | struct ahci_ioports *pp = &uc_priv->port[port]; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 325 | struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; |
| 326 | u32 sg_count, max_bytes; |
| 327 | int i; |
| 328 | |
| 329 | max_bytes = MAX_DATA_BYTES_PER_SG; |
| 330 | sg_count = ((buf_len - 1) / max_bytes) + 1; |
| 331 | if (sg_count > AHCI_MAX_SG) { |
| 332 | printf("Error:Too much sg!\n"); |
| 333 | return -1; |
| 334 | } |
| 335 | |
| 336 | for (i = 0; i < sg_count; i++) { |
| 337 | ahci_sg->addr = |
| 338 | cpu_to_le32((u32)buf + i * max_bytes); |
| 339 | ahci_sg->addr_hi = 0; |
| 340 | ahci_sg->flags_size = cpu_to_le32(0x3fffff & |
| 341 | (buf_len < max_bytes |
| 342 | ? (buf_len - 1) |
| 343 | : (max_bytes - 1))); |
| 344 | ahci_sg++; |
| 345 | buf_len -= max_bytes; |
| 346 | } |
| 347 | |
| 348 | return sg_count; |
| 349 | } |
| 350 | |
| 351 | static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts) |
| 352 | { |
| 353 | struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot + |
| 354 | AHCI_CMD_SLOT_SZ * cmd_slot); |
| 355 | |
| 356 | memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ); |
| 357 | cmd_hdr->opts = cpu_to_le32(opts); |
| 358 | cmd_hdr->status = 0; |
Tang Yuantian | fa31377 | 2015-07-09 14:37:30 +0800 | [diff] [blame] | 359 | pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); |
| 360 | #ifdef CONFIG_PHYS_64BIT |
| 361 | pp->cmd_slot->tbl_addr_hi = |
| 362 | cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); |
| 363 | #endif |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 364 | } |
| 365 | |
| 366 | #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0) |
| 367 | |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 368 | static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port, |
| 369 | struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len, |
| 370 | s32 is_write) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 371 | { |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 372 | struct ahci_ioports *pp = &uc_priv->port[port]; |
Simon Glass | 4b640db | 2017-07-29 11:35:05 -0600 | [diff] [blame] | 373 | struct sata_port_regs *port_mmio = pp->port_mmio; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 374 | u32 opts; |
| 375 | int sg_count = 0, cmd_slot = 0; |
| 376 | |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 377 | cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci)); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 378 | if (32 == cmd_slot) { |
| 379 | printf("Can't find empty command slot!\n"); |
| 380 | return 0; |
| 381 | } |
| 382 | |
| 383 | /* Check xfer length */ |
| 384 | if (buf_len > MAX_BYTES_PER_TRANS) { |
| 385 | printf("Max transfer length is %dB\n\r", |
| 386 | MAX_BYTES_PER_TRANS); |
| 387 | return 0; |
| 388 | } |
| 389 | |
| 390 | memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d)); |
| 391 | if (buf && buf_len) |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 392 | sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 393 | opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16); |
Eric Nelson | 2dbe64c | 2013-06-15 16:09:55 -0700 | [diff] [blame] | 394 | if (is_write) { |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 395 | opts |= 0x40; |
Eric Nelson | 2dbe64c | 2013-06-15 16:09:55 -0700 | [diff] [blame] | 396 | flush_cache((ulong)buf, buf_len); |
| 397 | } |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 398 | ahci_fill_cmd_slot(pp, cmd_slot, opts); |
| 399 | |
Eric Nelson | 2dbe64c | 2013-06-15 16:09:55 -0700 | [diff] [blame] | 400 | flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ); |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 401 | writel_with_flush(1 << cmd_slot, &port_mmio->ci); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 402 | |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 403 | if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000, |
| 404 | 0x1 << cmd_slot)) { |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 405 | printf("timeout exit!\n"); |
| 406 | return -1; |
| 407 | } |
Eric Nelson | 2dbe64c | 2013-06-15 16:09:55 -0700 | [diff] [blame] | 408 | invalidate_dcache_range((int)(pp->cmd_slot), |
| 409 | (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 410 | debug("ahci_exec_ata_cmd: %d byte transferred.\n", |
| 411 | pp->cmd_slot->status); |
Eric Nelson | 2dbe64c | 2013-06-15 16:09:55 -0700 | [diff] [blame] | 412 | if (!is_write) |
| 413 | invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 414 | |
| 415 | return buf_len; |
| 416 | } |
| 417 | |
Simon Glass | 47c0f36 | 2017-07-29 11:35:06 -0600 | [diff] [blame] | 418 | static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 419 | { |
Eric Nelson | 2dbe64c | 2013-06-15 16:09:55 -0700 | [diff] [blame] | 420 | struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); |
| 421 | struct sata_fis_h2d *cfis = &h2d; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 422 | |
| 423 | memset(cfis, 0, sizeof(struct sata_fis_h2d)); |
| 424 | cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; |
| 425 | cfis->pm_port_c = 1 << 7; |
| 426 | cfis->command = ATA_CMD_SET_FEATURES; |
| 427 | cfis->features = SETFEATURES_XFER; |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 428 | cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 429 | |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 430 | ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 431 | } |
| 432 | |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 433 | static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 434 | { |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 435 | struct ahci_ioports *pp = &uc_priv->port[port]; |
Simon Glass | 4b640db | 2017-07-29 11:35:05 -0600 | [diff] [blame] | 436 | struct sata_port_regs *port_mmio = pp->port_mmio; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 437 | u32 port_status; |
| 438 | u32 mem; |
| 439 | int timeout = 10000000; |
| 440 | |
| 441 | debug("Enter start port: %d\n", port); |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 442 | port_status = readl(&port_mmio->ssts); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 443 | debug("Port %d status: %x\n", port, port_status); |
| 444 | if ((port_status & 0xf) != 0x03) { |
| 445 | printf("No Link on this port!\n"); |
| 446 | return -1; |
| 447 | } |
| 448 | |
| 449 | mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024); |
| 450 | if (!mem) { |
| 451 | free(pp); |
| 452 | printf("No mem for table!\n"); |
| 453 | return -ENOMEM; |
| 454 | } |
| 455 | |
| 456 | mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */ |
| 457 | memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
| 458 | |
| 459 | /* |
| 460 | * First item in chunk of DMA memory: 32-slot command table, |
| 461 | * 32 bytes each in size |
| 462 | */ |
| 463 | pp->cmd_slot = (struct ahci_cmd_hdr *)mem; |
| 464 | debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot); |
| 465 | mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS); |
| 466 | |
| 467 | /* |
| 468 | * Second item: Received-FIS area, 256-Byte aligned |
| 469 | */ |
| 470 | pp->rx_fis = mem; |
| 471 | mem += AHCI_RX_FIS_SZ; |
| 472 | |
| 473 | /* |
| 474 | * Third item: data area for storing a single command |
| 475 | * and its scatter-gather table |
| 476 | */ |
| 477 | pp->cmd_tbl = mem; |
Tang Yuantian | fa31377 | 2015-07-09 14:37:30 +0800 | [diff] [blame] | 478 | debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 479 | |
| 480 | mem += AHCI_CMD_TBL_HDR; |
| 481 | |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 482 | writel_with_flush(0x00004444, &port_mmio->dmacr); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 483 | pp->cmd_tbl_sg = (struct ahci_sg *)mem; |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 484 | writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb); |
| 485 | writel_with_flush(pp->rx_fis, &port_mmio->fb); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 486 | |
| 487 | /* Enable FRE */ |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 488 | writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)), |
| 489 | &port_mmio->cmd); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 490 | |
| 491 | /* Wait device ready */ |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 492 | while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR | |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 493 | SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY)) |
| 494 | && --timeout) |
| 495 | ; |
| 496 | if (timeout <= 0) { |
| 497 | debug("Device not ready for BSY, DRQ and" |
| 498 | "ERR in TFD!\n"); |
| 499 | return -1; |
| 500 | } |
| 501 | |
| 502 | writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | |
| 503 | PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 504 | PORT_CMD_START, &port_mmio->cmd); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 505 | |
| 506 | debug("Exit start port %d\n", port); |
| 507 | |
| 508 | return 0; |
| 509 | } |
| 510 | |
Simon Glass | 47c0f36 | 2017-07-29 11:35:06 -0600 | [diff] [blame] | 511 | static void dwc_ahsata_print_info(struct blk_desc *pdev) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 512 | { |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 513 | printf("SATA Device Info:\n\r"); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 514 | printf("S/N: %s\n\rProduct model number: %s\n\r" |
Soeren Moch | d5326df | 2019-03-01 13:10:58 +0100 | [diff] [blame^] | 515 | "Firmware version: %s\n\rCapacity: " LBAFU " sectors\n\r", |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 516 | pdev->product, pdev->vendor, pdev->revision, pdev->lba); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 517 | } |
| 518 | |
Simon Glass | 47c0f36 | 2017-07-29 11:35:06 -0600 | [diff] [blame] | 519 | static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 520 | { |
Eric Nelson | 2dbe64c | 2013-06-15 16:09:55 -0700 | [diff] [blame] | 521 | struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); |
| 522 | struct sata_fis_h2d *cfis = &h2d; |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 523 | u8 port = uc_priv->hard_port_no; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 524 | |
| 525 | memset(cfis, 0, sizeof(struct sata_fis_h2d)); |
| 526 | |
| 527 | cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; |
| 528 | cfis->pm_port_c = 0x80; /* is command */ |
| 529 | cfis->command = ATA_CMD_ID_ATA; |
| 530 | |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 531 | ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2, |
| 532 | READ_CMD); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 533 | ata_swap_buf_le16(id, ATA_ID_WORDS); |
| 534 | } |
| 535 | |
Simon Glass | 47c0f36 | 2017-07-29 11:35:06 -0600 | [diff] [blame] | 536 | static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 537 | { |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 538 | uc_priv->pio_mask = id[ATA_ID_PIO_MODES]; |
| 539 | uc_priv->udma_mask = id[ATA_ID_UDMA_MODES]; |
| 540 | debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 541 | } |
| 542 | |
Simon Glass | 47c0f36 | 2017-07-29 11:35:06 -0600 | [diff] [blame] | 543 | static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start, |
| 544 | u32 blkcnt, u8 *buffer, int is_write) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 545 | { |
Eric Nelson | 2dbe64c | 2013-06-15 16:09:55 -0700 | [diff] [blame] | 546 | struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); |
| 547 | struct sata_fis_h2d *cfis = &h2d; |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 548 | u8 port = uc_priv->hard_port_no; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 549 | u32 block; |
| 550 | |
| 551 | block = start; |
| 552 | |
| 553 | memset(cfis, 0, sizeof(struct sata_fis_h2d)); |
| 554 | |
| 555 | cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; |
| 556 | cfis->pm_port_c = 0x80; /* is command */ |
| 557 | cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ; |
| 558 | cfis->device = ATA_LBA; |
| 559 | |
| 560 | cfis->device |= (block >> 24) & 0xf; |
| 561 | cfis->lba_high = (block >> 16) & 0xff; |
| 562 | cfis->lba_mid = (block >> 8) & 0xff; |
| 563 | cfis->lba_low = block & 0xff; |
| 564 | cfis->sector_count = (u8)(blkcnt & 0xff); |
| 565 | |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 566 | if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer, |
| 567 | ATA_SECT_SIZE * blkcnt, is_write) > 0) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 568 | return blkcnt; |
| 569 | else |
| 570 | return 0; |
| 571 | } |
| 572 | |
Simon Glass | 47c0f36 | 2017-07-29 11:35:06 -0600 | [diff] [blame] | 573 | static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 574 | { |
Eric Nelson | 2dbe64c | 2013-06-15 16:09:55 -0700 | [diff] [blame] | 575 | struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); |
| 576 | struct sata_fis_h2d *cfis = &h2d; |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 577 | u8 port = uc_priv->hard_port_no; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 578 | |
| 579 | memset(cfis, 0, sizeof(struct sata_fis_h2d)); |
| 580 | |
| 581 | cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; |
| 582 | cfis->pm_port_c = 0x80; /* is command */ |
| 583 | cfis->command = ATA_CMD_FLUSH; |
| 584 | |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 585 | ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 586 | } |
| 587 | |
Simon Glass | 47c0f36 | 2017-07-29 11:35:06 -0600 | [diff] [blame] | 588 | static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start, |
| 589 | lbaint_t blkcnt, u8 *buffer, int is_write) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 590 | { |
Eric Nelson | 2dbe64c | 2013-06-15 16:09:55 -0700 | [diff] [blame] | 591 | struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); |
| 592 | struct sata_fis_h2d *cfis = &h2d; |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 593 | u8 port = uc_priv->hard_port_no; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 594 | u64 block; |
| 595 | |
| 596 | block = (u64)start; |
| 597 | |
| 598 | memset(cfis, 0, sizeof(struct sata_fis_h2d)); |
| 599 | |
| 600 | cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; |
| 601 | cfis->pm_port_c = 0x80; /* is command */ |
| 602 | |
| 603 | cfis->command = (is_write) ? ATA_CMD_WRITE_EXT |
| 604 | : ATA_CMD_READ_EXT; |
| 605 | |
| 606 | cfis->lba_high_exp = (block >> 40) & 0xff; |
| 607 | cfis->lba_mid_exp = (block >> 32) & 0xff; |
| 608 | cfis->lba_low_exp = (block >> 24) & 0xff; |
| 609 | cfis->lba_high = (block >> 16) & 0xff; |
| 610 | cfis->lba_mid = (block >> 8) & 0xff; |
| 611 | cfis->lba_low = block & 0xff; |
| 612 | cfis->device = ATA_LBA; |
| 613 | cfis->sector_count_exp = (blkcnt >> 8) & 0xff; |
| 614 | cfis->sector_count = blkcnt & 0xff; |
| 615 | |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 616 | if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer, |
| 617 | ATA_SECT_SIZE * blkcnt, is_write) > 0) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 618 | return blkcnt; |
| 619 | else |
| 620 | return 0; |
| 621 | } |
| 622 | |
Simon Glass | 47c0f36 | 2017-07-29 11:35:06 -0600 | [diff] [blame] | 623 | static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 624 | { |
Eric Nelson | 2dbe64c | 2013-06-15 16:09:55 -0700 | [diff] [blame] | 625 | struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); |
| 626 | struct sata_fis_h2d *cfis = &h2d; |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 627 | u8 port = uc_priv->hard_port_no; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 628 | |
| 629 | memset(cfis, 0, sizeof(struct sata_fis_h2d)); |
| 630 | |
| 631 | cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; |
| 632 | cfis->pm_port_c = 0x80; /* is command */ |
| 633 | cfis->command = ATA_CMD_FLUSH_EXT; |
| 634 | |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 635 | ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 636 | } |
| 637 | |
Simon Glass | 47c0f36 | 2017-07-29 11:35:06 -0600 | [diff] [blame] | 638 | static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 639 | { |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 640 | if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id)) |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 641 | uc_priv->flags |= SATA_FLAG_WCACHE; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 642 | if (ata_id_has_flush(id)) |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 643 | uc_priv->flags |= SATA_FLAG_FLUSH; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 644 | if (ata_id_has_flush_ext(id)) |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 645 | uc_priv->flags |= SATA_FLAG_FLUSH_EXT; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 646 | } |
| 647 | |
Simon Glass | 47c0f36 | 2017-07-29 11:35:06 -0600 | [diff] [blame] | 648 | static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr, |
| 649 | lbaint_t blkcnt, const void *buffer, |
| 650 | int is_write) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 651 | { |
| 652 | u32 start, blks; |
| 653 | u8 *addr; |
| 654 | int max_blks; |
| 655 | |
| 656 | start = blknr; |
| 657 | blks = blkcnt; |
| 658 | addr = (u8 *)buffer; |
| 659 | |
| 660 | max_blks = ATA_MAX_SECTORS_LBA48; |
| 661 | |
| 662 | do { |
| 663 | if (blks > max_blks) { |
Simon Glass | 47c0f36 | 2017-07-29 11:35:06 -0600 | [diff] [blame] | 664 | if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, |
| 665 | max_blks, addr, |
| 666 | is_write)) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 667 | return 0; |
| 668 | start += max_blks; |
| 669 | blks -= max_blks; |
| 670 | addr += ATA_SECT_SIZE * max_blks; |
| 671 | } else { |
Simon Glass | 47c0f36 | 2017-07-29 11:35:06 -0600 | [diff] [blame] | 672 | if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks, |
| 673 | addr, is_write)) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 674 | return 0; |
| 675 | start += blks; |
| 676 | blks = 0; |
| 677 | addr += ATA_SECT_SIZE * blks; |
| 678 | } |
| 679 | } while (blks != 0); |
| 680 | |
| 681 | return blkcnt; |
| 682 | } |
| 683 | |
Simon Glass | 47c0f36 | 2017-07-29 11:35:06 -0600 | [diff] [blame] | 684 | static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr, |
| 685 | lbaint_t blkcnt, const void *buffer, |
| 686 | int is_write) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 687 | { |
| 688 | u32 start, blks; |
| 689 | u8 *addr; |
| 690 | int max_blks; |
| 691 | |
| 692 | start = blknr; |
| 693 | blks = blkcnt; |
| 694 | addr = (u8 *)buffer; |
| 695 | |
| 696 | max_blks = ATA_MAX_SECTORS; |
| 697 | do { |
| 698 | if (blks > max_blks) { |
Simon Glass | 47c0f36 | 2017-07-29 11:35:06 -0600 | [diff] [blame] | 699 | if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start, |
| 700 | max_blks, addr, |
| 701 | is_write)) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 702 | return 0; |
| 703 | start += max_blks; |
| 704 | blks -= max_blks; |
| 705 | addr += ATA_SECT_SIZE * max_blks; |
| 706 | } else { |
Simon Glass | 47c0f36 | 2017-07-29 11:35:06 -0600 | [diff] [blame] | 707 | if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks, |
| 708 | addr, is_write)) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 709 | return 0; |
| 710 | start += blks; |
| 711 | blks = 0; |
| 712 | addr += ATA_SECT_SIZE * blks; |
| 713 | } |
| 714 | } while (blks != 0); |
| 715 | |
| 716 | return blkcnt; |
| 717 | } |
| 718 | |
Simon Glass | 752126a | 2017-07-29 11:35:12 -0600 | [diff] [blame] | 719 | static int dwc_ahci_start_ports(struct ahci_uc_priv *uc_priv) |
| 720 | { |
| 721 | u32 linkmap; |
| 722 | int i; |
| 723 | |
| 724 | linkmap = uc_priv->link_port_map; |
| 725 | |
| 726 | if (0 == linkmap) { |
| 727 | printf("No port device detected!\n"); |
| 728 | return -ENXIO; |
| 729 | } |
| 730 | |
| 731 | for (i = 0; i < uc_priv->n_ports; i++) { |
| 732 | if ((linkmap >> i) && ((linkmap >> i) & 0x01)) { |
| 733 | if (ahci_port_start(uc_priv, (u8)i)) { |
| 734 | printf("Can not start port %d\n", i); |
| 735 | return 1; |
| 736 | } |
| 737 | uc_priv->hard_port_no = i; |
| 738 | break; |
| 739 | } |
| 740 | } |
| 741 | |
| 742 | return 0; |
| 743 | } |
| 744 | |
| 745 | static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv, |
| 746 | struct blk_desc *pdev) |
| 747 | { |
| 748 | u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 }; |
| 749 | u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 }; |
| 750 | u8 product[ATA_ID_PROD_LEN + 1] = { 0 }; |
Simon Glass | 752126a | 2017-07-29 11:35:12 -0600 | [diff] [blame] | 751 | u8 port = uc_priv->hard_port_no; |
| 752 | ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS); |
| 753 | |
| 754 | /* Identify device to get information */ |
| 755 | dwc_ahsata_identify(uc_priv, id); |
| 756 | |
| 757 | /* Serial number */ |
| 758 | ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial)); |
| 759 | memcpy(pdev->product, serial, sizeof(serial)); |
| 760 | |
| 761 | /* Firmware version */ |
| 762 | ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware)); |
| 763 | memcpy(pdev->revision, firmware, sizeof(firmware)); |
| 764 | |
| 765 | /* Product model */ |
| 766 | ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product)); |
| 767 | memcpy(pdev->vendor, product, sizeof(product)); |
| 768 | |
Soeren Moch | d5326df | 2019-03-01 13:10:58 +0100 | [diff] [blame^] | 769 | /* Total sectors */ |
| 770 | pdev->lba = ata_id_n_sectors(id); |
Simon Glass | 752126a | 2017-07-29 11:35:12 -0600 | [diff] [blame] | 771 | |
| 772 | pdev->type = DEV_TYPE_HARDDISK; |
| 773 | pdev->blksz = ATA_SECT_SIZE; |
| 774 | pdev->lun = 0; |
| 775 | |
| 776 | /* Check if support LBA48 */ |
| 777 | if (ata_id_has_lba48(id)) { |
| 778 | pdev->lba48 = 1; |
| 779 | debug("Device support LBA48\n\r"); |
| 780 | } |
| 781 | |
| 782 | /* Get the NCQ queue depth from device */ |
| 783 | uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK); |
| 784 | uc_priv->flags |= ata_id_queue_depth(id); |
| 785 | |
| 786 | /* Get the xfer mode from device */ |
| 787 | dwc_ahsata_xfer_mode(uc_priv, id); |
| 788 | |
| 789 | /* Get the write cache status from device */ |
| 790 | dwc_ahsata_init_wcache(uc_priv, id); |
| 791 | |
| 792 | /* Set the xfer mode to highest speed */ |
| 793 | ahci_set_feature(uc_priv, port); |
| 794 | |
| 795 | dwc_ahsata_print_info(pdev); |
| 796 | |
| 797 | return 0; |
| 798 | } |
| 799 | |
| 800 | /* |
| 801 | * SATA interface between low level driver and command layer |
| 802 | */ |
| 803 | static ulong sata_read_common(struct ahci_uc_priv *uc_priv, |
| 804 | struct blk_desc *desc, ulong blknr, |
| 805 | lbaint_t blkcnt, void *buffer) |
| 806 | { |
| 807 | u32 rc; |
| 808 | |
| 809 | if (desc->lba48) |
| 810 | rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer, |
| 811 | READ_CMD); |
| 812 | else |
| 813 | rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer, |
| 814 | READ_CMD); |
| 815 | |
| 816 | return rc; |
| 817 | } |
| 818 | |
| 819 | static ulong sata_write_common(struct ahci_uc_priv *uc_priv, |
| 820 | struct blk_desc *desc, ulong blknr, |
| 821 | lbaint_t blkcnt, const void *buffer) |
| 822 | { |
| 823 | u32 rc; |
| 824 | u32 flags = uc_priv->flags; |
| 825 | |
| 826 | if (desc->lba48) { |
| 827 | rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer, |
| 828 | WRITE_CMD); |
| 829 | if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH_EXT)) |
| 830 | dwc_ahsata_flush_cache_ext(uc_priv); |
| 831 | } else { |
| 832 | rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer, |
| 833 | WRITE_CMD); |
| 834 | if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH)) |
| 835 | dwc_ahsata_flush_cache(uc_priv); |
| 836 | } |
| 837 | |
| 838 | return rc; |
| 839 | } |
| 840 | |
Simon Glass | c893f1e | 2017-07-29 11:35:16 -0600 | [diff] [blame] | 841 | #if !CONFIG_IS_ENABLED(AHCI) |
Simon Glass | 036a803 | 2017-07-29 11:35:11 -0600 | [diff] [blame] | 842 | static int ahci_init_one(int pdev) |
| 843 | { |
| 844 | int rc; |
| 845 | struct ahci_uc_priv *uc_priv = NULL; |
| 846 | |
| 847 | uc_priv = malloc(sizeof(struct ahci_uc_priv)); |
| 848 | memset(uc_priv, 0, sizeof(struct ahci_uc_priv)); |
| 849 | uc_priv->dev = pdev; |
| 850 | |
| 851 | uc_priv->host_flags = ATA_FLAG_SATA |
| 852 | | ATA_FLAG_NO_LEGACY |
| 853 | | ATA_FLAG_MMIO |
| 854 | | ATA_FLAG_PIO_DMA |
| 855 | | ATA_FLAG_NO_ATAPI; |
| 856 | |
| 857 | uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR; |
| 858 | |
| 859 | /* initialize adapter */ |
| 860 | rc = ahci_host_init(uc_priv); |
| 861 | if (rc) |
| 862 | goto err_out; |
| 863 | |
| 864 | ahci_print_info(uc_priv); |
| 865 | |
| 866 | /* Save the uc_private struct to block device struct */ |
| 867 | sata_dev_desc[pdev].priv = uc_priv; |
| 868 | |
| 869 | return 0; |
| 870 | |
| 871 | err_out: |
| 872 | return rc; |
| 873 | } |
| 874 | |
Simon Glass | c5273ac | 2017-07-29 11:35:03 -0600 | [diff] [blame] | 875 | int init_sata(int dev) |
| 876 | { |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 877 | struct ahci_uc_priv *uc_priv = NULL; |
Simon Glass | c5273ac | 2017-07-29 11:35:03 -0600 | [diff] [blame] | 878 | |
| 879 | #if defined(CONFIG_MX6) |
| 880 | if (!is_mx6dq() && !is_mx6dqp()) |
| 881 | return 1; |
| 882 | #endif |
| 883 | if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { |
| 884 | printf("The sata index %d is out of ranges\n\r", dev); |
| 885 | return -1; |
| 886 | } |
| 887 | |
| 888 | ahci_init_one(dev); |
| 889 | |
Simon Glass | 4b640db | 2017-07-29 11:35:05 -0600 | [diff] [blame] | 890 | uc_priv = sata_dev_desc[dev].priv; |
Simon Glass | c5273ac | 2017-07-29 11:35:03 -0600 | [diff] [blame] | 891 | |
Simon Glass | 752126a | 2017-07-29 11:35:12 -0600 | [diff] [blame] | 892 | return dwc_ahci_start_ports(uc_priv) ? 1 : 0; |
Simon Glass | c5273ac | 2017-07-29 11:35:03 -0600 | [diff] [blame] | 893 | } |
| 894 | |
| 895 | int reset_sata(int dev) |
| 896 | { |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 897 | struct ahci_uc_priv *uc_priv; |
Simon Glass | c5273ac | 2017-07-29 11:35:03 -0600 | [diff] [blame] | 898 | struct sata_host_regs *host_mmio; |
| 899 | |
| 900 | if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { |
| 901 | printf("The sata index %d is out of ranges\n\r", dev); |
| 902 | return -1; |
| 903 | } |
| 904 | |
Simon Glass | 4b640db | 2017-07-29 11:35:05 -0600 | [diff] [blame] | 905 | uc_priv = sata_dev_desc[dev].priv; |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 906 | if (NULL == uc_priv) |
Simon Glass | c5273ac | 2017-07-29 11:35:03 -0600 | [diff] [blame] | 907 | /* not initialized, so nothing to reset */ |
| 908 | return 0; |
| 909 | |
Simon Glass | 4b640db | 2017-07-29 11:35:05 -0600 | [diff] [blame] | 910 | host_mmio = uc_priv->mmio_base; |
Simon Glass | c5273ac | 2017-07-29 11:35:03 -0600 | [diff] [blame] | 911 | setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR); |
| 912 | while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) |
| 913 | udelay(100); |
| 914 | |
| 915 | return 0; |
| 916 | } |
| 917 | |
Nikita Kiryanov | dc383dd | 2014-08-20 15:08:53 +0300 | [diff] [blame] | 918 | int sata_port_status(int dev, int port) |
| 919 | { |
| 920 | struct sata_port_regs *port_mmio; |
Simon Glass | 09bb951 | 2017-07-29 11:35:04 -0600 | [diff] [blame] | 921 | struct ahci_uc_priv *uc_priv = NULL; |
Nikita Kiryanov | dc383dd | 2014-08-20 15:08:53 +0300 | [diff] [blame] | 922 | |
| 923 | if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) |
| 924 | return -EINVAL; |
| 925 | |
| 926 | if (sata_dev_desc[dev].priv == NULL) |
| 927 | return -ENODEV; |
| 928 | |
Simon Glass | 4b640db | 2017-07-29 11:35:05 -0600 | [diff] [blame] | 929 | uc_priv = sata_dev_desc[dev].priv; |
| 930 | port_mmio = uc_priv->port[port].port_mmio; |
Nikita Kiryanov | dc383dd | 2014-08-20 15:08:53 +0300 | [diff] [blame] | 931 | |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 932 | return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK; |
Nikita Kiryanov | dc383dd | 2014-08-20 15:08:53 +0300 | [diff] [blame] | 933 | } |
| 934 | |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 935 | /* |
| 936 | * SATA interface between low level driver and command layer |
| 937 | */ |
Tom Rini | dac8757 | 2012-09-29 07:53:06 -0700 | [diff] [blame] | 938 | ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 939 | { |
Simon Glass | 47c0f36 | 2017-07-29 11:35:06 -0600 | [diff] [blame] | 940 | struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 941 | |
Simon Glass | 752126a | 2017-07-29 11:35:12 -0600 | [diff] [blame] | 942 | return sata_read_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt, |
| 943 | buffer); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 944 | } |
| 945 | |
Tom Rini | dac8757 | 2012-09-29 07:53:06 -0700 | [diff] [blame] | 946 | ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer) |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 947 | { |
Simon Glass | 4b640db | 2017-07-29 11:35:05 -0600 | [diff] [blame] | 948 | struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 949 | |
Simon Glass | 752126a | 2017-07-29 11:35:12 -0600 | [diff] [blame] | 950 | return sata_write_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt, |
| 951 | buffer); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 952 | } |
| 953 | |
| 954 | int scan_sata(int dev) |
| 955 | { |
Simon Glass | 4b640db | 2017-07-29 11:35:05 -0600 | [diff] [blame] | 956 | struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; |
Simon Glass | 3e59c30 | 2017-07-29 11:35:07 -0600 | [diff] [blame] | 957 | struct blk_desc *pdev = &sata_dev_desc[dev]; |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 958 | |
Simon Glass | 752126a | 2017-07-29 11:35:12 -0600 | [diff] [blame] | 959 | return dwc_ahsata_scan_common(uc_priv, pdev); |
Stefano Babic | 9f472e6 | 2012-02-22 00:24:39 +0000 | [diff] [blame] | 960 | } |
Simon Glass | c893f1e | 2017-07-29 11:35:16 -0600 | [diff] [blame] | 961 | #endif /* CONFIG_IS_ENABLED(AHCI) */ |
| 962 | |
| 963 | #if CONFIG_IS_ENABLED(AHCI) |
| 964 | |
| 965 | int dwc_ahsata_port_status(struct udevice *dev, int port) |
| 966 | { |
| 967 | struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); |
| 968 | struct sata_port_regs *port_mmio; |
| 969 | |
| 970 | port_mmio = uc_priv->port[port].port_mmio; |
| 971 | return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK ? 0 : -ENXIO; |
| 972 | } |
| 973 | |
| 974 | int dwc_ahsata_bus_reset(struct udevice *dev) |
| 975 | { |
| 976 | struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); |
| 977 | struct sata_host_regs *host_mmio = uc_priv->mmio_base; |
| 978 | |
| 979 | setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR); |
| 980 | while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) |
| 981 | udelay(100); |
| 982 | |
| 983 | return 0; |
| 984 | } |
| 985 | |
| 986 | int dwc_ahsata_scan(struct udevice *dev) |
| 987 | { |
| 988 | struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); |
| 989 | struct blk_desc *desc; |
| 990 | struct udevice *blk; |
| 991 | int ret; |
| 992 | |
| 993 | /* |
| 994 | * Create only one block device and do detection |
| 995 | * to make sure that there won't be a lot of |
| 996 | * block devices created |
| 997 | */ |
| 998 | device_find_first_child(dev, &blk); |
| 999 | if (!blk) { |
| 1000 | ret = blk_create_devicef(dev, "dwc_ahsata_blk", "blk", |
| 1001 | IF_TYPE_SATA, -1, 512, 0, &blk); |
| 1002 | if (ret) { |
| 1003 | debug("Can't create device\n"); |
| 1004 | return ret; |
| 1005 | } |
| 1006 | } |
| 1007 | |
| 1008 | desc = dev_get_uclass_platdata(blk); |
| 1009 | ret = dwc_ahsata_scan_common(uc_priv, desc); |
| 1010 | if (ret) { |
| 1011 | debug("%s: Failed to scan bus\n", __func__); |
| 1012 | return ret; |
| 1013 | } |
| 1014 | |
| 1015 | return 0; |
| 1016 | } |
| 1017 | |
| 1018 | int dwc_ahsata_probe(struct udevice *dev) |
| 1019 | { |
| 1020 | struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); |
| 1021 | int ret; |
| 1022 | |
| 1023 | uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
| 1024 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI; |
| 1025 | uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev); |
| 1026 | |
| 1027 | /* initialize adapter */ |
| 1028 | ret = ahci_host_init(uc_priv); |
| 1029 | if (ret) |
| 1030 | return ret; |
| 1031 | |
| 1032 | ahci_print_info(uc_priv); |
| 1033 | |
| 1034 | return dwc_ahci_start_ports(uc_priv); |
| 1035 | } |
| 1036 | |
| 1037 | static ulong dwc_ahsata_read(struct udevice *blk, lbaint_t blknr, |
| 1038 | lbaint_t blkcnt, void *buffer) |
| 1039 | { |
| 1040 | struct blk_desc *desc = dev_get_uclass_platdata(blk); |
| 1041 | struct udevice *dev = dev_get_parent(blk); |
| 1042 | struct ahci_uc_priv *uc_priv; |
| 1043 | |
| 1044 | uc_priv = dev_get_uclass_priv(dev); |
| 1045 | return sata_read_common(uc_priv, desc, blknr, blkcnt, buffer); |
| 1046 | } |
| 1047 | |
| 1048 | static ulong dwc_ahsata_write(struct udevice *blk, lbaint_t blknr, |
| 1049 | lbaint_t blkcnt, const void *buffer) |
| 1050 | { |
| 1051 | struct blk_desc *desc = dev_get_uclass_platdata(blk); |
| 1052 | struct udevice *dev = dev_get_parent(blk); |
| 1053 | struct ahci_uc_priv *uc_priv; |
| 1054 | |
| 1055 | uc_priv = dev_get_uclass_priv(dev); |
| 1056 | return sata_write_common(uc_priv, desc, blknr, blkcnt, buffer); |
| 1057 | } |
| 1058 | |
| 1059 | static const struct blk_ops dwc_ahsata_blk_ops = { |
| 1060 | .read = dwc_ahsata_read, |
| 1061 | .write = dwc_ahsata_write, |
| 1062 | }; |
| 1063 | |
| 1064 | U_BOOT_DRIVER(dwc_ahsata_blk) = { |
| 1065 | .name = "dwc_ahsata_blk", |
| 1066 | .id = UCLASS_BLK, |
| 1067 | .ops = &dwc_ahsata_blk_ops, |
| 1068 | }; |
| 1069 | |
| 1070 | #endif |