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Sergey Kubushync74b2102007-08-10 20:26:18 +02001/*
2 * Ethernet driver for TI TMS320DM644x (DaVinci) chips.
3 *
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
5 *
6 * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
7 * follows:
8 *
9 * ----------------------------------------------------------------------------
10 *
11 * dm644x_emac.c
12 *
13 * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
14 *
15 * Copyright (C) 2005 Texas Instruments.
16 *
17 * ----------------------------------------------------------------------------
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32 * ----------------------------------------------------------------------------
33
34 * Modifications:
35 * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
36 * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
37 *
38 */
39#include <common.h>
40#include <command.h>
41#include <net.h>
42#include <miiphy.h>
Ben Warren84535872009-05-26 00:34:07 -070043#include <malloc.h>
Sergey Kubushync74b2102007-08-10 20:26:18 +020044#include <asm/arch/emac_defs.h>
45
Sergey Kubushync74b2102007-08-10 20:26:18 +020046unsigned int emac_dbg = 0;
47#define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
48
Sandeep Paulrajfcaac582008-08-31 00:39:46 +020049static void davinci_eth_mdio_enable(void);
Sergey Kubushync74b2102007-08-10 20:26:18 +020050
51static int gen_init_phy(int phy_addr);
52static int gen_is_phy_connected(int phy_addr);
53static int gen_get_link_speed(int phy_addr);
54static int gen_auto_negotiate(int phy_addr);
55
Sergey Kubushync74b2102007-08-10 20:26:18 +020056void eth_mdio_enable(void)
57{
Sandeep Paulrajfcaac582008-08-31 00:39:46 +020058 davinci_eth_mdio_enable();
Sergey Kubushync74b2102007-08-10 20:26:18 +020059}
Sergey Kubushync74b2102007-08-10 20:26:18 +020060
Sandeep Paulrajfcaac582008-08-31 00:39:46 +020061static u_int8_t davinci_eth_mac_addr[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
Sergey Kubushync74b2102007-08-10 20:26:18 +020062
63/*
64 * This function must be called before emac_open() if you want to override
65 * the default mac address.
66 */
Sandeep Paulrajfcaac582008-08-31 00:39:46 +020067void davinci_eth_set_mac_addr(const u_int8_t *addr)
Sergey Kubushync74b2102007-08-10 20:26:18 +020068{
69 int i;
70
Sandeep Paulrajfcaac582008-08-31 00:39:46 +020071 for (i = 0; i < sizeof (davinci_eth_mac_addr); i++) {
72 davinci_eth_mac_addr[i] = addr[i];
Sergey Kubushync74b2102007-08-10 20:26:18 +020073 }
74}
75
76/* EMAC Addresses */
77static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
78static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
79static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;
80
81/* EMAC descriptors */
82static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
83static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
84static volatile emac_desc *emac_rx_active_head = 0;
85static volatile emac_desc *emac_rx_active_tail = 0;
86static int emac_rx_queue_active = 0;
87
88/* Receive packet buffers */
89static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
90
91/* PHY address for a discovered PHY (0xff - not found) */
92static volatile u_int8_t active_phy_addr = 0xff;
93
94phy_t phy;
95
Sandeep Paulrajfcaac582008-08-31 00:39:46 +020096static void davinci_eth_mdio_enable(void)
Sergey Kubushync74b2102007-08-10 20:26:18 +020097{
98 u_int32_t clkdiv;
99
100 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
101
102 adap_mdio->CONTROL = (clkdiv & 0xff) |
103 MDIO_CONTROL_ENABLE |
104 MDIO_CONTROL_FAULT |
105 MDIO_CONTROL_FAULT_ENABLE;
106
107 while (adap_mdio->CONTROL & MDIO_CONTROL_IDLE) {;}
108}
109
110/*
111 * Tries to find an active connected PHY. Returns 1 if address if found.
112 * If no active PHY (or more than one PHY) found returns 0.
113 * Sets active_phy_addr variable.
114 */
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200115static int davinci_eth_phy_detect(void)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200116{
117 u_int32_t phy_act_state;
118 int i;
119
120 active_phy_addr = 0xff;
121
122 if ((phy_act_state = adap_mdio->ALIVE) == 0)
123 return(0); /* No active PHYs */
124
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200125 debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200126
127 for (i = 0; i < 32; i++) {
128 if (phy_act_state & (1 << i)) {
129 if (phy_act_state & ~(1 << i))
130 return(0); /* More than one PHY */
131 else {
132 active_phy_addr = i;
133 return(1);
134 }
135 }
136 }
137
138 return(0); /* Just to make GCC happy */
139}
140
141
142/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200143int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200144{
145 int tmp;
146
147 while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;}
148
149 adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO |
150 MDIO_USERACCESS0_WRITE_READ |
151 ((reg_num & 0x1f) << 21) |
152 ((phy_addr & 0x1f) << 16);
153
154 /* Wait for command to complete */
155 while ((tmp = adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) {;}
156
157 if (tmp & MDIO_USERACCESS0_ACK) {
158 *data = tmp & 0xffff;
159 return(1);
160 }
161
162 *data = -1;
163 return(0);
164}
165
166/* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200167int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200168{
169
170 while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;}
171
172 adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO |
173 MDIO_USERACCESS0_WRITE_WRITE |
174 ((reg_num & 0x1f) << 21) |
175 ((phy_addr & 0x1f) << 16) |
176 (data & 0xffff);
177
178 /* Wait for command to complete */
179 while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;}
180
181 return(1);
182}
183
184/* PHY functions for a generic PHY */
185static int gen_init_phy(int phy_addr)
186{
187 int ret = 1;
188
189 if (gen_get_link_speed(phy_addr)) {
190 /* Try another time */
191 ret = gen_get_link_speed(phy_addr);
192 }
193
194 return(ret);
195}
196
197static int gen_is_phy_connected(int phy_addr)
198{
199 u_int16_t dummy;
200
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200201 return(davinci_eth_phy_read(phy_addr, PHY_PHYIDR1, &dummy));
Sergey Kubushync74b2102007-08-10 20:26:18 +0200202}
203
204static int gen_get_link_speed(int phy_addr)
205{
206 u_int16_t tmp;
207
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200208 if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && (tmp & 0x04))
Sergey Kubushync74b2102007-08-10 20:26:18 +0200209 return(1);
210
211 return(0);
212}
213
214static int gen_auto_negotiate(int phy_addr)
215{
216 u_int16_t tmp;
217
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200218 if (!davinci_eth_phy_read(phy_addr, PHY_BMCR, &tmp))
Sergey Kubushync74b2102007-08-10 20:26:18 +0200219 return(0);
220
221 /* Restart Auto_negotiation */
222 tmp |= PHY_BMCR_AUTON;
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200223 davinci_eth_phy_write(phy_addr, PHY_BMCR, tmp);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200224
225 /*check AutoNegotiate complete */
226 udelay (10000);
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200227 if (!davinci_eth_phy_read(phy_addr, PHY_BMSR, &tmp))
Sergey Kubushync74b2102007-08-10 20:26:18 +0200228 return(0);
229
230 if (!(tmp & PHY_BMSR_AUTN_COMP))
231 return(0);
232
233 return(gen_get_link_speed(phy_addr));
234}
235/* End of generic PHY functions */
236
237
Wolfgang Denkafaac862007-08-12 14:27:39 +0200238#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200239static int davinci_mii_phy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short *value)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200240{
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200241 return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200242}
243
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200244static int davinci_mii_phy_write(char *devname, unsigned char addr, unsigned char reg, unsigned short value)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200245{
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200246 return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200247}
248
Sergey Kubushync74b2102007-08-10 20:26:18 +0200249#endif
250
Sergey Kubushync74b2102007-08-10 20:26:18 +0200251
252/* Eth device open */
Ben Warren84535872009-05-26 00:34:07 -0700253static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200254{
255 dv_reg_p addr;
256 u_int32_t clkdiv, cnt;
257 volatile emac_desc *rx_desc;
258
259 debug_emac("+ emac_open\n");
260
261 /* Reset EMAC module and disable interrupts in wrapper */
262 adap_emac->SOFTRESET = 1;
263 while (adap_emac->SOFTRESET != 0) {;}
264 adap_ewrap->EWCTL = 0;
265 for (cnt = 0; cnt < 5; cnt++) {
266 clkdiv = adap_ewrap->EWCTL;
267 }
268
269 rx_desc = emac_rx_desc;
270
271 adap_emac->TXCONTROL = 0x01;
272 adap_emac->RXCONTROL = 0x01;
273
274 /* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast receive) */
275 /* Using channel 0 only - other channels are disabled */
276 adap_emac->MACINDEX = 0;
277 adap_emac->MACADDRHI =
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200278 (davinci_eth_mac_addr[3] << 24) |
279 (davinci_eth_mac_addr[2] << 16) |
280 (davinci_eth_mac_addr[1] << 8) |
281 (davinci_eth_mac_addr[0]);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200282 adap_emac->MACADDRLO =
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200283 (davinci_eth_mac_addr[5] << 8) |
284 (davinci_eth_mac_addr[4]);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200285
286 adap_emac->MACHASH1 = 0;
287 adap_emac->MACHASH2 = 0;
288
289 /* Set source MAC address - REQUIRED */
290 adap_emac->MACSRCADDRHI =
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200291 (davinci_eth_mac_addr[3] << 24) |
292 (davinci_eth_mac_addr[2] << 16) |
293 (davinci_eth_mac_addr[1] << 8) |
294 (davinci_eth_mac_addr[0]);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200295 adap_emac->MACSRCADDRLO =
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200296 (davinci_eth_mac_addr[4] << 8) |
297 (davinci_eth_mac_addr[5]);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200298
299 /* Set DMA 8 TX / 8 RX Head pointers to 0 */
300 addr = &adap_emac->TX0HDP;
301 for(cnt = 0; cnt < 16; cnt++)
302 *addr++ = 0;
303
304 addr = &adap_emac->RX0HDP;
305 for(cnt = 0; cnt < 16; cnt++)
306 *addr++ = 0;
307
308 /* Clear Statistics (do this before setting MacControl register) */
309 addr = &adap_emac->RXGOODFRAMES;
310 for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
311 *addr++ = 0;
312
313 /* No multicast addressing */
314 adap_emac->MACHASH1 = 0;
315 adap_emac->MACHASH2 = 0;
316
317 /* Create RX queue and set receive process in place */
318 emac_rx_active_head = emac_rx_desc;
319 for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
320 rx_desc->next = (u_int32_t)(rx_desc + 1);
321 rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
322 rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
323 rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
324 rx_desc++;
325 }
326
327 /* Set the last descriptor's "next" parameter to 0 to end the RX desc list */
328 rx_desc--;
329 rx_desc->next = 0;
330 emac_rx_active_tail = rx_desc;
331 emac_rx_queue_active = 1;
332
333 /* Enable TX/RX */
334 adap_emac->RXMAXLEN = EMAC_MAX_ETHERNET_PKT_SIZE;
335 adap_emac->RXBUFFEROFFSET = 0;
336
337 /* No fancy configs - Use this for promiscous for debug - EMAC_RXMBPENABLE_RXCAFEN_ENABLE */
338 adap_emac->RXMBPENABLE = EMAC_RXMBPENABLE_RXBROADEN;
339
340 /* Enable ch 0 only */
341 adap_emac->RXUNICASTSET = 0x01;
342
343 /* Enable MII interface and Full duplex mode */
344 adap_emac->MACCONTROL = (EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE);
345
346 /* Init MDIO & get link state */
347 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
348 adap_mdio->CONTROL = ((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT);
349
350 if (!phy.get_link_speed(active_phy_addr))
351 return(0);
352
353 /* Start receive process */
354 adap_emac->RX0HDP = (u_int32_t)emac_rx_desc;
355
356 debug_emac("- emac_open\n");
357
358 return(1);
359}
360
361/* EMAC Channel Teardown */
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200362static void davinci_eth_ch_teardown(int ch)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200363{
364 dv_reg dly = 0xff;
365 dv_reg cnt;
366
367 debug_emac("+ emac_ch_teardown\n");
368
369 if (ch == EMAC_CH_TX) {
370 /* Init TX channel teardown */
371 adap_emac->TXTEARDOWN = 1;
372 for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->TX0CP) {
373 /* Wait here for Tx teardown completion interrupt to occur
374 * Note: A task delay can be called here to pend rather than
375 * occupying CPU cycles - anyway it has been found that teardown
376 * takes very few cpu cycles and does not affect functionality */
377 dly--;
378 udelay(1);
379 if (dly == 0)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200380 break;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200381 }
382 adap_emac->TX0CP = cnt;
383 adap_emac->TX0HDP = 0;
384 } else {
385 /* Init RX channel teardown */
386 adap_emac->RXTEARDOWN = 1;
387 for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->RX0CP) {
388 /* Wait here for Rx teardown completion interrupt to occur
389 * Note: A task delay can be called here to pend rather than
390 * occupying CPU cycles - anyway it has been found that teardown
391 * takes very few cpu cycles and does not affect functionality */
392 dly--;
393 udelay(1);
394 if (dly == 0)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200395 break;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200396 }
397 adap_emac->RX0CP = cnt;
398 adap_emac->RX0HDP = 0;
399 }
400
401 debug_emac("- emac_ch_teardown\n");
402}
403
404/* Eth device close */
Ben Warren84535872009-05-26 00:34:07 -0700405static void davinci_eth_close(struct eth_device *dev)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200406{
407 debug_emac("+ emac_close\n");
408
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200409 davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */
410 davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */
Sergey Kubushync74b2102007-08-10 20:26:18 +0200411
412 /* Reset EMAC module and disable interrupts in wrapper */
413 adap_emac->SOFTRESET = 1;
414 adap_ewrap->EWCTL = 0;
415
416 debug_emac("- emac_close\n");
Sergey Kubushync74b2102007-08-10 20:26:18 +0200417}
418
419static int tx_send_loop = 0;
420
421/*
422 * This function sends a single packet on the network and returns
423 * positive number (number of bytes transmitted) or negative for error
424 */
Ben Warren84535872009-05-26 00:34:07 -0700425static int davinci_eth_send_packet (struct eth_device *dev,
426 volatile void *packet, int length)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200427{
428 int ret_status = -1;
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200429
Sergey Kubushync74b2102007-08-10 20:26:18 +0200430 tx_send_loop = 0;
431
432 /* Return error if no link */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200433 if (!phy.get_link_speed (active_phy_addr)) {
434 printf ("WARN: emac_send_packet: No link\n");
Sergey Kubushync74b2102007-08-10 20:26:18 +0200435 return (ret_status);
436 }
437
438 /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200439 if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
Sergey Kubushync74b2102007-08-10 20:26:18 +0200440 length = EMAC_MIN_ETHERNET_PKT_SIZE;
441 }
442
443 /* Populate the TX descriptor */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200444 emac_tx_desc->next = 0;
445 emac_tx_desc->buffer = (u_int8_t *) packet;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200446 emac_tx_desc->buff_off_len = (length & 0xffff);
447 emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200448 EMAC_CPPI_SOP_BIT |
449 EMAC_CPPI_OWNERSHIP_BIT |
450 EMAC_CPPI_EOP_BIT);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200451 /* Send the packet */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200452 adap_emac->TX0HDP = (unsigned int) emac_tx_desc;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200453
454 /* Wait for packet to complete or link down */
455 while (1) {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200456 if (!phy.get_link_speed (active_phy_addr)) {
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200457 davinci_eth_ch_teardown (EMAC_CH_TX);
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200458 return (ret_status);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200459 }
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200460 if (adap_emac->TXINTSTATRAW & 0x01) {
461 ret_status = length;
462 break;
463 }
464 tx_send_loop++;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200465 }
466
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200467 return (ret_status);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200468}
469
470/*
471 * This function handles receipt of a packet from the network
472 */
Ben Warren84535872009-05-26 00:34:07 -0700473static int davinci_eth_rcv_packet (struct eth_device *dev)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200474{
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200475 volatile emac_desc *rx_curr_desc;
476 volatile emac_desc *curr_desc;
477 volatile emac_desc *tail_desc;
478 int status, ret = -1;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200479
480 rx_curr_desc = emac_rx_active_head;
481 status = rx_curr_desc->pkt_flag_len;
482 if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200483 if (status & EMAC_CPPI_RX_ERROR_FRAME) {
484 /* Error in packet - discard it and requeue desc */
485 printf ("WARN: emac_rcv_pkt: Error in packet\n");
Sergey Kubushync74b2102007-08-10 20:26:18 +0200486 } else {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200487 NetReceive (rx_curr_desc->buffer,
488 (rx_curr_desc->buff_off_len & 0xffff));
Sergey Kubushync74b2102007-08-10 20:26:18 +0200489 ret = rx_curr_desc->buff_off_len & 0xffff;
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200490 }
Sergey Kubushync74b2102007-08-10 20:26:18 +0200491
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200492 /* Ack received packet descriptor */
493 adap_emac->RX0CP = (unsigned int) rx_curr_desc;
494 curr_desc = rx_curr_desc;
495 emac_rx_active_head =
496 (volatile emac_desc *) rx_curr_desc->next;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200497
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200498 if (status & EMAC_CPPI_EOQ_BIT) {
499 if (emac_rx_active_head) {
500 adap_emac->RX0HDP =
501 (unsigned int) emac_rx_active_head;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200502 } else {
503 emac_rx_queue_active = 0;
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200504 printf ("INFO:emac_rcv_packet: RX Queue not active\n");
Sergey Kubushync74b2102007-08-10 20:26:18 +0200505 }
506 }
507
508 /* Recycle RX descriptor */
509 rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
510 rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
511 rx_curr_desc->next = 0;
512
513 if (emac_rx_active_head == 0) {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200514 printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
Sergey Kubushync74b2102007-08-10 20:26:18 +0200515 emac_rx_active_head = curr_desc;
516 emac_rx_active_tail = curr_desc;
517 if (emac_rx_queue_active != 0) {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200518 adap_emac->RX0HDP =
519 (unsigned int) emac_rx_active_head;
520 printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
Sergey Kubushync74b2102007-08-10 20:26:18 +0200521 emac_rx_queue_active = 1;
522 }
523 } else {
524 tail_desc = emac_rx_active_tail;
525 emac_rx_active_tail = curr_desc;
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200526 tail_desc->next = (unsigned int) curr_desc;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200527 status = tail_desc->pkt_flag_len;
528 if (status & EMAC_CPPI_EOQ_BIT) {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200529 adap_emac->RX0HDP = (unsigned int) curr_desc;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200530 status &= ~EMAC_CPPI_EOQ_BIT;
531 tail_desc->pkt_flag_len = status;
532 }
533 }
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200534 return (ret);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200535 }
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200536 return (0);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200537}
538
Ben Warren8cc13c12009-04-27 23:19:10 -0700539/*
540 * This function initializes the emac hardware. It does NOT initialize
541 * EMAC modules power or pin multiplexors, that is done by board_init()
542 * much earlier in bootup process. Returns 1 on success, 0 otherwise.
543 */
Ben Warren84535872009-05-26 00:34:07 -0700544int davinci_emac_initialize(void)
Ben Warren8cc13c12009-04-27 23:19:10 -0700545{
546 u_int32_t phy_id;
547 u_int16_t tmp;
548 int i;
Ben Warren84535872009-05-26 00:34:07 -0700549 struct eth_device *dev;
550
551 dev = malloc(sizeof *dev);
552
553 if (dev == NULL)
554 return -1;
555
556 memset(dev, 0, sizeof *dev);
557
558 dev->iobase = 0;
559 dev->init = davinci_eth_open;
560 dev->halt = davinci_eth_close;
561 dev->send = davinci_eth_send_packet;
562 dev->recv = davinci_eth_rcv_packet;
563
564 eth_register(dev);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200565
Ben Warren8cc13c12009-04-27 23:19:10 -0700566 davinci_eth_mdio_enable();
567
568 for (i = 0; i < 256; i++) {
569 if (adap_mdio->ALIVE)
570 break;
571 udelay(10);
572 }
573
574 if (i >= 256) {
575 printf("No ETH PHY detected!!!\n");
576 return(0);
577 }
578
579 /* Find if a PHY is connected and get it's address */
580 if (!davinci_eth_phy_detect())
581 return(0);
582
583 /* Get PHY ID and initialize phy_ops for a detected PHY */
584 if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR1, &tmp)) {
585 active_phy_addr = 0xff;
586 return(0);
587 }
588
589 phy_id = (tmp << 16) & 0xffff0000;
590
591 if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR2, &tmp)) {
592 active_phy_addr = 0xff;
593 return(0);
594 }
595
596 phy_id |= tmp & 0x0000ffff;
597
598 switch (phy_id) {
599 case PHY_LXT972:
600 sprintf(phy.name, "LXT972 @ 0x%02x", active_phy_addr);
601 phy.init = lxt972_init_phy;
602 phy.is_phy_connected = lxt972_is_phy_connected;
603 phy.get_link_speed = lxt972_get_link_speed;
604 phy.auto_negotiate = lxt972_auto_negotiate;
605 break;
606 case PHY_DP83848:
607 sprintf(phy.name, "DP83848 @ 0x%02x", active_phy_addr);
608 phy.init = dp83848_init_phy;
609 phy.is_phy_connected = dp83848_is_phy_connected;
610 phy.get_link_speed = dp83848_get_link_speed;
611 phy.auto_negotiate = dp83848_auto_negotiate;
612 break;
613 default:
614 sprintf(phy.name, "GENERIC @ 0x%02x", active_phy_addr);
615 phy.init = gen_init_phy;
616 phy.is_phy_connected = gen_is_phy_connected;
617 phy.get_link_speed = gen_get_link_speed;
618 phy.auto_negotiate = gen_auto_negotiate;
619 }
620
621 printf("Ethernet PHY: %s\n", phy.name);
622
Ben Warren84535872009-05-26 00:34:07 -0700623 miiphy_register(phy.name, davinci_mii_phy_read, davinci_mii_phy_write);
Ben Warren8cc13c12009-04-27 23:19:10 -0700624 return(1);
625}