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wdenkc6097192002-11-03 00:24:07 +00001/*
stroese6f4474e2003-03-20 15:31:19 +00002 * (C) Copyright 2001-2003
wdenkc6097192002-11-03 00:24:07 +00003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/processor.h>
26#include <command.h>
wdenkc6097192002-11-03 00:24:07 +000027#include <malloc.h>
stroese87663b12004-12-16 18:27:05 +000028#include <net.h>
wdenkc6097192002-11-03 00:24:07 +000029
30/* ------------------------------------------------------------------------- */
wdenk8bde7f72003-06-27 21:31:46 +000031extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/
wdenkc6097192002-11-03 00:24:07 +000032#if 0
33#define FPGA_DEBUG
34#endif
35
36/* fpga configuration data - generated by bin2cc */
37const unsigned char fpgadata[] =
38{
39#ifdef CONFIG_CPCI405_VER2
stroesed4629c82003-05-23 11:30:39 +000040# ifdef CONFIG_CPCI405AB
41# include "fpgadata_cpci405ab.c"
42# else
43# include "fpgadata_cpci4052.c"
44# endif
wdenkc6097192002-11-03 00:24:07 +000045#else
46# include "fpgadata_cpci405.c"
47#endif
48};
49
50/*
51 * include common fpga code (for esd boards)
52 */
53#include "../common/fpga.c"
54
55
stroese87663b12004-12-16 18:27:05 +000056#include "../common/auto_update.h"
57
58#ifdef CONFIG_CPCI405AB
59au_image_t au_image[] = {
60 {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
61 {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
62 {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
63 {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
64 {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
65};
66#else
67#ifdef CONFIG_CPCI405_VER2
68au_image_t au_image[] = {
69 {"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
70 {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
71 {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
72 {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
73 {"cpci4052/postinst.img", 0, 0, AU_SCRIPT},
74};
75#else
76au_image_t au_image[] = {
77 {"cpci405/preinst.img", 0, -1, AU_SCRIPT},
78 {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR},
79 {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR},
80 {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE},
81 {"cpci405/postinst.img", 0, 0, AU_SCRIPT},
82};
83#endif
84#endif
85
86int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
87
88
wdenkc6097192002-11-03 00:24:07 +000089/* Prototypes */
stroese6f4474e2003-03-20 15:31:19 +000090int cpci405_version(void);
wdenkeedcd072004-09-08 22:03:11 +000091int gunzip(void *, int, unsigned char *, unsigned long *);
stroese87663b12004-12-16 18:27:05 +000092void lxt971_no_sleep(void);
wdenkc6097192002-11-03 00:24:07 +000093
94
wdenkc837dcb2004-01-20 23:12:12 +000095int board_early_init_f (void)
wdenkc6097192002-11-03 00:24:07 +000096{
97#ifndef CONFIG_CPCI405_VER2
98 int index, len, i;
99 int status;
100#endif
101
102#ifdef FPGA_DEBUG
103 DECLARE_GLOBAL_DATA_PTR;
104
105 /* set up serial port with default baudrate */
106 (void) get_clocks ();
107 gd->baudrate = CONFIG_BAUDRATE;
108 serial_init ();
109 console_init_f();
110#endif
111
112 /*
113 * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
114 */
stroesed4629c82003-05-23 11:30:39 +0000115 out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
116 out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
117 out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
118 out32(GPIO0_OR, 0); /* pull prg low */
wdenkc6097192002-11-03 00:24:07 +0000119
120 /*
121 * Boot onboard FPGA
122 */
123#ifndef CONFIG_CPCI405_VER2
stroese6f4474e2003-03-20 15:31:19 +0000124 if (cpci405_version() == 1) {
wdenkc6097192002-11-03 00:24:07 +0000125 status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
126 if (status != 0) {
127 /* booting FPGA failed */
128#ifndef FPGA_DEBUG
129 DECLARE_GLOBAL_DATA_PTR;
130
131 /* set up serial port with default baudrate */
132 (void) get_clocks ();
133 gd->baudrate = CONFIG_BAUDRATE;
134 serial_init ();
135 console_init_f();
136#endif
137 printf("\nFPGA: Booting failed ");
138 switch (status) {
139 case ERROR_FPGA_PRG_INIT_LOW:
140 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
141 break;
142 case ERROR_FPGA_PRG_INIT_HIGH:
143 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
144 break;
145 case ERROR_FPGA_PRG_DONE:
146 printf("(Timeout: DONE not high after programming FPGA)\n ");
147 break;
148 }
149
150 /* display infos on fpgaimage */
151 index = 15;
152 for (i=0; i<4; i++) {
153 len = fpgadata[index];
154 printf("FPGA: %s\n", &(fpgadata[index+1]));
155 index += len+3;
156 }
157 putc ('\n');
158 /* delayed reboot */
159 for (i=20; i>0; i--) {
160 printf("Rebooting in %2d seconds \r",i);
161 for (index=0;index<1000;index++)
162 udelay(1000);
163 }
164 putc ('\n');
165 do_reset(NULL, 0, 0, NULL);
166 }
167 }
168#endif /* !CONFIG_CPCI405_VER2 */
169
170 /*
171 * IRQ 0-15 405GP internally generated; active high; level sensitive
172 * IRQ 16 405GP internally generated; active low; level sensitive
173 * IRQ 17-24 RESERVED
174 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
175 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive
176 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
177 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
178 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
179 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
180 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
181 */
182 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
183 mtdcr(uicer, 0x00000000); /* disable all ints */
184 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
stroese6f4474e2003-03-20 15:31:19 +0000185 if (cpci405_version() == 3) {
186 mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
187 } else {
188 mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
189 }
wdenkc6097192002-11-03 00:24:07 +0000190 mtdcr(uictr, 0x10000000); /* set int trigger levels */
191 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
192 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
193
194 return 0;
195}
196
197
198/* ------------------------------------------------------------------------- */
199
200int ctermm2(void)
201{
202#ifdef CONFIG_CPCI405_VER2
203 return 0; /* no, board is cpci405 */
204#else
205 if ((*(unsigned char *)0xf0000400 == 0x00) &&
206 (*(unsigned char *)0xf0000401 == 0x01))
207 return 0; /* no, board is cpci405 */
208 else
209 return -1; /* yes, board is cterm-m2 */
210#endif
211}
212
213
214int cpci405_host(void)
215{
216 if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
217 return -1; /* yes, board is cpci405 host */
218 else
219 return 0; /* no, board is cpci405 adapter */
220}
221
222
stroese6f4474e2003-03-20 15:31:19 +0000223int cpci405_version(void)
wdenkc6097192002-11-03 00:24:07 +0000224{
225 unsigned long cntrl0Reg;
226 unsigned long value;
227
228 /*
stroese6f4474e2003-03-20 15:31:19 +0000229 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
wdenkc6097192002-11-03 00:24:07 +0000230 */
231 cntrl0Reg = mfdcr(cntrl0);
stroese6f4474e2003-03-20 15:31:19 +0000232 mtdcr(cntrl0, cntrl0Reg | 0x03000000);
stroesed4629c82003-05-23 11:30:39 +0000233 out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
234 out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
wdenkc6097192002-11-03 00:24:07 +0000235 udelay(1000); /* wait some time before reading input */
stroesed4629c82003-05-23 11:30:39 +0000236 value = in32(GPIO0_IR) & 0x00180000; /* get config bits */
wdenkc6097192002-11-03 00:24:07 +0000237
238 /*
stroese6f4474e2003-03-20 15:31:19 +0000239 * Restore GPIO settings
wdenkc6097192002-11-03 00:24:07 +0000240 */
241 mtdcr(cntrl0, cntrl0Reg);
242
stroese6f4474e2003-03-20 15:31:19 +0000243 switch (value) {
244 case 0x00180000:
245 /* CS2==1 && CS3==1 -> version 1 */
246 return 1;
247 case 0x00080000:
248 /* CS2==0 && CS3==1 -> version 2 */
249 return 2;
250 case 0x00100000:
251 /* CS2==1 && CS3==0 -> version 3 */
252 return 3;
253 case 0x00000000:
254 /* CS2==0 && CS3==0 -> version 4 */
255 return 4;
256 default:
257 /* should not be reached! */
258 return 2;
259 }
wdenkc6097192002-11-03 00:24:07 +0000260}
261
262
263int misc_init_f (void)
264{
265 return 0; /* dummy implementation */
266}
267
268
269int misc_init_r (void)
270{
271 DECLARE_GLOBAL_DATA_PTR;
stroeseafcc4a72003-04-04 16:52:57 +0000272 unsigned long cntrl0Reg;
wdenkc6097192002-11-03 00:24:07 +0000273
stroese87663b12004-12-16 18:27:05 +0000274 /* adjust flash start and offset */
275 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
276 gd->bd->bi_flashoffset = 0;
277
wdenkc6097192002-11-03 00:24:07 +0000278#ifdef CONFIG_CPCI405_VER2
stroese87663b12004-12-16 18:27:05 +0000279 {
wdenkc6097192002-11-03 00:24:07 +0000280 unsigned char *dst;
281 ulong len = sizeof(fpgadata);
282 int status;
283 int index;
284 int i;
wdenkc6097192002-11-03 00:24:07 +0000285
286 /*
287 * On CPCI-405 version 2 the environment is saved in eeprom!
288 * FPGA can be gzip compressed (malloc) and booted this late.
289 */
290
stroese6f4474e2003-03-20 15:31:19 +0000291 if (cpci405_version() >= 2) {
wdenkc6097192002-11-03 00:24:07 +0000292 /*
293 * Setup GPIO pins (CS6+CS7 as GPIO)
294 */
295 cntrl0Reg = mfdcr(cntrl0);
296 mtdcr(cntrl0, cntrl0Reg | 0x00300000);
297
298 dst = malloc(CFG_FPGA_MAX_SIZE);
wdenkeedcd072004-09-08 22:03:11 +0000299 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
wdenkc6097192002-11-03 00:24:07 +0000300 printf ("GUNZIP ERROR - must RESET board to recover\n");
301 do_reset (NULL, 0, 0, NULL);
302 }
303
304 status = fpga_boot(dst, len);
305 if (status != 0) {
306 printf("\nFPGA: Booting failed ");
307 switch (status) {
308 case ERROR_FPGA_PRG_INIT_LOW:
309 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
310 break;
311 case ERROR_FPGA_PRG_INIT_HIGH:
312 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
313 break;
314 case ERROR_FPGA_PRG_DONE:
315 printf("(Timeout: DONE not high after programming FPGA)\n ");
316 break;
317 }
318
319 /* display infos on fpgaimage */
320 index = 15;
321 for (i=0; i<4; i++) {
322 len = dst[index];
323 printf("FPGA: %s\n", &(dst[index+1]));
324 index += len+3;
325 }
326 putc ('\n');
327 /* delayed reboot */
328 for (i=20; i>0; i--) {
329 printf("Rebooting in %2d seconds \r",i);
330 for (index=0;index<1000;index++)
331 udelay(1000);
332 }
333 putc ('\n');
334 do_reset(NULL, 0, 0, NULL);
335 }
336
337 /* restore gpio/cs settings */
338 mtdcr(cntrl0, cntrl0Reg);
339
340 puts("FPGA: ");
341
342 /* display infos on fpgaimage */
343 index = 15;
344 for (i=0; i<4; i++) {
345 len = dst[index];
346 printf("%s ", &(dst[index+1]));
347 index += len+3;
348 }
349 putc ('\n');
350
351 free(dst);
stroese6f4474e2003-03-20 15:31:19 +0000352
353 /*
354 * Reset FPGA via FPGA_DATA pin
355 */
356 SET_FPGA(FPGA_PRG | FPGA_CLK);
357 udelay(1000); /* wait 1ms */
358 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
359 udelay(1000); /* wait 1ms */
360
361 if (cpci405_version() == 3) {
362 volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
363 volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;
364
365 /*
366 * Enable outputs in fpga on version 3 board
367 */
368 *fpga_mode |= CFG_FPGA_MODE_ENABLE_OUTPUT;
369
370 /*
371 * Set outputs to 0
372 */
373 *leds = 0x00;
374
375 /*
376 * Reset external DUART
377 */
378 *fpga_mode |= CFG_FPGA_MODE_DUART_RESET;
379 udelay(100);
380 *fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
381 }
wdenkc6097192002-11-03 00:24:07 +0000382 }
383 else {
stroese6f4474e2003-03-20 15:31:19 +0000384 puts("\n*** U-Boot Version does not match Board Version!\n");
385 puts("*** CPCI-405 Version 1.x detected!\n");
386 puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n");
wdenkc6097192002-11-03 00:24:07 +0000387 }
stroese87663b12004-12-16 18:27:05 +0000388 }
wdenkc6097192002-11-03 00:24:07 +0000389
390#else /* CONFIG_CPCI405_VER2 */
391
stroese87663b12004-12-16 18:27:05 +0000392#if 0 /* test-only: code-plug now not relavant for ip-address any more */
wdenkc6097192002-11-03 00:24:07 +0000393 /*
394 * Generate last byte of ip-addr from code-plug @ 0xf0000400
395 */
396 if (ctermm2()) {
397 char str[32];
398 unsigned char ipbyte = *(unsigned char *)0xf0000400;
399
400 /*
401 * Only overwrite ip-addr with allowed values
402 */
403 if ((ipbyte != 0x00) && (ipbyte != 0xff)) {
404 bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte;
405 sprintf(str, "%ld.%ld.%ld.%ld",
406 (bd->bi_ip_addr & 0xff000000) >> 24,
407 (bd->bi_ip_addr & 0x00ff0000) >> 16,
408 (bd->bi_ip_addr & 0x0000ff00) >> 8,
409 (bd->bi_ip_addr & 0x000000ff));
410 setenv("ipaddr", str);
411 }
412 }
stroese87663b12004-12-16 18:27:05 +0000413#endif
wdenkc6097192002-11-03 00:24:07 +0000414
stroese6f4474e2003-03-20 15:31:19 +0000415 if (cpci405_version() >= 2) {
416 puts("\n*** U-Boot Version does not match Board Version!\n");
417 puts("*** CPCI-405 Board Version 2.x detected!\n");
418 puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n");
wdenkc6097192002-11-03 00:24:07 +0000419 }
420
421#endif /* CONFIG_CPCI405_VER2 */
422
423 /*
stroeseafcc4a72003-04-04 16:52:57 +0000424 * Select cts (and not dsr) on uart1
425 */
426 cntrl0Reg = mfdcr(cntrl0);
427 mtdcr(cntrl0, cntrl0Reg | 0x00001000);
428
wdenkc6097192002-11-03 00:24:07 +0000429 return (0);
430}
431
432
433/*
434 * Check Board Identity:
435 */
436
437int checkboard (void)
438{
439#ifndef CONFIG_CPCI405_VER2
440 int index;
441 int len;
442#endif
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200443 char str[64];
wdenkc6097192002-11-03 00:24:07 +0000444 int i = getenv_r ("serial#", str, sizeof(str));
stroese6f4474e2003-03-20 15:31:19 +0000445 unsigned short ver;
wdenkc6097192002-11-03 00:24:07 +0000446
447 puts ("Board: ");
448
449 if (i == -1) {
450 puts ("### No HW ID - assuming CPCI405");
451 } else {
452 puts(str);
453 }
454
stroese6f4474e2003-03-20 15:31:19 +0000455 ver = cpci405_version();
456 printf(" (Ver %d.x, ", ver);
wdenkc6097192002-11-03 00:24:07 +0000457
stroese6f4474e2003-03-20 15:31:19 +0000458#if 0 /* test-only */
459 if (ver >= 2) {
460 volatile u16 *fpga_status = (u16 *)CFG_FPGA_BASE_ADDR + 1;
461
462 if (*fpga_status & CFG_FPGA_STATUS_FLASH) {
463 puts ("FLASH Bank B, ");
464 } else {
465 puts ("FLASH Bank A, ");
466 }
467 }
wdenkc6097192002-11-03 00:24:07 +0000468#endif
469
470 if (ctermm2()) {
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200471 char str[4];
stroese1b554402003-09-12 08:44:46 +0000472
473 /*
474 * Read board-id and save in env-variable
475 */
476 sprintf(str, "%d", *(unsigned char *)0xf0000400);
477 setenv("boardid", str);
478 printf("CTERM-M2 - Id=%s)", str);
wdenkc6097192002-11-03 00:24:07 +0000479 } else {
480 if (cpci405_host()) {
481 puts ("PCI Host Version)");
482 } else {
483 puts ("PCI Adapter Version)");
484 }
485 }
486
487#ifndef CONFIG_CPCI405_VER2
488 puts ("\nFPGA: ");
489
490 /* display infos on fpgaimage */
491 index = 15;
492 for (i=0; i<4; i++) {
493 len = fpgadata[index];
494 printf("%s ", &(fpgadata[index+1]));
495 index += len+3;
496 }
497#endif
498
499 putc ('\n');
500
stroese87663b12004-12-16 18:27:05 +0000501 /*
502 * Disable sleep mode in LXT971
503 */
504 lxt971_no_sleep();
505
wdenkc6097192002-11-03 00:24:07 +0000506 return 0;
507}
508
509/* ------------------------------------------------------------------------- */
510
511long int initdram (int board_type)
512{
513 unsigned long val;
514
515 mtdcr(memcfga, mem_mb0cf);
516 val = mfdcr(memcfgd);
517
518#if 0
519 printf("\nmb0cf=%x\n", val); /* test-only */
520 printf("strap=%x\n", mfdcr(strap)); /* test-only */
521#endif
522
523 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
524}
525
526/* ------------------------------------------------------------------------- */
527
528int testdram (void)
529{
530 /* TODO: XXX XXX XXX */
531 printf ("test: 16 MB - ok\n");
532
533 return (0);
534}
535
536/* ------------------------------------------------------------------------- */
537
538#ifdef CONFIG_CPCI405_VER2
539#ifdef CONFIG_IDE_RESET
540
541void ide_set_reset(int on)
542{
543 volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
544
545 /*
546 * Assert or deassert CompactFlash Reset Pin
547 */
548 if (on) { /* assert RESET */
549 *fpga_mode &= ~(CFG_FPGA_MODE_CF_RESET);
550 } else { /* release RESET */
551 *fpga_mode |= CFG_FPGA_MODE_CF_RESET;
552 }
553}
554
555#endif /* CONFIG_IDE_RESET */
556#endif /* CONFIG_CPCI405_VER2 */
557
stroesed4629c82003-05-23 11:30:39 +0000558
stroese1b554402003-09-12 08:44:46 +0000559#ifdef CONFIG_CPCI405AB
560
stroese87663b12004-12-16 18:27:05 +0000561#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
wdenkefe2a4d2004-12-16 21:44:03 +0000562 |= CFG_FPGA_MODE_1WIRE_DIR)
stroese87663b12004-12-16 18:27:05 +0000563#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
wdenkefe2a4d2004-12-16 21:44:03 +0000564 &= ~CFG_FPGA_MODE_1WIRE_DIR)
stroese87663b12004-12-16 18:27:05 +0000565#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
wdenkefe2a4d2004-12-16 21:44:03 +0000566 & CFG_FPGA_MODE_1WIRE)
stroese1b554402003-09-12 08:44:46 +0000567
568/*
569 * Generate a 1-wire reset, return 1 if no presence detect was found,
570 * return 0 otherwise.
571 * (NOTE: Does not handle alarm presence from DS2404/DS1994)
572 */
573int OWTouchReset(void)
stroesed4629c82003-05-23 11:30:39 +0000574{
stroese1b554402003-09-12 08:44:46 +0000575 int result;
stroesed4629c82003-05-23 11:30:39 +0000576
stroese1b554402003-09-12 08:44:46 +0000577 ONE_WIRE_CLEAR;
578 udelay(480);
579 ONE_WIRE_SET;
580 udelay(70);
stroesed4629c82003-05-23 11:30:39 +0000581
stroese1b554402003-09-12 08:44:46 +0000582 result = ONE_WIRE_GET;
583
584 udelay(410);
585 return result;
stroesed4629c82003-05-23 11:30:39 +0000586}
587
588
stroese1b554402003-09-12 08:44:46 +0000589/*
590 * Send 1 a 1-wire write bit.
591 * Provide 10us recovery time.
592 */
593void OWWriteBit(int bit)
stroesed4629c82003-05-23 11:30:39 +0000594{
stroese1b554402003-09-12 08:44:46 +0000595 if (bit) {
596 /*
597 * write '1' bit
598 */
599 ONE_WIRE_CLEAR;
600 udelay(6);
601 ONE_WIRE_SET;
602 udelay(64);
603 } else {
604 /*
605 * write '0' bit
606 */
607 ONE_WIRE_CLEAR;
608 udelay(60);
609 ONE_WIRE_SET;
610 udelay(10);
stroesed4629c82003-05-23 11:30:39 +0000611 }
stroesed4629c82003-05-23 11:30:39 +0000612}
613
stroese1b554402003-09-12 08:44:46 +0000614
615/*
616 * Read a bit from the 1-wire bus and return it.
617 * Provide 10us recovery time.
618 */
619int OWReadBit(void)
620{
621 int result;
622
623 ONE_WIRE_CLEAR;
624 udelay(6);
625 ONE_WIRE_SET;
626 udelay(9);
627
628 result = ONE_WIRE_GET;
629
630 udelay(55);
631 return result;
632}
633
634
635void OWWriteByte(int data)
636{
637 int loop;
638
639 for (loop=0; loop<8; loop++) {
640 OWWriteBit(data & 0x01);
641 data >>= 1;
642 }
643}
644
645
646int OWReadByte(void)
647{
648 int loop, result = 0;
649
650 for (loop=0; loop<8; loop++) {
651 result >>= 1;
652 if (OWReadBit()) {
653 result |= 0x80;
654 }
655 }
656
657 return result;
658}
659
660
661int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
662{
663 volatile unsigned short val;
664 int result;
665 int i;
666 unsigned char ow_id[6];
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200667 char str[32];
stroese1b554402003-09-12 08:44:46 +0000668 unsigned char ow_crc;
669
670 /*
671 * Clear 1-wire bit (open drain with pull-up)
672 */
673 val = *(volatile unsigned short *)0xf0400000;
674 val &= ~0x1000; /* clear 1-wire bit */
675 *(volatile unsigned short *)0xf0400000 = val;
676
677 result = OWTouchReset();
678 if (result != 0) {
679 puts("No 1-wire device detected!\n");
680 }
681
682 OWWriteByte(0x33); /* send read rom command */
683 OWReadByte(); /* skip family code ( == 0x01) */
684 for (i=0; i<6; i++) {
685 ow_id[i] = OWReadByte();
686 }
687 ow_crc = OWReadByte(); /* read crc */
688
689 sprintf(str, "%08X%04X", *(unsigned int *)&ow_id[0], *(unsigned short *)&ow_id[4]);
690 printf("Setting environment variable 'ow_id' to %s\n", str);
691 setenv("ow_id", str);
692
693 return 0;
694}
695U_BOOT_CMD(
696 onewire, 1, 1, do_onewire,
697 "onewire - Read 1-write ID\n",
698 NULL
699 );
700
stroese87663b12004-12-16 18:27:05 +0000701
702#define CFG_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */
703#define CFG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/
704
705/*
706 * Write backplane ip-address...
707 */
708int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
709{
710 DECLARE_GLOBAL_DATA_PTR;
711
712 bd_t *bd = gd->bd;
713 char *buf;
714 ulong crc;
715 char str[32];
716 char *ptr;
717 IPaddr_t ipaddr;
718
719 buf = malloc(CFG_ENV_SIZE_2);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200720 if (eeprom_read(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) {
stroese87663b12004-12-16 18:27:05 +0000721 puts("\nError reading backplane EEPROM!\n");
722 } else {
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200723 crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4);
stroese87663b12004-12-16 18:27:05 +0000724 if (crc != *(ulong *)buf) {
725 printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf);
726 return -1;
727 }
728
729 /*
730 * Find bp_ip
731 */
732 ptr = strstr(buf+4, "bp_ip=");
733 if (ptr == NULL) {
734 printf("ERROR: bp_ip not found!\n");
735 return -1;
736 }
737 ptr += 6;
738 ipaddr = string_to_ip(ptr);
739
740 /*
741 * Update whole ip-addr
742 */
743 bd->bi_ip_addr = ipaddr;
744 sprintf(str, "%ld.%ld.%ld.%ld",
745 (bd->bi_ip_addr & 0xff000000) >> 24,
746 (bd->bi_ip_addr & 0x00ff0000) >> 16,
747 (bd->bi_ip_addr & 0x0000ff00) >> 8,
748 (bd->bi_ip_addr & 0x000000ff));
749 setenv("ipaddr", str);
750 printf("Updated ip_addr from bp_eeprom to %s!\n", str);
751 }
752
753 free(buf);
754
755 return 0;
756}
757U_BOOT_CMD(
758 getbpip, 1, 1, do_get_bpip,
759 "getbpip - Update IP-Address with Backplane IP-Address\n",
760 NULL
761 );
762
763/*
764 * Set and print backplane ip...
765 */
766int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
767{
768 char *buf;
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200769 char str[32];
stroese87663b12004-12-16 18:27:05 +0000770 ulong crc;
771
772 if (argc < 2) {
773 puts("ERROR!\n");
774 return -1;
775 }
776
777 printf("Setting bp_ip to %s\n", argv[1]);
778 buf = malloc(CFG_ENV_SIZE_2);
779 memset(buf, 0, CFG_ENV_SIZE_2);
780 sprintf(str, "bp_ip=%s", argv[1]);
781 strcpy(buf+4, str);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200782 crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4);
stroese87663b12004-12-16 18:27:05 +0000783 *(ulong *)buf = crc;
784
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200785 if (eeprom_write(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) {
stroese87663b12004-12-16 18:27:05 +0000786 puts("\nError writing backplane EEPROM!\n");
787 }
788
789 free(buf);
790
791 return 0;
792}
793U_BOOT_CMD(
794 setbpip, 2, 1, do_set_bpip,
795 "setbpip - Write Backplane IP-Address\n",
796 NULL
797 );
798
stroese1b554402003-09-12 08:44:46 +0000799#endif /* CONFIG_CPCI405AB */