blob: ed8ac48e0157781b0181925f91d9f22bbfc9d161 [file] [log] [blame]
Peter Senna Tschudin6b0071c2017-11-06 19:14:11 +00001/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Jason Liu <r64343@freescale.com>
4 *
5 * Configuration settings for Freescale MX53 low cost board.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include <asm/arch/imx-regs.h>
14
15#define CONSOLE_DEV "ttymxc0"
16
17#define CONFIG_CMDLINE_TAG
18#define CONFIG_SETUP_MEMORY_TAGS
19#define CONFIG_INITRD_TAG
20
21#define CONFIG_SYS_FSL_CLK
22
23/* Size of malloc() pool */
24#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
25
26#define CONFIG_HW_WATCHDOG
27#define CONFIG_IMX_WATCHDOG
28#define CONFIG_WATCHDOG_TIMEOUT_MSECS 8000
29
30#define CONFIG_MISC_INIT_R
31#define CONFIG_BOARD_LATE_INIT
Peter Senna Tschudin6b0071c2017-11-06 19:14:11 +000032#define CONFIG_REVISION_TAG
33
34#define CONFIG_MXC_UART
35#define CONFIG_MXC_UART_BASE UART1_BASE
36
37/* MMC Configs */
38#define CONFIG_FSL_ESDHC
39#define CONFIG_SYS_FSL_ESDHC_ADDR 0
40#define CONFIG_SYS_FSL_ESDHC_NUM 2
41
Peter Senna Tschudin6b0071c2017-11-06 19:14:11 +000042/* Eth Configs */
43#define CONFIG_MII
44
45#define CONFIG_FEC_MXC
46#define IMX_FEC_BASE FEC_BASE_ADDR
47#define CONFIG_FEC_MXC_PHYADDR 0x1F
48
49/* USB Configs */
50#define CONFIG_USB_EHCI_MX5
51#define CONFIG_USB_HOST_ETHER
52#define CONFIG_USB_ETHER_ASIX
53#define CONFIG_USB_ETHER_MCS7830
54#define CONFIG_USB_ETHER_SMSC95XX
55#define CONFIG_MXC_USB_PORT 1
56#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
57#define CONFIG_MXC_USB_FLAGS 0
58
59#define CONFIG_SYS_RTC_BUS_NUM 2
60#define CONFIG_SYS_I2C_RTC_ADDR 0x30
61
62/* I2C Configs */
63#define CONFIG_SYS_I2C
64#define CONFIG_SYS_I2C_MXC
65#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
66#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
67#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
68
69/* PMIC Controller */
70#define CONFIG_POWER
71#define CONFIG_POWER_I2C
72#define CONFIG_DIALOG_POWER
73#define CONFIG_POWER_FSL
74#define CONFIG_POWER_FSL_MC13892
75#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
76#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
77
78/* allow to overwrite serial and ethaddr */
79#define CONFIG_ENV_OVERWRITE
80#define CONFIG_CONS_INDEX 1
81#define CONFIG_BAUDRATE 115200
82
83/* Command definition */
Peter Senna Tschudin6b0071c2017-11-06 19:14:11 +000084
85#define CONFIG_ETHPRIME "FEC0"
86
87#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
Peter Senna Tschudin6b0071c2017-11-06 19:14:11 +000088
89#define PPD_CONFIG_NFS \
90 "nfsserver=192.168.252.95\0" \
91 "gatewayip=192.168.252.95\0" \
92 "netmask=255.255.255.0\0" \
93 "ipaddr=192.168.252.99\0" \
94 "kernsize=0x2000\0" \
95 "use_dhcp=0\0" \
96 "nfsroot=/opt/springdale/rd\0" \
97 "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
98 "${kern_ipconf} nfsroot=${nfsserver}:${nfsroot},v3,tcp rw\0" \
99 "choose_ip=if test $use_dhcp = 1; then set kern_ipconf ip=dhcp; " \
100 "set getcmd dhcp; else set kern_ipconf " \
101 "ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off; " \
102 "set getcmd tftp; fi\0" \
103 "nfs=run choose_ip setargs bootargs_nfs; ${getcmd} ${loadaddr} " \
104 "${nfsserver}:${image}; bootm ${loadaddr}\0" \
105
106#define CONFIG_EXTRA_ENV_SETTINGS \
107 PPD_CONFIG_NFS \
108 "bootlimit=10\0" \
109 "image=/boot/fitImage\0" \
110 "fdt_high=0xffffffff\0" \
111 "dev=mmc\0" \
112 "devnum=0\0" \
113 "rootdev=mmcblk0p\0" \
114 "quiet=quiet loglevel=0\0" \
115 "console=" CONSOLE_DEV "\0" \
116 "lvds=ldb\0" \
117 "setargs=setenv bootargs ${lvds} jtag=on mem=2G " \
118 "vt.global_cursor_default=0 bootcause=${bootcause} ${quiet} " \
119 "console=${console} ${rtc_status}\0" \
120 "bootargs_emmc=setenv bootargs root=/dev/${rootdev}${partnum} ro " \
121 "rootwait ${bootargs}\0" \
122 "doquiet=if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
123 "then setenv quiet; fi\0" \
124 "hasfirstboot=ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
125 "/boot/bootcause/firstboot\0" \
126 "swappartitions=setexpr partnum 3 - ${partnum}\0" \
127 "failbootcmd=" \
128 "ppd_lcd_enable; " \
129 "msg=\"Monitor failed to start. " \
130 "Try again, or contact GE Service for support.\"; " \
131 "echo $msg; " \
132 "setenv stdout vga; " \
133 "echo \"\n\n\n\n \" $msg; " \
134 "setenv stdout serial; " \
135 "mw.b 0x7000A000 0xbc; " \
136 "mw.b 0x7000A001 0x00; " \
137 "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
138 "altbootcmd=" \
139 "run doquiet; " \
140 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
141 "run hasfirstboot || setenv partnum 0; " \
142 "if test ${partnum} != 0; then " \
143 "setenv bootcause REVERT; " \
144 "run swappartitions loadimage doboot; " \
145 "fi; " \
146 "run failbootcmd\0" \
147 "loadimage=" \
148 "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
149 "doboot=" \
150 "echo Booting from ${dev}:${devnum}:${partnum} ...; " \
151 "run setargs; " \
152 "run bootargs_emmc; " \
153 "bootm ${loadaddr}\0" \
154 "tryboot=" \
155 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
156 "run loadimage || run swappartitions && run loadimage || " \
157 "setenv partnum 0 && echo MISSING IMAGE;" \
158 "run doboot; " \
159 "run failbootcmd\0" \
160 "video-mode=" \
161 "lcd:800x480-24@60,monitor=lcd\0" \
162
163#define CONFIG_MMCBOOTCOMMAND \
164 "if mmc dev ${devnum}; then " \
165 "run doquiet; " \
166 "run tryboot; " \
167 "fi; " \
168
169#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
170
171#define CONFIG_ARP_TIMEOUT 200UL
172
173/* Miscellaneous configurable options */
Peter Senna Tschudin6b0071c2017-11-06 19:14:11 +0000174#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
175
176#define CONFIG_SYS_MAXARGS 48 /* max number of command args */
177#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
178
179#define CONFIG_SYS_MEMTEST_START 0x70000000
180#define CONFIG_SYS_MEMTEST_END 0x70010000
181
182#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
183
Peter Senna Tschudin6b0071c2017-11-06 19:14:11 +0000184/* Physical Memory Map */
185#define CONFIG_NR_DRAM_BANKS 2
186#define PHYS_SDRAM_1 CSD0_BASE_ADDR
187#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
188#define PHYS_SDRAM_2 CSD1_BASE_ADDR
189#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
190#define PHYS_SDRAM_SIZE (gd->ram_size)
191
192#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
193#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
194#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
195
196#define CONFIG_SYS_INIT_SP_OFFSET \
197 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
198#define CONFIG_SYS_INIT_SP_ADDR \
199 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
200
201/* FLASH and environment organization */
202#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
203#define CONFIG_ENV_SIZE (8 * 1024)
204#define CONFIG_ENV_IS_IN_MMC
205#define CONFIG_SYS_MMC_ENV_DEV 0
206
207#define CONFIG_CMD_FUSE
208#define CONFIG_FSL_IIM
209
210#define CONFIG_SYS_I2C_SPEED 100000
211
212/* I2C1 */
213#define CONFIG_SYS_NUM_I2C_BUSES 9
214#define CONFIG_SYS_I2C_MAX_HOPS 1
215#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
216 {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
217 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
218 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
219 {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
220 {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
221 {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
222 {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
223 {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
224 }
225
226#define CONFIG_BCH
227
Peter Senna Tschudin6b0071c2017-11-06 19:14:11 +0000228/* Backlight Control */
229#define CONFIG_PWM_IMX
230#define CONFIG_IMX6_PWM_PER_CLK 66666000
231
232/* Framebuffer and LCD */
233#ifdef CONFIG_VIDEO
234 #define CONFIG_VIDEO_IPUV3
235#endif
236
237#endif /* __CONFIG_H */