Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 1 | if ARCH_STM32MP |
| 2 | |
| 3 | config SPL |
Patrick Delaunay | 97f7e39 | 2020-07-24 11:13:31 +0200 | [diff] [blame] | 4 | select SPL_BOARD_INIT |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 5 | select SPL_CLK |
| 6 | select SPL_DM |
| 7 | select SPL_DM_SEQ_ALIAS |
Simon Glass | 9ca0068 | 2021-07-10 21:14:31 -0600 | [diff] [blame] | 8 | select SPL_DRIVERS_MISC |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 9 | select SPL_FRAMEWORK |
Simon Glass | 83061db | 2021-07-10 21:14:30 -0600 | [diff] [blame] | 10 | select SPL_GPIO |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 11 | select SPL_LIBCOMMON_SUPPORT |
| 12 | select SPL_LIBGENERIC_SUPPORT |
| 13 | select SPL_OF_CONTROL |
| 14 | select SPL_OF_TRANSLATE |
| 15 | select SPL_PINCTRL |
| 16 | select SPL_REGMAP |
Ley Foon Tan | bfc6bae | 2018-06-14 18:45:19 +0800 | [diff] [blame] | 17 | select SPL_DM_RESET |
Simon Glass | 2a73606 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 18 | select SPL_SERIAL |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 19 | select SPL_SYSCON |
Simon Glass | 078111b | 2021-07-10 21:14:28 -0600 | [diff] [blame] | 20 | select SPL_WATCHDOG if WATCHDOG |
Patrick Delaunay | 27a986d | 2019-04-18 17:32:47 +0200 | [diff] [blame] | 21 | imply BOOTSTAGE_STASH if SPL_BOOTSTAGE |
| 22 | imply SPL_BOOTSTAGE if BOOTSTAGE |
Patrick Delaunay | 006ea18 | 2019-02-27 17:01:14 +0100 | [diff] [blame] | 23 | imply SPL_DISPLAY_PRINT |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 24 | imply SPL_LIBDISK_SUPPORT |
Simon Glass | ea2ca7e | 2021-08-08 12:20:14 -0600 | [diff] [blame] | 25 | imply SPL_SPI_LOAD if SPL_SPI |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 26 | |
| 27 | config SYS_SOC |
| 28 | default "stm32mp" |
| 29 | |
Patrick Delaunay | ef84ddd | 2019-04-18 17:32:36 +0200 | [diff] [blame] | 30 | config SYS_MALLOC_LEN |
| 31 | default 0x2000000 |
| 32 | |
Patrick Delaunay | 579a3e7 | 2019-04-18 17:32:37 +0200 | [diff] [blame] | 33 | config ENV_SIZE |
Patrice Chotard | 1538e1a | 2019-05-07 18:40:47 +0200 | [diff] [blame] | 34 | default 0x2000 |
Patrick Delaunay | 579a3e7 | 2019-04-18 17:32:37 +0200 | [diff] [blame] | 35 | |
Patrick Delaunay | 647d319 | 2022-05-20 18:24:43 +0200 | [diff] [blame^] | 36 | choice |
| 37 | prompt "Select STMicroelectronics STM32MPxxx Soc" |
| 38 | default STM32MP15x |
| 39 | |
Patrick Delaunay | 8462548 | 2020-01-13 15:17:42 +0100 | [diff] [blame] | 40 | config STM32MP15x |
| 41 | bool "Support STMicroelectronics STM32MP15x Soc" |
Patrick Delaunay | 17aeb58 | 2021-10-11 09:52:49 +0200 | [diff] [blame] | 42 | select ARCH_SUPPORT_PSCI |
Patrick Delaunay | 5564b4c | 2021-10-13 15:11:18 +0200 | [diff] [blame] | 43 | select BINMAN |
Lokesh Vutla | acf1500 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 44 | select CPU_V7A |
Patrick Delaunay | 17aeb58 | 2021-10-11 09:52:49 +0200 | [diff] [blame] | 45 | select CPU_V7_HAS_NONSEC |
Patrick Delaunay | 41c7977 | 2018-04-16 10:13:24 +0200 | [diff] [blame] | 46 | select CPU_V7_HAS_VIRT |
Patrice Chotard | 22c0815 | 2022-01-20 08:19:15 +0100 | [diff] [blame] | 47 | select OF_BOARD if TFABOOT |
Patrick Delaunay | e81f8d1 | 2019-07-02 13:26:07 +0200 | [diff] [blame] | 48 | select OF_BOARD_SETUP |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 49 | select PINCTRL_STM32 |
Patrick Delaunay | d090cba | 2018-07-09 15:17:20 +0200 | [diff] [blame] | 50 | select STM32_RCC |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 51 | select STM32_RESET |
Patrick Delaunay | 16a0722 | 2019-07-30 19:16:25 +0200 | [diff] [blame] | 52 | select STM32_SERIAL |
Patrick Delaunay | 2ff0866 | 2022-05-20 18:24:40 +0200 | [diff] [blame] | 53 | select SUPPORT_SPL |
Andre Przywara | 7842b6a | 2018-04-12 04:24:46 +0300 | [diff] [blame] | 54 | select SYS_ARCH_TIMER |
Patrick Delaunay | c16cba8 | 2020-07-02 17:43:45 +0200 | [diff] [blame] | 55 | imply CMD_NVEDIT_INFO |
Patrick Delaunay | 8462548 | 2020-01-13 15:17:42 +0100 | [diff] [blame] | 56 | help |
| 57 | support of STMicroelectronics SOC STM32MP15x family |
| 58 | STM32MP157, STM32MP153 or STM32MP151 |
| 59 | STMicroelectronics MPU with core ARMv7 |
| 60 | dual core A7 for STM32MP157/3, monocore for STM32MP151 |
Patrick Delaunay | 647d319 | 2022-05-20 18:24:43 +0200 | [diff] [blame^] | 61 | endchoice |
| 62 | |
| 63 | if STM32MP15x |
Patrick Delaunay | 8462548 | 2020-01-13 15:17:42 +0100 | [diff] [blame] | 64 | |
Patrick Delaunay | 6de57b4 | 2021-07-26 11:21:34 +0200 | [diff] [blame] | 65 | config STM32MP15x_STM32IMAGE |
| 66 | bool "Support STM32 image for generated U-Boot image" |
Patrick Delaunay | 647d319 | 2022-05-20 18:24:43 +0200 | [diff] [blame^] | 67 | depends on TFABOOT |
Patrick Delaunay | 6de57b4 | 2021-07-26 11:21:34 +0200 | [diff] [blame] | 68 | help |
| 69 | Support of STM32 image generation for SOC STM32MP15x |
| 70 | for TF-A boot when FIP container is not used |
| 71 | |
Patrick Delaunay | 8462548 | 2020-01-13 15:17:42 +0100 | [diff] [blame] | 72 | choice |
| 73 | prompt "STM32MP15x board select" |
| 74 | optional |
| 75 | |
| 76 | config TARGET_ST_STM32MP15x |
| 77 | bool "STMicroelectronics STM32MP15x boards" |
Patrick Delaunay | 15ac0c7 | 2020-03-10 10:15:03 +0100 | [diff] [blame] | 78 | imply BOOTSTAGE |
Patrick Delaunay | 15ac0c7 | 2020-03-10 10:15:03 +0100 | [diff] [blame] | 79 | imply CMD_BOOTSTAGE |
Patrick Delaunay | eee1580 | 2019-12-03 09:38:58 +0100 | [diff] [blame] | 80 | imply CMD_CLS if CMD_BMP |
Patrick Delaunay | a67d958 | 2019-07-30 19:16:26 +0200 | [diff] [blame] | 81 | imply DISABLE_CONSOLE |
Patrick Delaunay | 6755198 | 2019-07-30 19:16:23 +0200 | [diff] [blame] | 82 | imply PRE_CONSOLE_BUFFER |
Patrick Delaunay | c50c928 | 2019-07-30 19:16:22 +0200 | [diff] [blame] | 83 | imply SILENT_CONSOLE |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 84 | help |
Patrick Delaunay | 8462548 | 2020-01-13 15:17:42 +0100 | [diff] [blame] | 85 | target the STMicroelectronics board with SOC STM32MP15x |
| 86 | managed by board/st/stm32mp1: |
| 87 | Evalulation board (EV1) or Discovery board (DK1 and DK2). |
| 88 | The difference between board are managed with devicetree |
| 89 | |
Jagan Teki | fd4dc09 | 2021-03-16 21:52:06 +0530 | [diff] [blame] | 90 | config TARGET_MICROGEA_STM32MP1 |
| 91 | bool "Engicam MicroGEA STM32MP1 SOM" |
Jagan Teki | fd4dc09 | 2021-03-16 21:52:06 +0530 | [diff] [blame] | 92 | imply BOOTSTAGE |
Jagan Teki | fd4dc09 | 2021-03-16 21:52:06 +0530 | [diff] [blame] | 93 | imply CMD_BOOTSTAGE |
| 94 | imply CMD_CLS if CMD_BMP |
| 95 | imply DISABLE_CONSOLE |
| 96 | imply PRE_CONSOLE_BUFFER |
| 97 | imply SILENT_CONSOLE |
| 98 | help |
| 99 | MicroGEA STM32MP1 is a STM32MP157A based Micro SOM. |
| 100 | |
| 101 | MicroGEA STM32MP1 MicroDev 2.0: |
| 102 | * MicroDev 2.0 is a general purpose miniature carrier board with CAN, |
| 103 | LTE and LVDS panel interfaces. |
| 104 | * MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board |
| 105 | for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board. |
| 106 | |
Jagan Teki | 0441b48 | 2021-03-16 21:52:07 +0530 | [diff] [blame] | 107 | MicroGEA STM32MP1 MicroDev 2.0 7" OF: |
| 108 | * 7" OF is a capacitive touch 7" Open Frame panel solutions with LVDS |
| 109 | panel and toucscreen. |
| 110 | * MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with |
| 111 | pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7" |
| 112 | Open Frame Solution board. |
| 113 | |
Jagan Teki | 30edf40 | 2021-03-16 21:52:03 +0530 | [diff] [blame] | 114 | config TARGET_ICORE_STM32MP1 |
| 115 | bool "Engicam i.Core STM32MP1 SOM" |
Jagan Teki | 30edf40 | 2021-03-16 21:52:03 +0530 | [diff] [blame] | 116 | imply BOOTSTAGE |
Jagan Teki | 30edf40 | 2021-03-16 21:52:03 +0530 | [diff] [blame] | 117 | imply CMD_BOOTSTAGE |
| 118 | imply CMD_CLS if CMD_BMP |
| 119 | imply DISABLE_CONSOLE |
| 120 | imply PRE_CONSOLE_BUFFER |
| 121 | imply SILENT_CONSOLE |
| 122 | help |
| 123 | i.Core STM32MP1 is an EDIMM SOM based on STM32MP157A. |
| 124 | |
| 125 | i.Core STM32MP1 EDIMM2.2: |
| 126 | * EDIMM2.2 is a Form Factor Capacitive Evaluation Board. |
| 127 | * i.Core STM32MP1 needs to mount on top of EDIMM2.2 for |
| 128 | creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit. |
| 129 | |
Jagan Teki | b594ec8 | 2021-03-16 21:52:04 +0530 | [diff] [blame] | 130 | i.Core STM32MP1 C.TOUCH 2.0 |
| 131 | * C.TOUCH 2.0 is a general purpose Carrier board. |
| 132 | * i.Core STM32MP1 needs to mount on top of this Carrier board |
| 133 | for creating complete i.Core STM32MP1 C.TOUCH 2.0 board. |
| 134 | |
Marek Vasut | 1995373 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 135 | config TARGET_DH_STM32MP1_PDK2 |
| 136 | bool "DH STM32MP1 PDK2" |
Marek Vasut | 1995373 | 2020-01-24 18:39:16 +0100 | [diff] [blame] | 137 | help |
| 138 | Target the DH PDK2 development kit with STM32MP15x SoM. |
| 139 | |
Patrick Delaunay | 8462548 | 2020-01-13 15:17:42 +0100 | [diff] [blame] | 140 | endchoice |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 141 | |
Patrick Delaunay | 647d319 | 2022-05-20 18:24:43 +0200 | [diff] [blame^] | 142 | source "board/st/stm32mp1/Kconfig" |
| 143 | source "board/dhelectronics/dh_stm32mp1/Kconfig" |
| 144 | source "board/engicam/stm32mp1/Kconfig" |
| 145 | endif |
| 146 | |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 147 | config SYS_TEXT_BASE |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 148 | default 0xC0100000 |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 149 | |
Patrick Delaunay | 45ccdb6 | 2019-02-27 17:01:15 +0100 | [diff] [blame] | 150 | config NR_DRAM_BANKS |
| 151 | default 1 |
| 152 | |
Patrick Delaunay | 67f9f11 | 2020-09-04 12:55:19 +0200 | [diff] [blame] | 153 | config DDR_CACHEABLE_SIZE |
| 154 | hex "Size of the DDR marked cacheable in pre-reloc stage" |
Patrick Delaunay | 67f9f11 | 2020-09-04 12:55:19 +0200 | [diff] [blame] | 155 | default 0x40000000 |
| 156 | help |
| 157 | Define the size of the DDR marked as cacheable in U-Boot |
| 158 | pre-reloc stage. |
| 159 | This option can be useful to avoid speculatif access |
| 160 | to secured area of DDR used by TF-A or OP-TEE before U-Boot |
| 161 | initialization. |
| 162 | The areas marked "no-map" in device tree should be located |
| 163 | before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. |
| 164 | |
Patrick Delaunay | 11dfd1a | 2018-03-20 10:54:54 +0100 | [diff] [blame] | 165 | config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 |
| 166 | hex "Partition on MMC2 to use to load U-Boot from" |
| 167 | depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION |
| 168 | default 1 |
| 169 | help |
| 170 | Partition on the second MMC to load U-Boot from when the MMC is being |
| 171 | used in raw mode |
| 172 | |
Patrick Delaunay | c60f3b3 | 2019-07-05 17:20:15 +0200 | [diff] [blame] | 173 | config STM32_ETZPC |
| 174 | bool "STM32 Extended TrustZone Protection" |
Patrick Delaunay | 7a02e4d | 2020-03-10 16:05:43 +0100 | [diff] [blame] | 175 | depends on STM32MP15x |
Patrick Delaunay | c60f3b3 | 2019-07-05 17:20:15 +0200 | [diff] [blame] | 176 | default y |
Simon Glass | d3877fb | 2021-12-18 11:27:51 -0700 | [diff] [blame] | 177 | imply BOOTP_SERVERIP |
Patrick Delaunay | c60f3b3 | 2019-07-05 17:20:15 +0200 | [diff] [blame] | 178 | help |
| 179 | Say y to enable STM32 Extended TrustZone Protection |
| 180 | |
Alexandru Gagniuc | ee87085 | 2021-07-29 11:47:17 -0500 | [diff] [blame] | 181 | config STM32_ECDSA_VERIFY |
| 182 | bool "STM32 ECDSA verification via the ROM API" |
| 183 | depends on SPL_ECDSA_VERIFY |
| 184 | default y |
| 185 | help |
| 186 | Say y to enable the uclass driver for ECDSA verification using the |
| 187 | ROM API provided on STM32MP. |
| 188 | The ROM API is only available during SPL for now. |
| 189 | |
Patrick Delaunay | f4cb5d6 | 2019-07-05 17:20:17 +0200 | [diff] [blame] | 190 | config CMD_STM32KEY |
| 191 | bool "command stm32key to fuse public key hash" |
Patrick Delaunay | f4cb5d6 | 2019-07-05 17:20:17 +0200 | [diff] [blame] | 192 | help |
| 193 | fuse public key hash in corresponding fuse used to authenticate |
| 194 | binary. |
Patrick Delaunay | 3a99481 | 2021-06-28 14:55:57 +0200 | [diff] [blame] | 195 | This command is used to evaluate the secure boot on stm32mp SOC, |
| 196 | it is deactivated by default in real products. |
Patrick Delaunay | f4cb5d6 | 2019-07-05 17:20:17 +0200 | [diff] [blame] | 197 | |
Patrick Delaunay | 6755198 | 2019-07-30 19:16:23 +0200 | [diff] [blame] | 198 | config PRE_CON_BUF_ADDR |
| 199 | default 0xC02FF000 |
| 200 | |
| 201 | config PRE_CON_BUF_SZ |
| 202 | default 4096 |
| 203 | |
Patrick Delaunay | 27a986d | 2019-04-18 17:32:47 +0200 | [diff] [blame] | 204 | config BOOTSTAGE_STASH_ADDR |
| 205 | default 0xC3000000 |
| 206 | |
Patrick Delaunay | 5c68904 | 2021-12-07 10:05:59 +0100 | [diff] [blame] | 207 | if BOOTCOUNT_GENERIC |
Patrick Delaunay | 3419982 | 2019-04-18 17:32:45 +0200 | [diff] [blame] | 208 | config SYS_BOOTCOUNT_SINGLEWORD |
| 209 | default y |
| 210 | |
| 211 | # TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21) |
| 212 | config SYS_BOOTCOUNT_ADDR |
| 213 | default 0x5C00A154 |
| 214 | endif |
| 215 | |
Patrick Delaunay | 320d266 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 216 | if DEBUG_UART |
| 217 | |
| 218 | config DEBUG_UART_BOARD_INIT |
| 219 | default y |
| 220 | |
| 221 | # debug on UART4 by default |
| 222 | config DEBUG_UART_BASE |
| 223 | default 0x40010000 |
| 224 | |
| 225 | # clock source is HSI on reset |
| 226 | config DEBUG_UART_CLOCK |
| 227 | default 64000000 |
| 228 | endif |
| 229 | |
Patrick Delaunay | 2dc2216 | 2021-02-25 13:37:00 +0100 | [diff] [blame] | 230 | source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig" |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 231 | endif |