blob: 446d3258c943db6602f02a65e90176bc89871ba8 [file] [log] [blame]
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01001if ARCH_STM32MP
2
3config SPL
Patrick Delaunay97f7e392020-07-24 11:13:31 +02004 select SPL_BOARD_INIT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01005 select SPL_CLK
6 select SPL_DM
7 select SPL_DM_SEQ_ALIAS
Simon Glass9ca00682021-07-10 21:14:31 -06008 select SPL_DRIVERS_MISC
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01009 select SPL_FRAMEWORK
Simon Glass83061db2021-07-10 21:14:30 -060010 select SPL_GPIO
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010011 select SPL_LIBCOMMON_SUPPORT
12 select SPL_LIBGENERIC_SUPPORT
13 select SPL_OF_CONTROL
14 select SPL_OF_TRANSLATE
15 select SPL_PINCTRL
16 select SPL_REGMAP
Ley Foon Tanbfc6bae2018-06-14 18:45:19 +080017 select SPL_DM_RESET
Simon Glass2a736062021-08-08 12:20:12 -060018 select SPL_SERIAL
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010019 select SPL_SYSCON
Simon Glass078111b2021-07-10 21:14:28 -060020 select SPL_WATCHDOG if WATCHDOG
Patrick Delaunay27a986d2019-04-18 17:32:47 +020021 imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
22 imply SPL_BOOTSTAGE if BOOTSTAGE
Patrick Delaunay006ea182019-02-27 17:01:14 +010023 imply SPL_DISPLAY_PRINT
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010024 imply SPL_LIBDISK_SUPPORT
Simon Glassea2ca7e2021-08-08 12:20:14 -060025 imply SPL_SPI_LOAD if SPL_SPI
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010026
27config SYS_SOC
28 default "stm32mp"
29
Patrick Delaunayef84ddd2019-04-18 17:32:36 +020030config SYS_MALLOC_LEN
31 default 0x2000000
32
Patrick Delaunay579a3e72019-04-18 17:32:37 +020033config ENV_SIZE
Patrice Chotard1538e1a2019-05-07 18:40:47 +020034 default 0x2000
Patrick Delaunay579a3e72019-04-18 17:32:37 +020035
Patrick Delaunay647d3192022-05-20 18:24:43 +020036choice
37 prompt "Select STMicroelectronics STM32MPxxx Soc"
38 default STM32MP15x
39
Patrick Delaunay84625482020-01-13 15:17:42 +010040config STM32MP15x
41 bool "Support STMicroelectronics STM32MP15x Soc"
Patrick Delaunay17aeb582021-10-11 09:52:49 +020042 select ARCH_SUPPORT_PSCI
Patrick Delaunay5564b4c2021-10-13 15:11:18 +020043 select BINMAN
Lokesh Vutlaacf15002018-04-26 18:21:26 +053044 select CPU_V7A
Patrick Delaunay17aeb582021-10-11 09:52:49 +020045 select CPU_V7_HAS_NONSEC
Patrick Delaunay41c79772018-04-16 10:13:24 +020046 select CPU_V7_HAS_VIRT
Patrice Chotard22c08152022-01-20 08:19:15 +010047 select OF_BOARD if TFABOOT
Patrick Delaunaye81f8d12019-07-02 13:26:07 +020048 select OF_BOARD_SETUP
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010049 select PINCTRL_STM32
Patrick Delaunayd090cba2018-07-09 15:17:20 +020050 select STM32_RCC
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010051 select STM32_RESET
Patrick Delaunay16a07222019-07-30 19:16:25 +020052 select STM32_SERIAL
Patrick Delaunay2ff08662022-05-20 18:24:40 +020053 select SUPPORT_SPL
Andre Przywara7842b6a2018-04-12 04:24:46 +030054 select SYS_ARCH_TIMER
Patrick Delaunayc16cba82020-07-02 17:43:45 +020055 imply CMD_NVEDIT_INFO
Patrick Delaunay84625482020-01-13 15:17:42 +010056 help
57 support of STMicroelectronics SOC STM32MP15x family
58 STM32MP157, STM32MP153 or STM32MP151
59 STMicroelectronics MPU with core ARMv7
60 dual core A7 for STM32MP157/3, monocore for STM32MP151
Patrick Delaunay647d3192022-05-20 18:24:43 +020061endchoice
62
63if STM32MP15x
Patrick Delaunay84625482020-01-13 15:17:42 +010064
Patrick Delaunay6de57b42021-07-26 11:21:34 +020065config STM32MP15x_STM32IMAGE
66 bool "Support STM32 image for generated U-Boot image"
Patrick Delaunay647d3192022-05-20 18:24:43 +020067 depends on TFABOOT
Patrick Delaunay6de57b42021-07-26 11:21:34 +020068 help
69 Support of STM32 image generation for SOC STM32MP15x
70 for TF-A boot when FIP container is not used
71
Patrick Delaunay84625482020-01-13 15:17:42 +010072choice
73 prompt "STM32MP15x board select"
74 optional
75
76config TARGET_ST_STM32MP15x
77 bool "STMicroelectronics STM32MP15x boards"
Patrick Delaunay15ac0c72020-03-10 10:15:03 +010078 imply BOOTSTAGE
Patrick Delaunay15ac0c72020-03-10 10:15:03 +010079 imply CMD_BOOTSTAGE
Patrick Delaunayeee15802019-12-03 09:38:58 +010080 imply CMD_CLS if CMD_BMP
Patrick Delaunaya67d9582019-07-30 19:16:26 +020081 imply DISABLE_CONSOLE
Patrick Delaunay67551982019-07-30 19:16:23 +020082 imply PRE_CONSOLE_BUFFER
Patrick Delaunayc50c9282019-07-30 19:16:22 +020083 imply SILENT_CONSOLE
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010084 help
Patrick Delaunay84625482020-01-13 15:17:42 +010085 target the STMicroelectronics board with SOC STM32MP15x
86 managed by board/st/stm32mp1:
87 Evalulation board (EV1) or Discovery board (DK1 and DK2).
88 The difference between board are managed with devicetree
89
Jagan Tekifd4dc092021-03-16 21:52:06 +053090config TARGET_MICROGEA_STM32MP1
91 bool "Engicam MicroGEA STM32MP1 SOM"
Jagan Tekifd4dc092021-03-16 21:52:06 +053092 imply BOOTSTAGE
Jagan Tekifd4dc092021-03-16 21:52:06 +053093 imply CMD_BOOTSTAGE
94 imply CMD_CLS if CMD_BMP
95 imply DISABLE_CONSOLE
96 imply PRE_CONSOLE_BUFFER
97 imply SILENT_CONSOLE
98 help
99 MicroGEA STM32MP1 is a STM32MP157A based Micro SOM.
100
101 MicroGEA STM32MP1 MicroDev 2.0:
102 * MicroDev 2.0 is a general purpose miniature carrier board with CAN,
103 LTE and LVDS panel interfaces.
104 * MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
105 for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.
106
Jagan Teki0441b482021-03-16 21:52:07 +0530107 MicroGEA STM32MP1 MicroDev 2.0 7" OF:
108 * 7" OF is a capacitive touch 7" Open Frame panel solutions with LVDS
109 panel and toucscreen.
110 * MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with
111 pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7"
112 Open Frame Solution board.
113
Jagan Teki30edf402021-03-16 21:52:03 +0530114config TARGET_ICORE_STM32MP1
115 bool "Engicam i.Core STM32MP1 SOM"
Jagan Teki30edf402021-03-16 21:52:03 +0530116 imply BOOTSTAGE
Jagan Teki30edf402021-03-16 21:52:03 +0530117 imply CMD_BOOTSTAGE
118 imply CMD_CLS if CMD_BMP
119 imply DISABLE_CONSOLE
120 imply PRE_CONSOLE_BUFFER
121 imply SILENT_CONSOLE
122 help
123 i.Core STM32MP1 is an EDIMM SOM based on STM32MP157A.
124
125 i.Core STM32MP1 EDIMM2.2:
126 * EDIMM2.2 is a Form Factor Capacitive Evaluation Board.
127 * i.Core STM32MP1 needs to mount on top of EDIMM2.2 for
128 creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit.
129
Jagan Tekib594ec82021-03-16 21:52:04 +0530130 i.Core STM32MP1 C.TOUCH 2.0
131 * C.TOUCH 2.0 is a general purpose Carrier board.
132 * i.Core STM32MP1 needs to mount on top of this Carrier board
133 for creating complete i.Core STM32MP1 C.TOUCH 2.0 board.
134
Marek Vasut19953732020-01-24 18:39:16 +0100135config TARGET_DH_STM32MP1_PDK2
136 bool "DH STM32MP1 PDK2"
Marek Vasut19953732020-01-24 18:39:16 +0100137 help
138 Target the DH PDK2 development kit with STM32MP15x SoM.
139
Patrick Delaunay84625482020-01-13 15:17:42 +0100140endchoice
Patrick Delaunay2514c2d2018-03-12 10:46:10 +0100141
Patrick Delaunay647d3192022-05-20 18:24:43 +0200142source "board/st/stm32mp1/Kconfig"
143source "board/dhelectronics/dh_stm32mp1/Kconfig"
144source "board/engicam/stm32mp1/Kconfig"
145endif
146
Patrick Delaunay2514c2d2018-03-12 10:46:10 +0100147config SYS_TEXT_BASE
Patrick Delaunay2514c2d2018-03-12 10:46:10 +0100148 default 0xC0100000
Patrick Delaunay2514c2d2018-03-12 10:46:10 +0100149
Patrick Delaunay45ccdb62019-02-27 17:01:15 +0100150config NR_DRAM_BANKS
151 default 1
152
Patrick Delaunay67f9f112020-09-04 12:55:19 +0200153config DDR_CACHEABLE_SIZE
154 hex "Size of the DDR marked cacheable in pre-reloc stage"
Patrick Delaunay67f9f112020-09-04 12:55:19 +0200155 default 0x40000000
156 help
157 Define the size of the DDR marked as cacheable in U-Boot
158 pre-reloc stage.
159 This option can be useful to avoid speculatif access
160 to secured area of DDR used by TF-A or OP-TEE before U-Boot
161 initialization.
162 The areas marked "no-map" in device tree should be located
163 before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
164
Patrick Delaunay11dfd1a2018-03-20 10:54:54 +0100165config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
166 hex "Partition on MMC2 to use to load U-Boot from"
167 depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
168 default 1
169 help
170 Partition on the second MMC to load U-Boot from when the MMC is being
171 used in raw mode
172
Patrick Delaunayc60f3b32019-07-05 17:20:15 +0200173config STM32_ETZPC
174 bool "STM32 Extended TrustZone Protection"
Patrick Delaunay7a02e4d2020-03-10 16:05:43 +0100175 depends on STM32MP15x
Patrick Delaunayc60f3b32019-07-05 17:20:15 +0200176 default y
Simon Glassd3877fb2021-12-18 11:27:51 -0700177 imply BOOTP_SERVERIP
Patrick Delaunayc60f3b32019-07-05 17:20:15 +0200178 help
179 Say y to enable STM32 Extended TrustZone Protection
180
Alexandru Gagniucee870852021-07-29 11:47:17 -0500181config STM32_ECDSA_VERIFY
182 bool "STM32 ECDSA verification via the ROM API"
183 depends on SPL_ECDSA_VERIFY
184 default y
185 help
186 Say y to enable the uclass driver for ECDSA verification using the
187 ROM API provided on STM32MP.
188 The ROM API is only available during SPL for now.
189
Patrick Delaunayf4cb5d62019-07-05 17:20:17 +0200190config CMD_STM32KEY
191 bool "command stm32key to fuse public key hash"
Patrick Delaunayf4cb5d62019-07-05 17:20:17 +0200192 help
193 fuse public key hash in corresponding fuse used to authenticate
194 binary.
Patrick Delaunay3a994812021-06-28 14:55:57 +0200195 This command is used to evaluate the secure boot on stm32mp SOC,
196 it is deactivated by default in real products.
Patrick Delaunayf4cb5d62019-07-05 17:20:17 +0200197
Patrick Delaunay67551982019-07-30 19:16:23 +0200198config PRE_CON_BUF_ADDR
199 default 0xC02FF000
200
201config PRE_CON_BUF_SZ
202 default 4096
203
Patrick Delaunay27a986d2019-04-18 17:32:47 +0200204config BOOTSTAGE_STASH_ADDR
205 default 0xC3000000
206
Patrick Delaunay5c689042021-12-07 10:05:59 +0100207if BOOTCOUNT_GENERIC
Patrick Delaunay34199822019-04-18 17:32:45 +0200208config SYS_BOOTCOUNT_SINGLEWORD
209 default y
210
211# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21)
212config SYS_BOOTCOUNT_ADDR
213 default 0x5C00A154
214endif
215
Patrick Delaunay320d2662018-05-17 14:50:46 +0200216if DEBUG_UART
217
218config DEBUG_UART_BOARD_INIT
219 default y
220
221# debug on UART4 by default
222config DEBUG_UART_BASE
223 default 0x40010000
224
225# clock source is HSI on reset
226config DEBUG_UART_CLOCK
227 default 64000000
228endif
229
Patrick Delaunay2dc22162021-02-25 13:37:00 +0100230source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
Patrick Delaunay2514c2d2018-03-12 10:46:10 +0100231endif