Blame - arch/arm/mach-stm32mp/Kconfig - platform/external/u-boot

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Patrick Delaunay	2514c2d	2018-03-12 10:46:10 +0100	[diff] [blame]	1	if ARCH_STM32MP
				2
				3	config SPL
Patrick Delaunay	97f7e39	2020-07-24 11:13:31 +0200	[diff] [blame]	4	select SPL_BOARD_INIT
Patrick Delaunay	2514c2d	2018-03-12 10:46:10 +0100	[diff] [blame]	5	select SPL_CLK
				6	select SPL_DM
				7	select SPL_DM_SEQ_ALIAS
Simon Glass	9ca0068	2021-07-10 21:14:31 -0600	[diff] [blame]	8	select SPL_DRIVERS_MISC
Patrick Delaunay	2514c2d	2018-03-12 10:46:10 +0100	[diff] [blame]	9	select SPL_FRAMEWORK
Simon Glass	83061db	2021-07-10 21:14:30 -0600	[diff] [blame]	10	select SPL_GPIO
Patrick Delaunay	2514c2d	2018-03-12 10:46:10 +0100	[diff] [blame]	11	select SPL_LIBCOMMON_SUPPORT
				12	select SPL_LIBGENERIC_SUPPORT
				13	select SPL_OF_CONTROL
				14	select SPL_OF_TRANSLATE
				15	select SPL_PINCTRL
				16	select SPL_REGMAP
Ley Foon Tan	bfc6bae	2018-06-14 18:45:19 +0800	[diff] [blame]	17	select SPL_DM_RESET
Simon Glass	2a73606	2021-08-08 12:20:12 -0600	[diff] [blame]	18	select SPL_SERIAL
Patrick Delaunay	2514c2d	2018-03-12 10:46:10 +0100	[diff] [blame]	19	select SPL_SYSCON
Simon Glass	078111b	2021-07-10 21:14:28 -0600	[diff] [blame]	20	select SPL_WATCHDOG if WATCHDOG
Patrick Delaunay	27a986d	2019-04-18 17:32:47 +0200	[diff] [blame]	21	imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
				22	imply SPL_BOOTSTAGE if BOOTSTAGE
Patrick Delaunay	006ea18	2019-02-27 17:01:14 +0100	[diff] [blame]	23	imply SPL_DISPLAY_PRINT
Patrick Delaunay	2514c2d	2018-03-12 10:46:10 +0100	[diff] [blame]	24	imply SPL_LIBDISK_SUPPORT
Simon Glass	ea2ca7e	2021-08-08 12:20:14 -0600	[diff] [blame]	25	imply SPL_SPI_LOAD if SPL_SPI
Patrick Delaunay	2514c2d	2018-03-12 10:46:10 +0100	[diff] [blame]	26
				27	config SYS_SOC
				28	default "stm32mp"
				29
Patrick Delaunay	ef84ddd	2019-04-18 17:32:36 +0200	[diff] [blame]	30	config SYS_MALLOC_LEN
				31	default 0x2000000
				32
Patrick Delaunay	579a3e7	2019-04-18 17:32:37 +0200	[diff] [blame]	33	config ENV_SIZE
Patrice Chotard	1538e1a	2019-05-07 18:40:47 +0200	[diff] [blame]	34	default 0x2000
Patrick Delaunay	579a3e7	2019-04-18 17:32:37 +0200	[diff] [blame]	35
Patrick Delaunay	647d319	2022-05-20 18:24:43 +0200	[diff] [blame]	36	choice
				37	prompt "Select STMicroelectronics STM32MPxxx Soc"
				38	default STM32MP15x
				39
Patrick Delaunay	8462548	2020-01-13 15:17:42 +0100	[diff] [blame]	40	config STM32MP15x
				41	bool "Support STMicroelectronics STM32MP15x Soc"
Patrick Delaunay	17aeb58	2021-10-11 09:52:49 +0200	[diff] [blame]	42	select ARCH_SUPPORT_PSCI
Patrick Delaunay	5564b4c	2021-10-13 15:11:18 +0200	[diff] [blame]	43	select BINMAN
Lokesh Vutla	acf1500	2018-04-26 18:21:26 +0530	[diff] [blame]	44	select CPU_V7A
Patrick Delaunay	17aeb58	2021-10-11 09:52:49 +0200	[diff] [blame]	45	select CPU_V7_HAS_NONSEC
Patrick Delaunay	41c7977	2018-04-16 10:13:24 +0200	[diff] [blame]	46	select CPU_V7_HAS_VIRT
Patrice Chotard	22c0815	2022-01-20 08:19:15 +0100	[diff] [blame]	47	select OF_BOARD if TFABOOT
Patrick Delaunay	e81f8d1	2019-07-02 13:26:07 +0200	[diff] [blame]	48	select OF_BOARD_SETUP
Patrick Delaunay	2514c2d	2018-03-12 10:46:10 +0100	[diff] [blame]	49	select PINCTRL_STM32
Patrick Delaunay	d090cba	2018-07-09 15:17:20 +0200	[diff] [blame]	50	select STM32_RCC
Patrick Delaunay	2514c2d	2018-03-12 10:46:10 +0100	[diff] [blame]	51	select STM32_RESET
Patrick Delaunay	16a0722	2019-07-30 19:16:25 +0200	[diff] [blame]	52	select STM32_SERIAL
Patrick Delaunay	2ff0866	2022-05-20 18:24:40 +0200	[diff] [blame]	53	select SUPPORT_SPL
Andre Przywara	7842b6a	2018-04-12 04:24:46 +0300	[diff] [blame]	54	select SYS_ARCH_TIMER
Patrick Delaunay	c16cba8	2020-07-02 17:43:45 +0200	[diff] [blame]	55	imply CMD_NVEDIT_INFO
Patrick Delaunay	8462548	2020-01-13 15:17:42 +0100	[diff] [blame]	56	help
				57	support of STMicroelectronics SOC STM32MP15x family
				58	STM32MP157, STM32MP153 or STM32MP151
				59	STMicroelectronics MPU with core ARMv7
				60	dual core A7 for STM32MP157/3, monocore for STM32MP151
Patrick Delaunay	647d319	2022-05-20 18:24:43 +0200	[diff] [blame]	61	endchoice
				62
Patrick Delaunay	45ccdb6	2019-02-27 17:01:15 +0100	[diff] [blame]	63	config NR_DRAM_BANKS
				64	default 1
				65
Patrick Delaunay	67f9f11	2020-09-04 12:55:19 +0200	[diff] [blame]	66	config DDR_CACHEABLE_SIZE
				67	hex "Size of the DDR marked cacheable in pre-reloc stage"
Patrick Delaunay	67f9f11	2020-09-04 12:55:19 +0200	[diff] [blame]	68	default 0x40000000
				69	help
				70	Define the size of the DDR marked as cacheable in U-Boot
				71	pre-reloc stage.
				72	This option can be useful to avoid speculatif access
				73	to secured area of DDR used by TF-A or OP-TEE before U-Boot
				74	initialization.
				75	The areas marked "no-map" in device tree should be located
				76	before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
				77
Patrick Delaunay	11dfd1a	2018-03-20 10:54:54 +0100	[diff] [blame]	78	config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
				79	hex "Partition on MMC2 to use to load U-Boot from"
				80	depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
				81	default 1
				82	help
				83	Partition on the second MMC to load U-Boot from when the MMC is being
				84	used in raw mode
				85
Patrick Delaunay	c60f3b3	2019-07-05 17:20:15 +0200	[diff] [blame]	86	config STM32_ETZPC
				87	bool "STM32 Extended TrustZone Protection"
Patrick Delaunay	7a02e4d	2020-03-10 16:05:43 +0100	[diff] [blame]	88	depends on STM32MP15x
Patrick Delaunay	c60f3b3	2019-07-05 17:20:15 +0200	[diff] [blame]	89	default y
Simon Glass	d3877fb	2021-12-18 11:27:51 -0700	[diff] [blame]	90	imply BOOTP_SERVERIP
Patrick Delaunay	c60f3b3	2019-07-05 17:20:15 +0200	[diff] [blame]	91	help
				92	Say y to enable STM32 Extended TrustZone Protection
				93
Alexandru Gagniuc	ee87085	2021-07-29 11:47:17 -0500	[diff] [blame]	94	config STM32_ECDSA_VERIFY
				95	bool "STM32 ECDSA verification via the ROM API"
				96	depends on SPL_ECDSA_VERIFY
				97	default y
				98	help
				99	Say y to enable the uclass driver for ECDSA verification using the
				100	ROM API provided on STM32MP.
				101	The ROM API is only available during SPL for now.
				102
Patrick Delaunay	f4cb5d6	2019-07-05 17:20:17 +0200	[diff] [blame]	103	config CMD_STM32KEY
				104	bool "command stm32key to fuse public key hash"
Patrick Delaunay	f4cb5d6	2019-07-05 17:20:17 +0200	[diff] [blame]	105	help
				106	fuse public key hash in corresponding fuse used to authenticate
				107	binary.
Patrick Delaunay	3a99481	2021-06-28 14:55:57 +0200	[diff] [blame]	108	This command is used to evaluate the secure boot on stm32mp SOC,
				109	it is deactivated by default in real products.
Patrick Delaunay	f4cb5d6	2019-07-05 17:20:17 +0200	[diff] [blame]	110
Patrick Delaunay	d8b78fd	2022-05-20 18:24:44 +0200	[diff] [blame^]	111	source "arch/arm/mach-stm32mp/Kconfig.15x"
Patrick Delaunay	320d266	2018-05-17 14:50:46 +0200	[diff] [blame]	112
Patrick Delaunay	2dc2216	2021-02-25 13:37:00 +0100	[diff] [blame]	113	source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
Patrick Delaunay	2514c2d	2018-03-12 10:46:10 +0100	[diff] [blame]	114	endif