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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37#define CONFIG_MVS 1 /* ...on a MVsensor module */
38#define CONFIG_MVS_16BIT_FLASH /* ...with 16-bit flash access */
39#define CONFIG_8xx_GCLK_FREQ 50000000/* ... and a 50 MHz CPU */
40
41#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
42
43#undef CONFIG_8xx_CONS_SMC1 /* Console is *NOT* on SMC1 */
44#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
45#undef CONFIG_8xx_CONS_NONE
Wolfgang Denk53677ef2008-05-20 16:00:29 +020046#define CONFIG_BAUDRATE 115200 /* console baudrate */
wdenkc6097192002-11-03 00:24:07 +000047#define CONFIG_BOOTDELAY 5 /* autoboot after this many seconds */
48
Wolfgang Denk53677ef2008-05-20 16:00:29 +020049#define CONFIG_PREBOOT "echo;" \
50 "echo To mount root over NFS use \"run bootnet\";" \
51 "echo To mount root from FLASH use \"run bootflash\";" \
52 "echo"
wdenkc6097192002-11-03 00:24:07 +000053#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw"
Wolfgang Denk53677ef2008-05-20 16:00:29 +020054#define CONFIG_BOOTCOMMAND \
55 "bootp; " \
56 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
57 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
58 "bootm"
wdenkc6097192002-11-03 00:24:07 +000059
60#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkc6097192002-11-03 00:24:07 +000062
63#define CONFIG_WATCHDOG /* watchdog disabled/enabled */
64
65#undef CONFIG_STATUS_LED /* Status LED disabled/enabled */
66
Wolfgang Denk53677ef2008-05-20 16:00:29 +020067#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
wdenkc6097192002-11-03 00:24:07 +000068
Jon Loeliger7be044e2007-07-09 21:24:19 -050069
70/*
71 * BOOTP options
72 */
73#define CONFIG_BOOTP_SUBNETMASK
74#define CONFIG_BOOTP_GATEWAY
75#define CONFIG_BOOTP_HOSTNAME
76#define CONFIG_BOOTP_BOOTPATH
77#define CONFIG_BOOTP_VENDOREX
wdenkc6097192002-11-03 00:24:07 +000078
79#undef CONFIG_MAC_PARTITION
80#undef CONFIG_DOS_PARTITION
81
82#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
83
wdenkc6097192002-11-03 00:24:07 +000084
Jon Loeliger8353e132007-07-08 14:14:17 -050085/*
86 * Command line configuration.
87 */
88#define CONFIG_CMD_LOADS
89#define CONFIG_CMD_LOADB
90#define CONFIG_CMD_IMI
91#define CONFIG_CMD_FLASH
92#define CONFIG_CMD_MEMORY
93#define CONFIG_CMD_NET
94#define CONFIG_CMD_DHCP
Mike Frysingerbdab39d2009-01-28 19:08:14 -050095#define CONFIG_CMD_SAVEENV
Jon Loeliger8353e132007-07-08 14:14:17 -050096#define CONFIG_CMD_BOOTD
97#define CONFIG_CMD_RUN
98
wdenkc6097192002-11-03 00:24:07 +000099
100/*
101 * Miscellaneous configurable options
102 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#undef CONFIG_SYS_LONGHELP /* undef to save memory */
104#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenkc6097192002-11-03 00:24:07 +0000105
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot ?? */
107#ifdef CONFIG_SYS_HUSH_PARSER
108#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkc6097192002-11-03 00:24:07 +0000109#endif
110
Jon Loeliger8353e132007-07-08 14:14:17 -0500111#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000113#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000115#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
117#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
118#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
121#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkc6097192002-11-03 00:24:07 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc6097192002-11-03 00:24:07 +0000126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkc6097192002-11-03 00:24:07 +0000128
129/*
130 * Low Level Configuration Settings
131 * (address mappings, register initial values, etc.)
132 * You should know what you are doing if you make changes here.
133 */
134/*-----------------------------------------------------------------------
135 * Internal Memory Mapped Register
136 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_IMMR 0xFFF00000
wdenkc6097192002-11-03 00:24:07 +0000138
139/*-----------------------------------------------------------------------
140 * Definitions for initial stack pointer and data area (in DPRAM)
141 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
143#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
144#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
145#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
146#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000147
148/*-----------------------------------------------------------------------
149 * Start addresses for the final memory configuration
150 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000152 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_SDRAM_BASE 0x00000000
154#define CONFIG_SYS_FLASH_BASE 0x40000000
wdenkc6097192002-11-03 00:24:07 +0000155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 192 kB for Monitor */
wdenkc6097192002-11-03 00:24:07 +0000157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
159#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000160
161/*
162 * For booting Linux, the board info and command line data
163 * have to be in the first 8 MB of memory, since this is
164 * the maximum mapped by the Linux kernel during initialization.
165 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000167
168/*-----------------------------------------------------------------------
169 * FLASH organization
170 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
172#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip (for AMD320DB chip) */
wdenkc6097192002-11-03 00:24:07 +0000173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
175#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000176
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200177#define CONFIG_ENV_IS_IN_FLASH 1
wdenkc6097192002-11-03 00:24:07 +0000178
179/* 4MB flash - use bottom sectors of a bottom boot sector flash (16 bit access) */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200180#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector (bottom boot sector) */
181#define CONFIG_ENV_SIZE 0x2000 /* Used Size of Environment Sector 8k */
wdenkc6097192002-11-03 00:24:07 +0000182
183/*-----------------------------------------------------------------------
184 * Cache Configuration
185 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger8353e132007-07-08 14:14:17 -0500187#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkc6097192002-11-03 00:24:07 +0000189#endif
190
191/*-----------------------------------------------------------------------
192 * SYPCR - System Protection Control 11-9
193 * SYPCR can only be written once after reset!
194 *-----------------------------------------------------------------------
195 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
196 */
197#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200199 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
wdenkc6097192002-11-03 00:24:07 +0000200#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkc6097192002-11-03 00:24:07 +0000202#endif
203
204/*-----------------------------------------------------------------------
205 * SIUMCR - SIU Module Configuration 11-6
206 *-----------------------------------------------------------------------
207 * PCMCIA config., multi-function pin tri-state
208 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkc6097192002-11-03 00:24:07 +0000210
211/*-----------------------------------------------------------------------
212 * TBSCR - Time Base Status and Control 11-26
213 *-----------------------------------------------------------------------
214 * Clear Reference Interrupt Status, Timebase freezing enabled
215 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkc6097192002-11-03 00:24:07 +0000217
218/*-----------------------------------------------------------------------
219 * RTCSC - Real-Time Clock Status and Control Register 11-27
220 *-----------------------------------------------------------------------
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkc6097192002-11-03 00:24:07 +0000223
224/*-----------------------------------------------------------------------
225 * PISCR - Periodic Interrupt Status and Control 11-31
226 *-----------------------------------------------------------------------
227 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
228 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkc6097192002-11-03 00:24:07 +0000230
231/*-----------------------------------------------------------------------
232 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
233 *-----------------------------------------------------------------------
234 * Reset PLL lock status sticky bit, timer expired status bit and timer
235 * interrupt status bit
236 *
237 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkc6097192002-11-03 00:24:07 +0000239
240/*-----------------------------------------------------------------------
241 * SCCR - System Clock and reset Control Register 15-27
242 *-----------------------------------------------------------------------
243 * Set clock output, timebase and RTC source and divider,
244 * power management and some other internal clocks
245 */
246#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_SCCR (SCCR_TBS | \
wdenkc6097192002-11-03 00:24:07 +0000248 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
249 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
250 SCCR_DFALCD00)
251
252/*-----------------------------------------------------------------------
253 * PCMCIA stuff
254 *-----------------------------------------------------------------------
255 *
256 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
258#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
259#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
260#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
261#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
262#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
263#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
264#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkc6097192002-11-03 00:24:07 +0000265
266/*-----------------------------------------------------------------------
267 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
268 *-----------------------------------------------------------------------
269 */
270
271#define CONFIG_IDE_PCCARD 0 /* **DON'T** Use IDE with PC Card Adapter */
272
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200273#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
274#undef CONFIG_IDE_LED /* LED for ide not supported */
wdenkc6097192002-11-03 00:24:07 +0000275#undef CONFIG_IDE_RESET /* reset for ide not supported */
276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_IDE_MAXBUS 0 /* max. no. of IDE buses */
278#define CONFIG_SYS_IDE_MAXDEVICE 0 /* max. no. of drives per IDE bus */
wdenkc6097192002-11-03 00:24:07 +0000279
280
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkc6097192002-11-03 00:24:07 +0000282
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkc6097192002-11-03 00:24:07 +0000284
285/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkc6097192002-11-03 00:24:07 +0000287
288/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkc6097192002-11-03 00:24:07 +0000290
291/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkc6097192002-11-03 00:24:07 +0000293
294/*-----------------------------------------------------------------------
295 *
296 *-----------------------------------------------------------------------
297 *
298 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299/*#define CONFIG_SYS_DER 0x2002000F*/
300#define CONFIG_SYS_DER 0
wdenkc6097192002-11-03 00:24:07 +0000301
302/*
303 * Init Memory Controller:
304 *
305 * BR0/1 and OR0/1 (FLASH)
306 */
307
308#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
309#undef FLASH_BASE1_PRELIM
310
311/* used to re-map FLASH both when starting from SRAM or FLASH:
312 * restrict access enough to keep SRAM working (if any)
313 * but not too much to meddle with FLASH accesses
314 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
316#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkc6097192002-11-03 00:24:07 +0000317
318
319/*
320 * FLASH timing:
321 */
322/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkc6097192002-11-03 00:24:07 +0000324 OR_SCY_2_CLK | OR_EHTR | OR_BI)
325/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
326/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
wdenkc6097192002-11-03 00:24:07 +0000328 OR_SCY_5_CLK | OR_EHTR)
329*/
330
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
332#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
wdenkc6097192002-11-03 00:24:07 +0000333#ifdef CONFIG_MVS_16BIT_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
wdenkc6097192002-11-03 00:24:07 +0000335#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
wdenkc6097192002-11-03 00:24:07 +0000337#endif
338
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#undef CONFIG_SYS_OR1_REMAP
340#undef CONFIG_SYS_OR1_PRELIM
341#undef CONFIG_SYS_BR1_PRELIM
wdenkc6097192002-11-03 00:24:07 +0000342/*
343 * BR2/3 and OR2/3 (SDRAM)
344 *
345 */
346#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
347#undef SDRAM_BASE3_PRELIM
348#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
349
350/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkc6097192002-11-03 00:24:07 +0000352
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
354#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkc6097192002-11-03 00:24:07 +0000355
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#undef CONFIG_SYS_OR3_PRELIM
357#undef CONFIG_SYS_BR3_PRELIM
wdenkc6097192002-11-03 00:24:07 +0000358
359
360/*
361 * Memory Periodic Timer Prescaler
362 *
363 * The Divider for PTA (refresh timer) configuration is based on an
364 * example SDRAM configuration (64 MBit, one bank). The adjustment to
365 * the number of chip selects (NCS) and the actually needed refresh
366 * rate is done by setting MPTPR.
367 *
368 * PTA is calculated from
369 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
370 *
371 * gclk CPU clock (not bus clock!)
372 * Trefresh Refresh cycle * 4 (four word bursts used)
373 *
374 * 4096 Rows from SDRAM example configuration
375 * 1000 factor s -> ms
376 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
377 * 4 Number of refresh cycles per period
378 * 64 Refresh cycle in ms per number of rows
379 * --------------------------------------------
380 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
381 *
382 * 50 MHz => 50.000.000 / Divider = 98
383 * 66 Mhz => 66.000.000 / Divider = 129
384 * 80 Mhz => 80.000.000 / Divider = 156
385 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_MAMR_PTA 98
wdenkc6097192002-11-03 00:24:07 +0000387
388/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
390#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkc6097192002-11-03 00:24:07 +0000391
392/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
394#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkc6097192002-11-03 00:24:07 +0000395
396/*
397 * MAMR settings for SDRAM
398 */
399
400/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkc6097192002-11-03 00:24:07 +0000402 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
403 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
404/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkc6097192002-11-03 00:24:07 +0000406 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 | \
407 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
408
wdenkc6097192002-11-03 00:24:07 +0000409#endif /* __CONFIG_H */