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Marek Vasutd5914012011-01-19 04:40:37 +00001/*
2 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
3 *
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <asm/io.h>
27#include <asm/arch/imx-regs.h>
28#include <asm/arch/mx5x_pins.h>
29#include <asm/arch/iomux.h>
Stefano Babice70a1062011-08-21 10:53:32 +020030#include <asm/gpio.h>
Marek Vasutd5914012011-01-19 04:40:37 +000031#include <asm/errno.h>
32#include <asm/arch/sys_proto.h>
33#include <asm/arch/crm_regs.h>
34#include <i2c.h>
35#include <mmc.h>
36#include <fsl_esdhc.h>
Stefano Babic9c38f7d2011-10-06 11:44:26 +020037#include <pmic.h>
Marek Vasutd5914012011-01-19 04:40:37 +000038#include <fsl_pmic.h>
39#include <mc13892.h>
40
41DECLARE_GLOBAL_DATA_PTR;
42
43/*
44 * Compile-time error checking
45 */
46#ifndef CONFIG_MXC_SPI
47#error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
48#endif
49
50/*
51 * Shared variables / local defines
52 */
53/* LED */
54#define EFIKAMX_LED_BLUE 0x1
55#define EFIKAMX_LED_GREEN 0x2
56#define EFIKAMX_LED_RED 0x4
57
58void efikamx_toggle_led(uint32_t mask);
59
60/* Board revisions */
61#define EFIKAMX_BOARD_REV_11 0x1
62#define EFIKAMX_BOARD_REV_12 0x2
63#define EFIKAMX_BOARD_REV_13 0x3
64#define EFIKAMX_BOARD_REV_14 0x4
65
Marek Vasutaf708cb2011-09-25 09:55:43 +000066#define EFIKASB_BOARD_REV_13 0x1
67#define EFIKASB_BOARD_REV_20 0x2
68
Marek Vasutd5914012011-01-19 04:40:37 +000069/*
70 * Board identification
71 */
Marek Vasutaf708cb2011-09-25 09:55:43 +000072u32 get_efikamx_rev(void)
Marek Vasutd5914012011-01-19 04:40:37 +000073{
74 u32 rev = 0;
75 /*
76 * Retrieve board ID:
77 * rev1.1: 1,1,1
78 * rev1.2: 1,1,0
79 * rev1.3: 1,0,1
80 * rev1.4: 1,0,0
81 */
82 mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
Marek Vasutd5914012011-01-19 04:40:37 +000083 /* set to 1 in order to get correct value on board rev1.1 */
Stefano Babice70a1062011-08-21 10:53:32 +020084 gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1);
Marek Vasutd5914012011-01-19 04:40:37 +000085
86 mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
87 mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU);
Stefano Babice70a1062011-08-21 10:53:32 +020088 gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0));
89 rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0;
Marek Vasutd5914012011-01-19 04:40:37 +000090
91 mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO);
92 mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU);
Stefano Babice70a1062011-08-21 10:53:32 +020093 gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1));
94 rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1;
Marek Vasutd5914012011-01-19 04:40:37 +000095
96 mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO);
97 mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU);
Stefano Babice70a1062011-08-21 10:53:32 +020098 gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3));
99 rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2;
Marek Vasutd5914012011-01-19 04:40:37 +0000100
101 return (~rev & 0x7) + 1;
102}
103
Marek Vasutaf708cb2011-09-25 09:55:43 +0000104inline u32 get_efikasb_rev(void)
105{
106 u32 rev = 0;
107
108 mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_GPIO);
109 mxc_iomux_set_pad(MX51_PIN_EIM_CS3, PAD_CTL_100K_PU);
110 gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3));
111 rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3))) << 0;
112
113 mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_GPIO);
114 mxc_iomux_set_pad(MX51_PIN_EIM_CS4, PAD_CTL_100K_PU);
115 gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4));
116 rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4))) << 1;
117
118 return rev;
119}
120
121inline uint32_t get_efika_rev(void)
122{
123 if (machine_is_efikamx())
124 return get_efikamx_rev();
125 else
126 return get_efikasb_rev();
127}
128
Marek Vasutd5914012011-01-19 04:40:37 +0000129u32 get_board_rev(void)
130{
131 return get_cpu_rev() | (get_efika_rev() << 8);
132}
133
134/*
135 * DRAM initialization
136 */
137int dram_init(void)
138{
139 /* dram_init must store complete ramsize in gd->ram_size */
Albert ARIBAUDa55d23c2011-07-03 05:55:33 +0000140 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
Marek Vasutd5914012011-01-19 04:40:37 +0000141 PHYS_SDRAM_1_SIZE);
142 return 0;
143}
144
145/*
146 * UART configuration
147 */
148static void setup_iomux_uart(void)
149{
150 unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
151 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
152
153 mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
154 mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
155 mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
156 mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
157 mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
158 mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
159 mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
160 mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
161}
162
163/*
164 * SPI configuration
165 */
166#ifdef CONFIG_MXC_SPI
167static void setup_iomux_spi(void)
168{
169 /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
170 mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
171 mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
172 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
173
174 /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
175 mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
176 mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
177 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
178
179 /* Configure SS0 as a GPIO */
180 mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
Stefano Babice70a1062011-08-21 10:53:32 +0200181 gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0);
Marek Vasutd5914012011-01-19 04:40:37 +0000182
183 /* Configure SS1 as a GPIO */
184 mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO);
Stefano Babice70a1062011-08-21 10:53:32 +0200185 gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1);
Marek Vasutd5914012011-01-19 04:40:37 +0000186
187 /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
188 mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
189 mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY,
190 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
191
192 /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
193 mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
194 mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
195 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
196}
197#else
198static inline void setup_iomux_spi(void) { }
199#endif
200
201/*
202 * PMIC configuration
203 */
204#ifdef CONFIG_MXC_SPI
205static void power_init(void)
206{
207 unsigned int val;
208 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200209 struct pmic *p;
210
211 pmic_init();
212 p = get_pmic();
Marek Vasutd5914012011-01-19 04:40:37 +0000213
214 /* Write needed to Power Gate 2 register */
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200215 pmic_reg_read(p, REG_POWER_MISC, &val);
Marek Vasutd5914012011-01-19 04:40:37 +0000216 val &= ~PWGT2SPIEN;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200217 pmic_reg_write(p, REG_POWER_MISC, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000218
219 /* Externally powered */
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200220 pmic_reg_read(p, REG_CHARGE, &val);
Marek Vasutd5914012011-01-19 04:40:37 +0000221 val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200222 pmic_reg_write(p, REG_CHARGE, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000223
224 /* power up the system first */
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200225 pmic_reg_write(p, REG_POWER_MISC, PWUP);
Marek Vasutd5914012011-01-19 04:40:37 +0000226
227 /* Set core voltage to 1.1V */
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200228 pmic_reg_read(p, REG_SW_0, &val);
Marek Vasut55723952011-09-28 02:19:57 +0000229 val = (val & ~SWx_VOLT_MASK) | SWx_1_200V;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200230 pmic_reg_write(p, REG_SW_0, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000231
232 /* Setup VCC (SW2) to 1.25 */
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200233 pmic_reg_read(p, REG_SW_1, &val);
Marek Vasutd5914012011-01-19 04:40:37 +0000234 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200235 pmic_reg_write(p, REG_SW_1, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000236
237 /* Setup 1V2_DIG1 (SW3) to 1.25 */
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200238 pmic_reg_read(p, REG_SW_2, &val);
Marek Vasutd5914012011-01-19 04:40:37 +0000239 val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200240 pmic_reg_write(p, REG_SW_2, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000241 udelay(50);
242
243 /* Raise the core frequency to 800MHz */
244 writel(0x0, &mxc_ccm->cacrr);
245
246 /* Set switchers in Auto in NORMAL mode & STANDBY mode */
247 /* Setup the switcher mode for SW1 & SW2*/
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200248 pmic_reg_read(p, REG_SW_4, &val);
Marek Vasutd5914012011-01-19 04:40:37 +0000249 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
250 (SWMODE_MASK << SWMODE2_SHIFT)));
251 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
252 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200253 pmic_reg_write(p, REG_SW_4, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000254
255 /* Setup the switcher mode for SW3 & SW4 */
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200256 pmic_reg_read(p, REG_SW_5, &val);
Marek Vasutd5914012011-01-19 04:40:37 +0000257 val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
258 (SWMODE_MASK << SWMODE4_SHIFT)));
259 val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
260 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200261 pmic_reg_write(p, REG_SW_5, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000262
Marek Vasut55723952011-09-28 02:19:57 +0000263 /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200264 pmic_reg_read(p, REG_SETTING_0, &val);
Marek Vasutd5914012011-01-19 04:40:37 +0000265 val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
Marek Vasut55723952011-09-28 02:19:57 +0000266 val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200267 pmic_reg_write(p, REG_SETTING_0, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000268
269 /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200270 pmic_reg_read(p, REG_SETTING_1, &val);
Marek Vasutd5914012011-01-19 04:40:37 +0000271 val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
Marek Vasut55723952011-09-28 02:19:57 +0000272 val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200273 pmic_reg_write(p, REG_SETTING_1, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000274
Marek Vasut55723952011-09-28 02:19:57 +0000275 /* Enable VGEN1, VGEN2, VDIG, VPLL */
276 pmic_reg_read(p, REG_MODE_0, &val);
277 val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN;
278 pmic_reg_write(p, REG_MODE_0, val);
279
Marek Vasutd5914012011-01-19 04:40:37 +0000280 /* Configure VGEN3 and VCAM regulators to use external PNP */
281 val = VGEN3CONFIG | VCAMCONFIG;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200282 pmic_reg_write(p, REG_MODE_1, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000283 udelay(200);
284
285 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
286 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
Marek Vasut55723952011-09-28 02:19:57 +0000287 VVIDEOEN | VAUDIOEN | VSDEN;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200288 pmic_reg_write(p, REG_MODE_1, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000289
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200290 pmic_reg_read(p, REG_POWER_CTL2, &val);
Marek Vasutd5914012011-01-19 04:40:37 +0000291 val |= WDIRESET;
Stefano Babic9c38f7d2011-10-06 11:44:26 +0200292 pmic_reg_write(p, REG_POWER_CTL2, val);
Marek Vasutd5914012011-01-19 04:40:37 +0000293
294 udelay(2500);
295}
296#else
297static inline void power_init(void) { }
298#endif
299
300/*
301 * MMC configuration
302 */
303#ifdef CONFIG_FSL_ESDHC
304struct fsl_esdhc_cfg esdhc_cfg[2] = {
305 {MMC_SDHC1_BASE_ADDR, 1},
306 {MMC_SDHC2_BASE_ADDR, 1},
307};
308
Marek Vasutaf708cb2011-09-25 09:55:43 +0000309static inline uint32_t efika_mmc_cd(void)
310{
311 if (machine_is_efikamx())
312 return MX51_PIN_GPIO1_0;
313 else
314 return MX51_PIN_EIM_CS2;
315}
316
Marek Vasutd5914012011-01-19 04:40:37 +0000317int board_mmc_getcd(u8 *absent, struct mmc *mmc)
318{
319 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
Marek Vasutaf708cb2011-09-25 09:55:43 +0000320 uint32_t cd = efika_mmc_cd();
Marek Vasutd5914012011-01-19 04:40:37 +0000321
322 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
Marek Vasutaf708cb2011-09-25 09:55:43 +0000323 *absent = gpio_get_value(IOMUX_TO_GPIO(cd));
Marek Vasutd5914012011-01-19 04:40:37 +0000324 else
Stefano Babice70a1062011-08-21 10:53:32 +0200325 *absent = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
Marek Vasutd5914012011-01-19 04:40:37 +0000326
327 return 0;
328}
Marek Vasutaf708cb2011-09-25 09:55:43 +0000329
Marek Vasutd5914012011-01-19 04:40:37 +0000330int board_mmc_init(bd_t *bis)
331{
332 int ret;
Marek Vasutaf708cb2011-09-25 09:55:43 +0000333 uint32_t cd = efika_mmc_cd();
Marek Vasutd5914012011-01-19 04:40:37 +0000334
335 /* SDHC1 is used on all revisions, setup control pins first */
Marek Vasutaf708cb2011-09-25 09:55:43 +0000336 mxc_request_iomux(cd,
Marek Vasutd5914012011-01-19 04:40:37 +0000337 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
Marek Vasutaf708cb2011-09-25 09:55:43 +0000338 mxc_iomux_set_pad(cd,
Marek Vasutd5914012011-01-19 04:40:37 +0000339 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
340 PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
341 PAD_CTL_ODE_OPENDRAIN_NONE |
342 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
343 mxc_request_iomux(MX51_PIN_GPIO1_1,
344 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
345 mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
346 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
347 PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
348 PAD_CTL_SRE_FAST);
349
Marek Vasutaf708cb2011-09-25 09:55:43 +0000350 gpio_direction_input(IOMUX_TO_GPIO(cd));
Stefano Babice70a1062011-08-21 10:53:32 +0200351 gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1));
Marek Vasutd5914012011-01-19 04:40:37 +0000352
353 /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */
Marek Vasutaf708cb2011-09-25 09:55:43 +0000354 if (machine_is_efikasb() || (machine_is_efikamx() &&
355 (get_efika_rev() < EFIKAMX_BOARD_REV_12))) {
Marek Vasutd5914012011-01-19 04:40:37 +0000356 /* SDHC1 IOMUX */
357 mxc_request_iomux(MX51_PIN_SD1_CMD,
358 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
359 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
360 PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
361 PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
362
363 mxc_request_iomux(MX51_PIN_SD1_CLK,
364 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
365 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
366 PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
367 PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
368
369 mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
370 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
371 PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
372 PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
373
374 mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
375 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
376 PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
377 PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
378
379 mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
380 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
381 PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
382 PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
383
384 mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
385 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
386 PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
387 PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
388
389 /* SDHC2 IOMUX */
390 mxc_request_iomux(MX51_PIN_SD2_CMD,
391 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
392 mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
393 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
394
395 mxc_request_iomux(MX51_PIN_SD2_CLK,
396 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
397 mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
398 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
399
400 mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0);
401 mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
402 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
403
404 mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0);
405 mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
406 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
407
408 mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0);
409 mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
410 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
411
412 mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0);
413 mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
414 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
415
416 /* SDHC2 Control lines IOMUX */
417 mxc_request_iomux(MX51_PIN_GPIO1_7,
418 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
419 mxc_iomux_set_pad(MX51_PIN_GPIO1_7,
420 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
421 PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
422 PAD_CTL_ODE_OPENDRAIN_NONE |
423 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
424 mxc_request_iomux(MX51_PIN_GPIO1_8,
425 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
426 mxc_iomux_set_pad(MX51_PIN_GPIO1_8,
427 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
428 PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
429 PAD_CTL_SRE_FAST);
430
Stefano Babice70a1062011-08-21 10:53:32 +0200431 gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
432 gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7));
Marek Vasutd5914012011-01-19 04:40:37 +0000433
434 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
435 if (!ret)
436 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
437 } else { /* New boards use only SDHC1 */
438 /* SDHC1 IOMUX */
439 mxc_request_iomux(MX51_PIN_SD1_CMD,
440 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
441 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
442 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
443
444 mxc_request_iomux(MX51_PIN_SD1_CLK,
445 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
446 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
447 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
448
449 mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
450 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
451 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
452
453 mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
454 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
455 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
456
457 mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
458 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
459 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
460
461 mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
462 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
463 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
464
465 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
466 }
Marek Vasutaf708cb2011-09-25 09:55:43 +0000467
Marek Vasutd5914012011-01-19 04:40:37 +0000468 return ret;
469}
470#endif
471
472/*
473 * ATA
474 */
475#ifdef CONFIG_MX51_PATA
476#define ATA_PAD_CONFIG (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH)
477void setup_iomux_ata(void)
478{
479 mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1);
480 mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG);
481 mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1);
482 mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG);
483 mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1);
484 mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG);
485 mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1);
486 mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG);
487 mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1);
488 mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG);
489 mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1);
490 mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG);
491 mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1);
492 mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG);
493 mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1);
494 mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG);
495 mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1);
496 mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG);
497 mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1);
498 mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG);
499 mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1);
500 mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG);
501 mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1);
502 mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG);
503 mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1);
504 mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG);
505 mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1);
506 mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG);
507 mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1);
508 mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG);
509 mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1);
510 mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG);
511 mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1);
512 mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG);
513 mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1);
514 mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG);
515 mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1);
516 mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG);
517 mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1);
518 mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG);
519 mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1);
520 mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG);
521 mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1);
522 mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG);
523 mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1);
524 mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG);
525 mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1);
526 mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG);
527 mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1);
528 mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG);
529 mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1);
530 mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG);
531 mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1);
532 mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG);
533 mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1);
534 mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG);
535 mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1);
536 mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG);
537}
538#else
539static inline void setup_iomux_ata(void) { }
540#endif
541
542/*
543 * LED configuration
544 */
545void setup_iomux_led(void)
546{
Marek Vasutaf708cb2011-09-25 09:55:43 +0000547 if (machine_is_efikamx()) {
548 /* Blue LED */
549 mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3);
550 gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0);
Stefano Babice70a1062011-08-21 10:53:32 +0200551
Marek Vasutaf708cb2011-09-25 09:55:43 +0000552 /* Green LED */
553 mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3);
554 gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), 0);
Stefano Babice70a1062011-08-21 10:53:32 +0200555
Marek Vasutaf708cb2011-09-25 09:55:43 +0000556 /* Red LED */
557 mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3);
558 gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), 0);
559 } else {
560 /* CAPS-LOCK LED */
561 mxc_request_iomux(MX51_PIN_EIM_CS0, IOMUX_CONFIG_GPIO);
562 gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), 0);
563
564 /* ALARM-LED LED */
565 mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_GPIO);
566 gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), 0);
567 }
Marek Vasutd5914012011-01-19 04:40:37 +0000568}
569
570void efikamx_toggle_led(uint32_t mask)
571{
Marek Vasutaf708cb2011-09-25 09:55:43 +0000572 if (machine_is_efikamx()) {
573 gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),
574 mask & EFIKAMX_LED_BLUE);
575 gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),
576 mask & EFIKAMX_LED_GREEN);
577 gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),
578 mask & EFIKAMX_LED_RED);
579 } else {
580 gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0),
581 mask & EFIKAMX_LED_BLUE);
582 gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3),
583 !(mask & EFIKAMX_LED_GREEN));
584 }
Marek Vasutd5914012011-01-19 04:40:37 +0000585}
586
587/*
588 * Board initialization
589 */
590static void init_drive_strength(void)
591{
592 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
593 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
594 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
595 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
596 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
597 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
598 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
599 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
600 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
601 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
602 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
603 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
604 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
605 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
606 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
607 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
608 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
609 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
610 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
611 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
612 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
613 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
614 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
615 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
616 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
617 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
618 mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
619
620 /* Setting pad options */
621 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
622 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
623 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
624 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
625 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
626 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
627 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
628 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
629 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
630 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
631 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
632 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
633 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
634 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
635 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
636 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
637 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
638 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
639 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
640 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
641 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
642 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
643 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
644 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
645 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
646 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
647 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
648 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
649 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
650 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
651 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
652 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
653 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
654 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
655 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
656 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
657 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
658 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
659 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
660 mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
661 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
662 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
663}
664
665int board_early_init_f(void)
666{
667 init_drive_strength();
668
669 setup_iomux_uart();
670 setup_iomux_spi();
671 setup_iomux_led();
672
673 return 0;
674}
675
676int board_init(void)
677{
Marek Vasutd5914012011-01-19 04:40:37 +0000678 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
679
680 return 0;
681}
682
683int board_late_init(void)
684{
685 setup_iomux_spi();
686
687 power_init();
688
689 setup_iomux_led();
690 setup_iomux_ata();
691
692 efikamx_toggle_led(EFIKAMX_LED_BLUE);
693
694 return 0;
695}
696
697int checkboard(void)
698{
Marek Vasutaf708cb2011-09-25 09:55:43 +0000699 u32 rev = get_efika_rev();
700
701 if (machine_is_efikamx()) {
702 printf("Board: Efika MX, rev1.%i\n", rev & 0xf);
703 return 0;
704 } else {
705 switch (rev) {
706 case EFIKASB_BOARD_REV_13:
707 printf("Board: Efika SB rev1.3\n");
708 break;
709 case EFIKASB_BOARD_REV_20:
710 printf("Board: Efika SB rev2.0\n");
711 break;
712 default:
713 printf("Board: Efika SB, rev Unknown\n");
714 break;
715 }
716 }
Marek Vasutd5914012011-01-19 04:40:37 +0000717
718 return 0;
719}