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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / d9f8500b56734edf3e02a85aaa9af5866e60c0d4 / . / drivers / pinctrl / renesas / pfc-r8a77980.c
blob: 523faa0ac8f66efa915d24584828f62ee4bbd1ee [file] [log] [blame]
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R8A77980 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 *
Marek Vasuta2a14852021-04-26 22:04:11 +0200[diff] [blame]8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
14
15#include <common.h>
16#include <dm.h>
17#include <errno.h>
18#include <dm/pinctrl.h>
19#include <linux/kernel.h>
20
21#include "sh_pfc.h"
22
Marek Vasuta2a14852021-04-26 22:04:11 +0200[diff] [blame]23#define CPU_ALL_GP(fn, sfx) \
Marek Vasut827cece2023-09-17 16:08:44 +0200[diff] [blame]24 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]25 PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
Marek Vasut827cece2023-09-17 16:08:44 +0200[diff] [blame]26 PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
27 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]28 PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
29 PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
30
31#define CPU_ALL_NOGP(fn) \
32 PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
33 PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
34 PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
35 PIN_NOGP_CFG(DCUTRST_N, "DCUTRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
36 PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
37 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
38 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
39 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
Marek Vasut827cece2023-09-17 16:08:44 +0200[diff] [blame]40 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
41 PIN_NOGP_CFG(VDDQ_AVB, "VDDQ_AVB", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33), \
42 PIN_NOGP_CFG(VDDQ_GE, "VDDQ_GE", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]43
44/*
45 * F_() : just information
46 * FM() : macro for FN_xxx / xxx_MARK
47 */
48
49/* GPSR0 */
50#define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
51#define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
52#define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
53#define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
54#define GPSR0_17 F_(DU_DB7, IP2_7_4)
55#define GPSR0_16 F_(DU_DB6, IP2_3_0)
56#define GPSR0_15 F_(DU_DB5, IP1_31_28)
57#define GPSR0_14 F_(DU_DB4, IP1_27_24)
58#define GPSR0_13 F_(DU_DB3, IP1_23_20)
59#define GPSR0_12 F_(DU_DB2, IP1_19_16)
60#define GPSR0_11 F_(DU_DG7, IP1_15_12)
61#define GPSR0_10 F_(DU_DG6, IP1_11_8)
62#define GPSR0_9 F_(DU_DG5, IP1_7_4)
63#define GPSR0_8 F_(DU_DG4, IP1_3_0)
64#define GPSR0_7 F_(DU_DG3, IP0_31_28)
65#define GPSR0_6 F_(DU_DG2, IP0_27_24)
66#define GPSR0_5 F_(DU_DR7, IP0_23_20)
67#define GPSR0_4 F_(DU_DR6, IP0_19_16)
68#define GPSR0_3 F_(DU_DR5, IP0_15_12)
69#define GPSR0_2 F_(DU_DR4, IP0_11_8)
70#define GPSR0_1 F_(DU_DR3, IP0_7_4)
71#define GPSR0_0 F_(DU_DR2, IP0_3_0)
72
73/* GPSR1 */
74#define GPSR1_27 F_(DIGRF_CLKOUT, IP8_31_28)
75#define GPSR1_26 F_(DIGRF_CLKIN, IP8_27_24)
76#define GPSR1_25 F_(CANFD_CLK_A, IP8_23_20)
77#define GPSR1_24 F_(CANFD1_RX, IP8_19_16)
78#define GPSR1_23 F_(CANFD1_TX, IP8_15_12)
79#define GPSR1_22 F_(CANFD0_RX_A, IP8_11_8)
80#define GPSR1_21 F_(CANFD0_TX_A, IP8_7_4)
81#define GPSR1_20 F_(AVB_AVTP_CAPTURE, IP8_3_0)
82#define GPSR1_19 F_(AVB_AVTP_MATCH, IP7_31_28)
83#define GPSR1_18 FM(AVB_LINK)
84#define GPSR1_17 FM(AVB_PHY_INT)
85#define GPSR1_16 FM(AVB_MAGIC)
86#define GPSR1_15 FM(AVB_MDC)
87#define GPSR1_14 FM(AVB_MDIO)
88#define GPSR1_13 FM(AVB_TXCREFCLK)
89#define GPSR1_12 FM(AVB_TD3)
90#define GPSR1_11 FM(AVB_TD2)
91#define GPSR1_10 FM(AVB_TD1)
92#define GPSR1_9 FM(AVB_TD0)
93#define GPSR1_8 FM(AVB_TXC)
94#define GPSR1_7 FM(AVB_TX_CTL)
95#define GPSR1_6 FM(AVB_RD3)
96#define GPSR1_5 FM(AVB_RD2)
97#define GPSR1_4 FM(AVB_RD1)
98#define GPSR1_3 FM(AVB_RD0)
99#define GPSR1_2 FM(AVB_RXC)
100#define GPSR1_1 FM(AVB_RX_CTL)
101#define GPSR1_0 F_(IRQ0, IP2_27_24)
102
103/* GPSR2 */
Marek Vasut827cece2023-09-17 16:08:44 +0200[diff] [blame]104#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]105#define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12)
106#define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8)
107#define GPSR2_26 F_(SDA3, IP10_7_4)
108#define GPSR2_25 F_(SCL3, IP10_3_0)
109#define GPSR2_24 F_(MSIOF0_SS2, IP9_31_28)
110#define GPSR2_23 F_(MSIOF0_SS1, IP9_27_24)
111#define GPSR2_22 F_(MSIOF0_SYNC, IP9_23_20)
112#define GPSR2_21 F_(MSIOF0_SCK, IP9_19_16)
113#define GPSR2_20 F_(MSIOF0_TXD, IP9_15_12)
114#define GPSR2_19 F_(MSIOF0_RXD, IP9_11_8)
115#define GPSR2_18 F_(IRQ5, IP9_7_4)
116#define GPSR2_17 F_(IRQ4, IP9_3_0)
117#define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
118#define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
119#define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
120#define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
121#define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
122#define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
123#define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
124#define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
125#define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
126#define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
127#define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
128#define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
129#define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
130#define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
131#define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
132#define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
133#define GPSR2_0 F_(VI0_CLK, IP2_31_28)
134
135/* GPSR3 */
136#define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
137#define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
138#define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
139#define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
140#define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
141#define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
142#define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
143#define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
144#define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
145#define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
146#define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
147#define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
148#define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
149#define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
150#define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
151#define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
152#define GPSR3_0 F_(VI1_CLK, IP5_3_0)
153
154/* GPSR4 */
155#define GPSR4_24 FM(GETHER_LINK_A)
156#define GPSR4_23 FM(GETHER_PHY_INT_A)
157#define GPSR4_22 FM(GETHER_MAGIC)
158#define GPSR4_21 FM(GETHER_MDC_A)
159#define GPSR4_20 FM(GETHER_MDIO_A)
160#define GPSR4_19 FM(GETHER_TXCREFCLK_MEGA)
161#define GPSR4_18 FM(GETHER_TXCREFCLK)
162#define GPSR4_17 FM(GETHER_TD3)
163#define GPSR4_16 FM(GETHER_TD2)
164#define GPSR4_15 FM(GETHER_TD1)
165#define GPSR4_14 FM(GETHER_TD0)
166#define GPSR4_13 FM(GETHER_TXC)
167#define GPSR4_12 FM(GETHER_TX_CTL)
168#define GPSR4_11 FM(GETHER_RD3)
169#define GPSR4_10 FM(GETHER_RD2)
170#define GPSR4_9 FM(GETHER_RD1)
171#define GPSR4_8 FM(GETHER_RD0)
172#define GPSR4_7 FM(GETHER_RXC)
173#define GPSR4_6 FM(GETHER_RX_CTL)
174#define GPSR4_5 F_(SDA2, IP7_27_24)
175#define GPSR4_4 F_(SCL2, IP7_23_20)
176#define GPSR4_3 F_(SDA1, IP7_19_16)
177#define GPSR4_2 F_(SCL1, IP7_15_12)
178#define GPSR4_1 F_(SDA0, IP7_11_8)
179#define GPSR4_0 F_(SCL0, IP7_7_4)
180
181/* GPSR5 */
182#define GPSR5_14 FM(RPC_INT_N)
183#define GPSR5_13 FM(RPC_WP_N)
184#define GPSR5_12 FM(RPC_RESET_N)
185#define GPSR5_11 FM(QSPI1_SSL)
186#define GPSR5_10 FM(QSPI1_IO3)
187#define GPSR5_9 FM(QSPI1_IO2)
188#define GPSR5_8 FM(QSPI1_MISO_IO1)
189#define GPSR5_7 FM(QSPI1_MOSI_IO0)
190#define GPSR5_6 FM(QSPI1_SPCLK)
191#define GPSR5_5 FM(QSPI0_SSL)
192#define GPSR5_4 FM(QSPI0_IO3)
193#define GPSR5_3 FM(QSPI0_IO2)
194#define GPSR5_2 FM(QSPI0_MISO_IO1)
195#define GPSR5_1 FM(QSPI0_MOSI_IO0)
196#define GPSR5_0 FM(QSPI0_SPCLK)
197
198
199/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
200#define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201#define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202#define IP0_11_8 FM(DU_DR4) FM(TX4) FM(GETHER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203#define IP0_15_12 FM(DU_DR5) FM(CTS4_N) FM(GETHER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204#define IP0_19_16 FM(DU_DR6) FM(RTS4_N) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205#define IP0_23_20 FM(DU_DR7) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206#define IP0_27_24 FM(DU_DG2) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207#define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208#define IP1_3_0 FM(DU_DG4) FM(SCL5) F_(0, 0) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209#define IP1_7_4 FM(DU_DG5) FM(SDA5) FM(GETHER_MDC_B) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210#define IP1_11_8 FM(DU_DG6) FM(SCIF_CLK_A) FM(GETHER_MDIO_B) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211#define IP1_15_12 FM(DU_DG7) FM(HRX0_A) F_(0, 0) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212#define IP1_19_16 FM(DU_DB2) FM(HSCK0_A) F_(0, 0) FM(A12) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP1_23_20 FM(DU_DB3) FM(HRTS0_N_A) F_(0, 0) FM(A13) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP1_27_24 FM(DU_DB4) FM(HCTS0_N_A) F_(0, 0) FM(A14) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP1_31_28 FM(DU_DB5) FM(HTX0_A) FM(PWM0_A) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP2_3_0 FM(DU_DB6) FM(MSIOF3_RXD) F_(0, 0) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP2_7_4 FM(DU_DB7) FM(MSIOF3_TXD) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP2_11_8 FM(DU_DOTCLKOUT) FM(MSIOF3_SS1) FM(GETHER_LINK_B) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(MSIOF3_SS2) FM(GETHER_PHY_INT_B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP3_23_20 FM(VI0_DATA2) FM(AVB_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP6_7_4 FM(VI1_DATA5) F_(0, 0) F_(0, 0) FM(D8) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP6_11_8 FM(VI1_DATA6) F_(0, 0) F_(0, 0) FM(D9) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP6_15_12 FM(VI1_DATA7) F_(0, 0) F_(0, 0) FM(D10) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP6_19_16 FM(VI1_DATA8) F_(0, 0) F_(0, 0) FM(D11) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP6_23_20 FM(VI1_DATA9) FM(TCLK1_A) F_(0, 0) FM(D12) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP6_27_24 FM(VI1_DATA10) FM(TCLK2_A) F_(0, 0) FM(D13) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) F_(0, 0) FM(D14) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) F_(0, 0) FM(D15) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP7_7_4 FM(SCL0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP7_11_8 FM(SDA0) F_(0, 0) F_(0, 0) FM(BS_N) FM(SCK0) FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP7_15_12 FM(SCL1) F_(0, 0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(HCTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP7_23_20 FM(SCL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP7_27_24 FM(SDA2) F_(0, 0) F_(0, 0) FM(EX_WAIT0) FM(TX0) FM(HTX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP7_31_28 FM(AVB_AVTP_MATCH) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP8_3_0 FM(AVB_AVTP_CAPTURE) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP8_7_4 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut827cece2023-09-17 16:08:44 +0200[diff] [blame]269#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]270#define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut827cece2023-09-17 16:08:44 +0200[diff] [blame]273#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]274#define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP9_23_20 FM(MSIOF0_SYNC) FM(DU_DG1) F_(0, 0) FM(VI0_DATA17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP9_27_24 FM(MSIOF0_SS1) FM(DU_DB0) FM(TCLK3) FM(VI0_DATA18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP9_31_28 FM(MSIOF0_SS2) FM(DU_DB1) FM(TCLK4) FM(VI0_DATA19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP10_3_0 FM(SCL3) F_(0, 0) F_(0, 0) FM(VI0_DATA20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP10_7_4 FM(SDA3) F_(0, 0) F_(0, 0) FM(VI0_DATA21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP10_11_8 FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) FM(VI0_DATA22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP10_15_12 FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) FM(VI0_DATA23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP10_19_16 FM(FSO_TOE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]285
286#define PINMUX_GPSR \
287\
288 GPSR2_29 \
289 GPSR2_28 \
290 GPSR1_27 GPSR2_27 \
291 GPSR1_26 GPSR2_26 \
292 GPSR1_25 GPSR2_25 \
293 GPSR1_24 GPSR2_24 GPSR4_24 \
294 GPSR1_23 GPSR2_23 GPSR4_23 \
295 GPSR1_22 GPSR2_22 GPSR4_22 \
296GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \
297GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 \
298GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 \
299GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 \
300GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 \
301GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 \
302GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 \
303GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 \
304GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 \
305GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 \
306GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 \
307GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 \
308GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 \
309GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 \
310GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 \
311GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 \
312GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
313GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
314GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
315GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
316GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
317GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
318
319#define PINMUX_IPSR \
320\
321FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
322FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
323FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
324FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
325FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
326FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
327FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
328FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
329\
330FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
331FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
332FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
333FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
334FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
335FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
336FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
337FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
338\
339FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 \
340FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 \
341FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 \
342FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 \
343FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 \
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]344FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 \
345FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 \
346FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]347
348/* MOD_SEL0 */ /* 0 */ /* 1 */
349#define MOD_SEL0_11 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
350#define MOD_SEL0_10 FM(SEL_GETHER_0) FM(SEL_GETHER_1)
351#define MOD_SEL0_9 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
352#define MOD_SEL0_8 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
353#define MOD_SEL0_7 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
354#define MOD_SEL0_6 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
355#define MOD_SEL0_5 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
356#define MOD_SEL0_4 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
357#define MOD_SEL0_2 FM(SEL_RSP_0) FM(SEL_RSP_1)
358#define MOD_SEL0_1 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
359#define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
360
361#define PINMUX_MOD_SELS \
362\
363MOD_SEL0_11 \
364MOD_SEL0_10 \
365MOD_SEL0_9 \
366MOD_SEL0_8 \
367MOD_SEL0_7 \
368MOD_SEL0_6 \
369MOD_SEL0_5 \
370MOD_SEL0_4 \
371MOD_SEL0_2 \
372MOD_SEL0_1 \
373MOD_SEL0_0
374
375enum {
376 PINMUX_RESERVED = 0,
377
378 PINMUX_DATA_BEGIN,
379 GP_ALL(DATA),
380 PINMUX_DATA_END,
381
382#define F_(x, y)
383#define FM(x) FN_##x,
384 PINMUX_FUNCTION_BEGIN,
385 GP_ALL(FN),
386 PINMUX_GPSR
387 PINMUX_IPSR
388 PINMUX_MOD_SELS
389 PINMUX_FUNCTION_END,
390#undef F_
391#undef FM
392
393#define F_(x, y)
394#define FM(x) x##_MARK,
395 PINMUX_MARK_BEGIN,
396 PINMUX_GPSR
397 PINMUX_IPSR
398 PINMUX_MOD_SELS
399 PINMUX_MARK_END,
400#undef F_
401#undef FM
402};
403
404static const u16 pinmux_data[] = {
405 PINMUX_DATA_GP_ALL(),
406
407 PINMUX_SINGLE(AVB_RX_CTL),
408 PINMUX_SINGLE(AVB_RXC),
409 PINMUX_SINGLE(AVB_RD0),
410 PINMUX_SINGLE(AVB_RD1),
411 PINMUX_SINGLE(AVB_RD2),
412 PINMUX_SINGLE(AVB_RD3),
413 PINMUX_SINGLE(AVB_TX_CTL),
414 PINMUX_SINGLE(AVB_TXC),
415 PINMUX_SINGLE(AVB_TD0),
416 PINMUX_SINGLE(AVB_TD1),
417 PINMUX_SINGLE(AVB_TD2),
418 PINMUX_SINGLE(AVB_TD3),
419 PINMUX_SINGLE(AVB_TXCREFCLK),
420 PINMUX_SINGLE(AVB_MDIO),
421 PINMUX_SINGLE(AVB_MDC),
422 PINMUX_SINGLE(AVB_MAGIC),
423 PINMUX_SINGLE(AVB_PHY_INT),
424 PINMUX_SINGLE(AVB_LINK),
425
426 PINMUX_SINGLE(GETHER_RX_CTL),
427 PINMUX_SINGLE(GETHER_RXC),
428 PINMUX_SINGLE(GETHER_RD0),
429 PINMUX_SINGLE(GETHER_RD1),
430 PINMUX_SINGLE(GETHER_RD2),
431 PINMUX_SINGLE(GETHER_RD3),
432 PINMUX_SINGLE(GETHER_TX_CTL),
433 PINMUX_SINGLE(GETHER_TXC),
434 PINMUX_SINGLE(GETHER_TD0),
435 PINMUX_SINGLE(GETHER_TD1),
436 PINMUX_SINGLE(GETHER_TD2),
437 PINMUX_SINGLE(GETHER_TD3),
438 PINMUX_SINGLE(GETHER_TXCREFCLK),
439 PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA),
440 PINMUX_SINGLE(GETHER_MDIO_A),
441 PINMUX_SINGLE(GETHER_MDC_A),
442 PINMUX_SINGLE(GETHER_MAGIC),
443 PINMUX_SINGLE(GETHER_PHY_INT_A),
444 PINMUX_SINGLE(GETHER_LINK_A),
445
446 PINMUX_SINGLE(QSPI0_SPCLK),
447 PINMUX_SINGLE(QSPI0_MOSI_IO0),
448 PINMUX_SINGLE(QSPI0_MISO_IO1),
449 PINMUX_SINGLE(QSPI0_IO2),
450 PINMUX_SINGLE(QSPI0_IO3),
451 PINMUX_SINGLE(QSPI0_SSL),
452 PINMUX_SINGLE(QSPI1_SPCLK),
453 PINMUX_SINGLE(QSPI1_MOSI_IO0),
454 PINMUX_SINGLE(QSPI1_MISO_IO1),
455 PINMUX_SINGLE(QSPI1_IO2),
456 PINMUX_SINGLE(QSPI1_IO3),
457 PINMUX_SINGLE(QSPI1_SSL),
458 PINMUX_SINGLE(RPC_RESET_N),
459 PINMUX_SINGLE(RPC_WP_N),
460 PINMUX_SINGLE(RPC_INT_N),
461
462 /* IPSR0 */
463 PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
464 PINMUX_IPSR_GPSR(IP0_3_0, SCK4),
465 PINMUX_IPSR_GPSR(IP0_3_0, GETHER_RMII_CRS_DV),
466 PINMUX_IPSR_GPSR(IP0_3_0, A0),
467
468 PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
469 PINMUX_IPSR_GPSR(IP0_7_4, RX4),
470 PINMUX_IPSR_GPSR(IP0_7_4, GETHER_RMII_RX_ER),
471 PINMUX_IPSR_GPSR(IP0_7_4, A1),
472
473 PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
474 PINMUX_IPSR_GPSR(IP0_11_8, TX4),
475 PINMUX_IPSR_GPSR(IP0_11_8, GETHER_RMII_RXD0),
476 PINMUX_IPSR_GPSR(IP0_11_8, A2),
477
478 PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
479 PINMUX_IPSR_GPSR(IP0_15_12, CTS4_N),
480 PINMUX_IPSR_GPSR(IP0_15_12, GETHER_RMII_RXD1),
481 PINMUX_IPSR_GPSR(IP0_15_12, A3),
482
483 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
484 PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N),
485 PINMUX_IPSR_GPSR(IP0_19_16, GETHER_RMII_TXD_EN),
486 PINMUX_IPSR_GPSR(IP0_19_16, A4),
487
488 PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
489 PINMUX_IPSR_GPSR(IP0_23_20, GETHER_RMII_TXD0),
490 PINMUX_IPSR_GPSR(IP0_23_20, A5),
491
492 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
493 PINMUX_IPSR_GPSR(IP0_27_24, GETHER_RMII_TXD1),
494 PINMUX_IPSR_GPSR(IP0_27_24, A6),
495
496 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
497 PINMUX_IPSR_GPSR(IP0_31_28, CPG_CPCKOUT),
498 PINMUX_IPSR_GPSR(IP0_31_28, GETHER_RMII_REFCLK),
499 PINMUX_IPSR_GPSR(IP0_31_28, A7),
500 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
501
502 /* IPSR1 */
503 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
504 PINMUX_IPSR_GPSR(IP1_3_0, SCL5),
505 PINMUX_IPSR_GPSR(IP1_3_0, A8),
506
507 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
508 PINMUX_IPSR_GPSR(IP1_7_4, SDA5),
509 PINMUX_IPSR_MSEL(IP1_7_4, GETHER_MDC_B, SEL_GETHER_1),
510 PINMUX_IPSR_GPSR(IP1_7_4, A9),
511
512 PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
513 PINMUX_IPSR_MSEL(IP1_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
514 PINMUX_IPSR_MSEL(IP1_11_8, GETHER_MDIO_B, SEL_GETHER_1),
515 PINMUX_IPSR_GPSR(IP1_11_8, A10),
516
517 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
518 PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0),
519 PINMUX_IPSR_GPSR(IP1_15_12, A11),
520
521 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
522 PINMUX_IPSR_MSEL(IP1_19_16, HSCK0_A, SEL_HSCIF0_0),
523 PINMUX_IPSR_GPSR(IP1_19_16, A12),
524 PINMUX_IPSR_GPSR(IP1_19_16, IRQ1),
525
526 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
527 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_A, SEL_HSCIF0_0),
528 PINMUX_IPSR_GPSR(IP1_23_20, A13),
529 PINMUX_IPSR_GPSR(IP1_23_20, IRQ2),
530
531 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
532 PINMUX_IPSR_MSEL(IP1_27_24, HCTS0_N_A, SEL_HSCIF0_0),
533 PINMUX_IPSR_GPSR(IP1_27_24, A14),
534 PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
535
536 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
537 PINMUX_IPSR_MSEL(IP1_31_28, HTX0_A, SEL_HSCIF0_0),
538 PINMUX_IPSR_MSEL(IP1_31_28, PWM0_A, SEL_PWM0_0),
539 PINMUX_IPSR_GPSR(IP1_31_28, A15),
540
541 /* IPSR2 */
542 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
543 PINMUX_IPSR_GPSR(IP2_3_0, MSIOF3_RXD),
544 PINMUX_IPSR_GPSR(IP2_3_0, A16),
545
546 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
547 PINMUX_IPSR_GPSR(IP2_7_4, MSIOF3_TXD),
548 PINMUX_IPSR_GPSR(IP2_7_4, A17),
549
550 PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
551 PINMUX_IPSR_GPSR(IP2_11_8, MSIOF3_SS1),
552 PINMUX_IPSR_MSEL(IP2_11_8, GETHER_LINK_B, SEL_GETHER_1),
553 PINMUX_IPSR_GPSR(IP2_11_8, A18),
554
555 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
556 PINMUX_IPSR_GPSR(IP2_15_12, MSIOF3_SS2),
557 PINMUX_IPSR_MSEL(IP2_15_12, GETHER_PHY_INT_B, SEL_GETHER_1),
558 PINMUX_IPSR_GPSR(IP2_15_12, A19),
559 PINMUX_IPSR_GPSR(IP2_15_12, FXR_TXENA_N),
560
561 PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
562 PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
563 PINMUX_IPSR_GPSR(IP2_19_16, FXR_TXENB_N),
564
565 PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
566 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
567
568 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
569
570 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
571 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
572 PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
573 PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
574
575 /* IPSR3 */
576 PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
577 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
578 PINMUX_IPSR_GPSR(IP3_3_0, RX3),
579 PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
580 PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
581
582 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
583 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
584 PINMUX_IPSR_GPSR(IP3_7_4, TX3),
585 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
586
587 PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
588 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
589 PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
590 PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
591
592 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
593 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
594 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
595 PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
596
597 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
598 PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
599 PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
600 PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
601
602 PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
603 PINMUX_IPSR_GPSR(IP3_23_20, AVB_AVTP_PPS),
604
605 PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
606 PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
607
608 PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
609 PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
610 PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
611
612 /* IPSR4 */
613 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
614 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
615 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
616
617 PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
618 PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
619 PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
620
621 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
622 PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
623 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
624
625 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
626 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
627
628 PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
629 PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
630 PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
631
632 PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
633 PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
634 PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
635
636 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
637 PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
638 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
639
640 PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
641 PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
642 PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
643 PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
644
645 /* IPSR5 */
646 PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
647 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
648 PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
649
650 PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
651 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
652 PINMUX_IPSR_GPSR(IP5_7_4, D0),
653
654 PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
655 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
656 PINMUX_IPSR_GPSR(IP5_11_8, D1),
657
658 PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
659 PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
660 PINMUX_IPSR_GPSR(IP5_15_12, D2),
661
662 PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
663 PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
664 PINMUX_IPSR_GPSR(IP5_19_16, D3),
665 PINMUX_IPSR_GPSR(IP5_19_16, MMC_WP),
666
667 PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
668 PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
669 PINMUX_IPSR_GPSR(IP5_23_20, D4),
670 PINMUX_IPSR_GPSR(IP5_23_20, MMC_CD),
671
672 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
673 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
674 PINMUX_IPSR_GPSR(IP5_27_24, D5),
675 PINMUX_IPSR_GPSR(IP5_27_24, MMC_DS),
676
677 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
678 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
679 PINMUX_IPSR_GPSR(IP5_31_28, D6),
680 PINMUX_IPSR_GPSR(IP5_31_28, MMC_CMD),
681
682 /* IPSR6 */
683 PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
684 PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
685 PINMUX_IPSR_GPSR(IP6_3_0, D7),
686 PINMUX_IPSR_GPSR(IP6_3_0, MMC_D0),
687
688 PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
689 PINMUX_IPSR_GPSR(IP6_7_4, D8),
690 PINMUX_IPSR_GPSR(IP6_7_4, MMC_D1),
691
692 PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
693 PINMUX_IPSR_GPSR(IP6_11_8, D9),
694 PINMUX_IPSR_GPSR(IP6_11_8, MMC_D2),
695
696 PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
697 PINMUX_IPSR_GPSR(IP6_15_12, D10),
698 PINMUX_IPSR_GPSR(IP6_15_12, MMC_D3),
699
700 PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
701 PINMUX_IPSR_GPSR(IP6_19_16, D11),
702 PINMUX_IPSR_GPSR(IP6_19_16, MMC_CLK),
703
704 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
705 PINMUX_IPSR_MSEL(IP6_23_20, TCLK1_A, SEL_TMU_0),
706 PINMUX_IPSR_GPSR(IP6_23_20, D12),
707 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D4),
708
709 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
710 PINMUX_IPSR_MSEL(IP6_27_24, TCLK2_A, SEL_TMU_0),
711 PINMUX_IPSR_GPSR(IP6_27_24, D13),
712 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D5),
713
714 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
715 PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
716 PINMUX_IPSR_GPSR(IP6_31_28, D14),
717 PINMUX_IPSR_GPSR(IP6_31_28, MMC_D6),
718
719 /* IPSR7 */
720 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
721 PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
722 PINMUX_IPSR_GPSR(IP7_3_0, D15),
723 PINMUX_IPSR_GPSR(IP7_3_0, MMC_D7),
724
725 PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
726 PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
727
728 PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
729 PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
730 PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
731 PINMUX_IPSR_MSEL(IP7_11_8, HSCK0_B, SEL_HSCIF0_1),
732
733 PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
734 PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
735 PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
736 PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
737 PINMUX_IPSR_GPSR(IP7_15_12, HCTS0_N_B),
738
739 PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
740 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
741 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
742 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
743 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_B, SEL_HSCIF0_1),
744
745 PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
746 PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
747 PINMUX_IPSR_GPSR(IP7_23_20, RX0),
748 PINMUX_IPSR_MSEL(IP7_23_20, HRX0_B, SEL_HSCIF0_1),
749
750 PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
751 PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
752 PINMUX_IPSR_GPSR(IP7_27_24, TX0),
753 PINMUX_IPSR_MSEL(IP7_27_24, HTX0_B, SEL_HSCIF0_1),
754
755 PINMUX_IPSR_GPSR(IP7_31_28, AVB_AVTP_MATCH),
756 PINMUX_IPSR_GPSR(IP7_31_28, TPU0TO0),
757
758 /* IPSR8 */
759 PINMUX_IPSR_GPSR(IP8_3_0, AVB_AVTP_CAPTURE),
760 PINMUX_IPSR_GPSR(IP8_3_0, TPU0TO1),
761
762 PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_TX_A, SEL_CANFD0_0),
763 PINMUX_IPSR_GPSR(IP8_7_4, FXR_TXDA),
764 PINMUX_IPSR_MSEL(IP8_7_4, PWM0_B, SEL_PWM0_1),
765 PINMUX_IPSR_GPSR(IP8_7_4, DU_DISP),
766
767 PINMUX_IPSR_MSEL(IP8_11_8, CANFD0_RX_A, SEL_CANFD0_0),
768 PINMUX_IPSR_GPSR(IP8_11_8, RXDA_EXTFXR),
769 PINMUX_IPSR_MSEL(IP8_11_8, PWM1_B, SEL_PWM1_1),
770 PINMUX_IPSR_GPSR(IP8_11_8, DU_CDE),
771
772 PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_TX),
773 PINMUX_IPSR_GPSR(IP8_15_12, FXR_TXDB),
774 PINMUX_IPSR_MSEL(IP8_15_12, PWM2_B, SEL_PWM2_1),
775 PINMUX_IPSR_MSEL(IP8_15_12, TCLK1_B, SEL_TMU_1),
776 PINMUX_IPSR_MSEL(IP8_15_12, TX1_B, SEL_SCIF1_1),
777
778 PINMUX_IPSR_GPSR(IP8_19_16, CANFD1_RX),
779 PINMUX_IPSR_GPSR(IP8_19_16, RXDB_EXTFXR),
780 PINMUX_IPSR_MSEL(IP8_19_16, PWM3_B, SEL_PWM3_1),
781 PINMUX_IPSR_MSEL(IP8_19_16, TCLK2_B, SEL_TMU_1),
782 PINMUX_IPSR_MSEL(IP8_19_16, RX1_B, SEL_SCIF1_1),
783
784 PINMUX_IPSR_MSEL(IP8_23_20, CANFD_CLK_A, SEL_CANFD0_0),
785 PINMUX_IPSR_GPSR(IP8_23_20, CLK_EXTFXR),
786 PINMUX_IPSR_MSEL(IP8_23_20, PWM4_B, SEL_PWM4_1),
787 PINMUX_IPSR_MSEL(IP8_23_20, SPEEDIN_B, SEL_RSP_1),
788 PINMUX_IPSR_MSEL(IP8_23_20, SCIF_CLK_B, SEL_HSCIF0_1),
789
790 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKIN),
791 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_IN),
792
793 PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKOUT),
794 PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKEN_OUT),
795
796 /* IPSR9 */
797 PINMUX_IPSR_GPSR(IP9_3_0, IRQ4),
798 PINMUX_IPSR_GPSR(IP9_3_0, VI0_DATA12),
799
800 PINMUX_IPSR_GPSR(IP9_7_4, IRQ5),
801 PINMUX_IPSR_GPSR(IP9_7_4, VI0_DATA13),
802
803 PINMUX_IPSR_GPSR(IP9_11_8, MSIOF0_RXD),
804 PINMUX_IPSR_GPSR(IP9_11_8, DU_DR0),
805 PINMUX_IPSR_GPSR(IP9_11_8, VI0_DATA14),
806
807 PINMUX_IPSR_GPSR(IP9_15_12, MSIOF0_TXD),
808 PINMUX_IPSR_GPSR(IP9_15_12, DU_DR1),
809 PINMUX_IPSR_GPSR(IP9_15_12, VI0_DATA15),
810
811 PINMUX_IPSR_GPSR(IP9_19_16, MSIOF0_SCK),
812 PINMUX_IPSR_GPSR(IP9_19_16, DU_DG0),
813 PINMUX_IPSR_GPSR(IP9_19_16, VI0_DATA16),
814
815 PINMUX_IPSR_GPSR(IP9_23_20, MSIOF0_SYNC),
816 PINMUX_IPSR_GPSR(IP9_23_20, DU_DG1),
817 PINMUX_IPSR_GPSR(IP9_23_20, VI0_DATA17),
818
819 PINMUX_IPSR_GPSR(IP9_27_24, MSIOF0_SS1),
820 PINMUX_IPSR_GPSR(IP9_27_24, DU_DB0),
821 PINMUX_IPSR_GPSR(IP9_27_24, TCLK3),
822 PINMUX_IPSR_GPSR(IP9_27_24, VI0_DATA18),
823
824 PINMUX_IPSR_GPSR(IP9_31_28, MSIOF0_SS2),
825 PINMUX_IPSR_GPSR(IP9_31_28, DU_DB1),
826 PINMUX_IPSR_GPSR(IP9_31_28, TCLK4),
827 PINMUX_IPSR_GPSR(IP9_31_28, VI0_DATA19),
828
829 /* IPSR10 */
830 PINMUX_IPSR_GPSR(IP10_3_0, SCL3),
831 PINMUX_IPSR_GPSR(IP10_3_0, VI0_DATA20),
832
833 PINMUX_IPSR_GPSR(IP10_7_4, SDA3),
834 PINMUX_IPSR_GPSR(IP10_7_4, VI0_DATA21),
835
836 PINMUX_IPSR_GPSR(IP10_11_8, FSO_CFE_0_N),
837 PINMUX_IPSR_GPSR(IP10_11_8, VI0_DATA22),
838
839 PINMUX_IPSR_GPSR(IP10_15_12, FSO_CFE_1_N),
840 PINMUX_IPSR_GPSR(IP10_15_12, VI0_DATA23),
841
842 PINMUX_IPSR_GPSR(IP10_19_16, FSO_TOE_N),
843};
844
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]845/*
846 * Pins not associated with a GPIO port.
847 */
848enum {
849 GP_ASSIGN_LAST(),
850 NOGP_ALL(),
851};
852
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]853static const struct sh_pfc_pin pinmux_pins[] = {
854 PINMUX_GPIO_GP_ALL(),
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]855 PINMUX_NOGP_ALL(),
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]856};
857
858/* - AVB -------------------------------------------------------------------- */
859static const unsigned int avb_link_pins[] = {
860 /* AVB_LINK */
861 RCAR_GP_PIN(1, 18),
862};
863static const unsigned int avb_link_mux[] = {
864 AVB_LINK_MARK,
865};
866static const unsigned int avb_magic_pins[] = {
867 /* AVB_MAGIC */
868 RCAR_GP_PIN(1, 16),
869};
870static const unsigned int avb_magic_mux[] = {
871 AVB_MAGIC_MARK,
872};
873static const unsigned int avb_phy_int_pins[] = {
874 /* AVB_PHY_INT */
875 RCAR_GP_PIN(1, 17),
876};
877static const unsigned int avb_phy_int_mux[] = {
878 AVB_PHY_INT_MARK,
879};
880static const unsigned int avb_mdio_pins[] = {
881 /* AVB_MDC, AVB_MDIO */
882 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
883};
884static const unsigned int avb_mdio_mux[] = {
885 AVB_MDC_MARK, AVB_MDIO_MARK,
886};
887static const unsigned int avb_rgmii_pins[] = {
888 /*
889 * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3,
890 * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3,
891 */
892 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
893 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
894 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
895 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
896 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
897 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
898};
899static const unsigned int avb_rgmii_mux[] = {
900 AVB_TX_CTL_MARK, AVB_TXC_MARK,
901 AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
902 AVB_RX_CTL_MARK, AVB_RXC_MARK,
903 AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
904};
905static const unsigned int avb_txcrefclk_pins[] = {
906 /* AVB_TXCREFCLK */
907 RCAR_GP_PIN(1, 13),
908};
909static const unsigned int avb_txcrefclk_mux[] = {
910 AVB_TXCREFCLK_MARK,
911};
912static const unsigned int avb_avtp_pps_pins[] = {
913 /* AVB_AVTP_PPS */
914 RCAR_GP_PIN(2, 6),
915};
916static const unsigned int avb_avtp_pps_mux[] = {
917 AVB_AVTP_PPS_MARK,
918};
919static const unsigned int avb_avtp_capture_pins[] = {
920 /* AVB_AVTP_CAPTURE */
921 RCAR_GP_PIN(1, 20),
922};
923static const unsigned int avb_avtp_capture_mux[] = {
924 AVB_AVTP_CAPTURE_MARK,
925};
926static const unsigned int avb_avtp_match_pins[] = {
927 /* AVB_AVTP_MATCH */
928 RCAR_GP_PIN(1, 19),
929};
930static const unsigned int avb_avtp_match_mux[] = {
931 AVB_AVTP_MATCH_MARK,
932};
933
934/* - CANFD0 ----------------------------------------------------------------- */
935static const unsigned int canfd0_data_a_pins[] = {
936 /* CANFD0_TX, CANFD0_RX */
937 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
938};
939static const unsigned int canfd0_data_a_mux[] = {
940 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
941};
942static const unsigned int canfd0_data_b_pins[] = {
943 /* CANFD0_TX, CANFD0_RX */
944 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
945};
946static const unsigned int canfd0_data_b_mux[] = {
947 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
948};
949
950/* - CANFD1 ----------------------------------------------------------------- */
951static const unsigned int canfd1_data_pins[] = {
952 /* CANFD1_TX, CANFD1_RX */
953 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
954};
955static const unsigned int canfd1_data_mux[] = {
956 CANFD1_TX_MARK, CANFD1_RX_MARK,
957};
958
959/* - CANFD Clock ------------------------------------------------------------ */
960static const unsigned int canfd_clk_a_pins[] = {
961 /* CANFD_CLK */
962 RCAR_GP_PIN(1, 25),
963};
964static const unsigned int canfd_clk_a_mux[] = {
965 CANFD_CLK_A_MARK,
966};
967static const unsigned int canfd_clk_b_pins[] = {
968 /* CANFD_CLK */
969 RCAR_GP_PIN(3, 8),
970};
971static const unsigned int canfd_clk_b_mux[] = {
972 CANFD_CLK_B_MARK,
973};
974
975/* - DU --------------------------------------------------------------------- */
976static const unsigned int du_rgb666_pins[] = {
977 /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
978 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
979 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
980 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
981 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
982 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
983 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
984};
985static const unsigned int du_rgb666_mux[] = {
986 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
987 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
988 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
989 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
990 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
991 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
992};
993static const unsigned int du_rgb888_pins[] = {
994 /* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */
995 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
996 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
997 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19),
998 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
999 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
1000 RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1001 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
1002 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
1003 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
1004};
1005static const unsigned int du_rgb888_mux[] = {
1006 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
1007 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
1008 DU_DR1_MARK, DU_DR0_MARK,
1009 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
1010 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
1011 DU_DG1_MARK, DU_DG0_MARK,
1012 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
1013 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
1014 DU_DB1_MARK, DU_DB0_MARK,
1015};
1016static const unsigned int du_clk_out_pins[] = {
1017 /* DU_DOTCLKOUT */
1018 RCAR_GP_PIN(0, 18),
1019};
1020static const unsigned int du_clk_out_mux[] = {
1021 DU_DOTCLKOUT_MARK,
1022};
1023static const unsigned int du_sync_pins[] = {
1024 /* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */
1025 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
1026};
1027static const unsigned int du_sync_mux[] = {
1028 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
1029};
1030static const unsigned int du_oddf_pins[] = {
1031 /* DU_EXODDF/DU_ODDF/DISP/CDE */
1032 RCAR_GP_PIN(0, 21),
1033};
1034static const unsigned int du_oddf_mux[] = {
1035 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1036};
1037static const unsigned int du_cde_pins[] = {
1038 /* DU_CDE */
1039 RCAR_GP_PIN(1, 22),
1040};
1041static const unsigned int du_cde_mux[] = {
1042 DU_CDE_MARK,
1043};
1044static const unsigned int du_disp_pins[] = {
1045 /* DU_DISP */
1046 RCAR_GP_PIN(1, 21),
1047};
1048static const unsigned int du_disp_mux[] = {
1049 DU_DISP_MARK,
1050};
1051
1052/* - GETHER ----------------------------------------------------------------- */
1053static const unsigned int gether_link_a_pins[] = {
1054 /* GETHER_LINK */
1055 RCAR_GP_PIN(4, 24),
1056};
1057static const unsigned int gether_link_a_mux[] = {
1058 GETHER_LINK_A_MARK,
1059};
1060static const unsigned int gether_phy_int_a_pins[] = {
1061 /* GETHER_PHY_INT */
1062 RCAR_GP_PIN(4, 23),
1063};
1064static const unsigned int gether_phy_int_a_mux[] = {
1065 GETHER_PHY_INT_A_MARK,
1066};
1067static const unsigned int gether_mdio_a_pins[] = {
1068 /* GETHER_MDC, GETHER_MDIO */
1069 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1070};
1071static const unsigned int gether_mdio_a_mux[] = {
1072 GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK,
1073};
1074static const unsigned int gether_link_b_pins[] = {
1075 /* GETHER_LINK */
1076 RCAR_GP_PIN(0, 18),
1077};
1078static const unsigned int gether_link_b_mux[] = {
1079 GETHER_LINK_B_MARK,
1080};
1081static const unsigned int gether_phy_int_b_pins[] = {
1082 /* GETHER_PHY_INT */
1083 RCAR_GP_PIN(0, 19),
1084};
1085static const unsigned int gether_phy_int_b_mux[] = {
1086 GETHER_PHY_INT_B_MARK,
1087};
1088static const unsigned int gether_mdio_b_mux[] = {
1089 GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK,
1090};
1091static const unsigned int gether_mdio_b_pins[] = {
1092 /* GETHER_MDC, GETHER_MDIO */
1093 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1094};
1095static const unsigned int gether_magic_pins[] = {
1096 /* GETHER_MAGIC */
1097 RCAR_GP_PIN(4, 22),
1098};
1099static const unsigned int gether_magic_mux[] = {
1100 GETHER_MAGIC_MARK,
1101};
1102static const unsigned int gether_rgmii_pins[] = {
1103 /*
1104 * GETHER_TX_CTL, GETHER_TXC,
1105 * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3,
1106 * GETHER_RX_CTL, GETHER_RXC,
1107 * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3,
1108 */
1109 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1110 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1111 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1112 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1113 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1114 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1115};
1116static const unsigned int gether_rgmii_mux[] = {
1117 GETHER_TX_CTL_MARK, GETHER_TXC_MARK,
1118 GETHER_TD0_MARK, GETHER_TD1_MARK,
1119 GETHER_TD2_MARK, GETHER_TD3_MARK,
1120 GETHER_RX_CTL_MARK, GETHER_RXC_MARK,
1121 GETHER_RD0_MARK, AVB_RD1_MARK,
1122 GETHER_RD2_MARK, AVB_RD3_MARK,
1123};
1124static const unsigned int gether_txcrefclk_pins[] = {
1125 /* GETHER_TXCREFCLK */
1126 RCAR_GP_PIN(4, 18),
1127};
1128static const unsigned int gether_txcrefclk_mux[] = {
1129 GETHER_TXCREFCLK_MARK,
1130};
1131static const unsigned int gether_txcrefclk_mega_pins[] = {
1132 /* GETHER_TXCREFCLK_MEGA */
1133 RCAR_GP_PIN(4, 19),
1134};
1135static const unsigned int gether_txcrefclk_mega_mux[] = {
1136 GETHER_TXCREFCLK_MEGA_MARK,
1137};
1138static const unsigned int gether_rmii_pins[] = {
1139 /*
1140 * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER,
1141 * GETHER_RMII_RXD0, GETHER_RMII_RXD1,
1142 * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0,
1143 * GETHER_RMII_TXD1, GETHER_RMII_REFCLK
1144 */
1145 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
1146 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
1147 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1148 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
1149};
1150static const unsigned int gether_rmii_mux[] = {
1151 GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK,
1152 GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK,
1153 GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK,
1154 GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK,
1155};
1156
1157/* - HSCIF0 ----------------------------------------------------------------- */
1158static const unsigned int hscif0_data_a_pins[] = {
1159 /* HRX0, HTX0 */
1160 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15),
1161};
1162static const unsigned int hscif0_data_a_mux[] = {
1163 HRX0_A_MARK, HTX0_A_MARK,
1164};
1165static const unsigned int hscif0_clk_a_pins[] = {
1166 /* HSCK0 */
1167 RCAR_GP_PIN(0, 12),
1168};
1169static const unsigned int hscif0_clk_a_mux[] = {
1170 HSCK0_A_MARK,
1171};
1172static const unsigned int hscif0_ctrl_a_pins[] = {
1173 /* HRTS0#, HCTS0# */
1174 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1175};
1176static const unsigned int hscif0_ctrl_a_mux[] = {
1177 HRTS0_N_A_MARK, HCTS0_N_A_MARK,
1178};
1179static const unsigned int hscif0_data_b_pins[] = {
1180 /* HRX0, HTX0 */
1181 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1182};
1183static const unsigned int hscif0_data_b_mux[] = {
1184 HRX0_B_MARK, HTX0_B_MARK,
1185};
1186static const unsigned int hscif0_clk_b_pins[] = {
1187 /* HSCK0 */
1188 RCAR_GP_PIN(4, 1),
1189};
1190static const unsigned int hscif0_clk_b_mux[] = {
1191 HSCK0_B_MARK,
1192};
1193static const unsigned int hscif0_ctrl_b_pins[] = {
1194 /* HRTS0#, HCTS0# */
1195 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1196};
1197static const unsigned int hscif0_ctrl_b_mux[] = {
1198 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
1199};
1200
1201/* - HSCIF1 ----------------------------------------------------------------- */
1202static const unsigned int hscif1_data_pins[] = {
1203 /* HRX1, HTX1 */
1204 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1205};
1206static const unsigned int hscif1_data_mux[] = {
1207 HRX1_MARK, HTX1_MARK,
1208};
1209static const unsigned int hscif1_clk_pins[] = {
1210 /* HSCK1 */
1211 RCAR_GP_PIN(2, 7),
1212};
1213static const unsigned int hscif1_clk_mux[] = {
1214 HSCK1_MARK,
1215};
1216static const unsigned int hscif1_ctrl_pins[] = {
1217 /* HRTS1#, HCTS1# */
1218 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1219};
1220static const unsigned int hscif1_ctrl_mux[] = {
1221 HRTS1_N_MARK, HCTS1_N_MARK,
1222};
1223
1224/* - HSCIF2 ----------------------------------------------------------------- */
1225static const unsigned int hscif2_data_pins[] = {
1226 /* HRX2, HTX2 */
1227 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
1228};
1229static const unsigned int hscif2_data_mux[] = {
1230 HRX2_MARK, HTX2_MARK,
1231};
1232static const unsigned int hscif2_clk_pins[] = {
1233 /* HSCK2 */
1234 RCAR_GP_PIN(2, 12),
1235};
1236static const unsigned int hscif2_clk_mux[] = {
1237 HSCK2_MARK,
1238};
1239static const unsigned int hscif2_ctrl_pins[] = {
1240 /* HRTS2#, HCTS2# */
1241 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1242};
1243static const unsigned int hscif2_ctrl_mux[] = {
1244 HRTS2_N_MARK, HCTS2_N_MARK,
1245};
1246
1247/* - HSCIF3 ----------------------------------------------------------------- */
1248static const unsigned int hscif3_data_pins[] = {
1249 /* HRX3, HTX3 */
1250 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1251};
1252static const unsigned int hscif3_data_mux[] = {
1253 HRX3_MARK, HTX3_MARK,
1254};
1255static const unsigned int hscif3_clk_pins[] = {
1256 /* HSCK3 */
1257 RCAR_GP_PIN(2, 0),
1258};
1259static const unsigned int hscif3_clk_mux[] = {
1260 HSCK3_MARK,
1261};
1262static const unsigned int hscif3_ctrl_pins[] = {
1263 /* HRTS3#, HCTS3# */
1264 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
1265};
1266static const unsigned int hscif3_ctrl_mux[] = {
1267 HRTS3_N_MARK, HCTS3_N_MARK,
1268};
1269
1270/* - I2C0 ------------------------------------------------------------------- */
1271static const unsigned int i2c0_pins[] = {
1272 /* SDA0, SCL0 */
1273 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1274};
1275static const unsigned int i2c0_mux[] = {
1276 SDA0_MARK, SCL0_MARK,
1277};
1278
1279/* - I2C1 ------------------------------------------------------------------- */
1280static const unsigned int i2c1_pins[] = {
1281 /* SDA1, SCL1 */
1282 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1283};
1284static const unsigned int i2c1_mux[] = {
1285 SDA1_MARK, SCL1_MARK,
1286};
1287
1288/* - I2C2 ------------------------------------------------------------------- */
1289static const unsigned int i2c2_pins[] = {
1290 /* SDA2, SCL2 */
1291 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1292};
1293static const unsigned int i2c2_mux[] = {
1294 SDA2_MARK, SCL2_MARK,
1295};
1296
1297/* - I2C3 ------------------------------------------------------------------- */
1298static const unsigned int i2c3_pins[] = {
1299 /* SDA3, SCL3 */
1300 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
1301};
1302static const unsigned int i2c3_mux[] = {
1303 SDA3_MARK, SCL3_MARK,
1304};
1305
1306/* - I2C4 ------------------------------------------------------------------- */
1307static const unsigned int i2c4_pins[] = {
1308 /* SDA4, SCL4 */
1309 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1310};
1311static const unsigned int i2c4_mux[] = {
1312 SDA4_MARK, SCL4_MARK,
1313};
1314
1315/* - I2C5 ------------------------------------------------------------------- */
1316static const unsigned int i2c5_pins[] = {
1317 /* SDA5, SCL5 */
1318 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1319};
1320static const unsigned int i2c5_mux[] = {
1321 SDA5_MARK, SCL5_MARK,
1322};
1323
1324/* - INTC-EX ---------------------------------------------------------------- */
1325static const unsigned int intc_ex_irq0_pins[] = {
1326 /* IRQ0 */
1327 RCAR_GP_PIN(1, 0),
1328};
1329static const unsigned int intc_ex_irq0_mux[] = {
1330 IRQ0_MARK,
1331};
1332static const unsigned int intc_ex_irq1_pins[] = {
1333 /* IRQ1 */
1334 RCAR_GP_PIN(0, 12),
1335};
1336static const unsigned int intc_ex_irq1_mux[] = {
1337 IRQ1_MARK,
1338};
1339static const unsigned int intc_ex_irq2_pins[] = {
1340 /* IRQ2 */
1341 RCAR_GP_PIN(0, 13),
1342};
1343static const unsigned int intc_ex_irq2_mux[] = {
1344 IRQ2_MARK,
1345};
1346static const unsigned int intc_ex_irq3_pins[] = {
1347 /* IRQ3 */
1348 RCAR_GP_PIN(0, 14),
1349};
1350static const unsigned int intc_ex_irq3_mux[] = {
1351 IRQ3_MARK,
1352};
1353static const unsigned int intc_ex_irq4_pins[] = {
1354 /* IRQ4 */
1355 RCAR_GP_PIN(2, 17),
1356};
1357static const unsigned int intc_ex_irq4_mux[] = {
1358 IRQ4_MARK,
1359};
1360static const unsigned int intc_ex_irq5_pins[] = {
1361 /* IRQ5 */
1362 RCAR_GP_PIN(2, 18),
1363};
1364static const unsigned int intc_ex_irq5_mux[] = {
1365 IRQ5_MARK,
1366};
1367
1368/* - MMC -------------------------------------------------------------------- */
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]1369static const unsigned int mmc_data_pins[] = {
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]1370 /* MMC_D[0:7] */
1371 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1372 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1373 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1374 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1375};
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]1376static const unsigned int mmc_data_mux[] = {
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]1377 MMC_D0_MARK, MMC_D1_MARK,
1378 MMC_D2_MARK, MMC_D3_MARK,
1379 MMC_D4_MARK, MMC_D5_MARK,
1380 MMC_D6_MARK, MMC_D7_MARK,
1381};
1382static const unsigned int mmc_ctrl_pins[] = {
1383 /* MMC_CLK, MMC_CMD */
1384 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7),
1385};
1386static const unsigned int mmc_ctrl_mux[] = {
1387 MMC_CLK_MARK, MMC_CMD_MARK,
1388};
1389static const unsigned int mmc_cd_pins[] = {
1390 /* MMC_CD */
1391 RCAR_GP_PIN(3, 5),
1392};
1393static const unsigned int mmc_cd_mux[] = {
1394 MMC_CD_MARK,
1395};
1396static const unsigned int mmc_wp_pins[] = {
1397 /* MMC_WP */
1398 RCAR_GP_PIN(3, 4),
1399};
1400static const unsigned int mmc_wp_mux[] = {
1401 MMC_WP_MARK,
1402};
1403static const unsigned int mmc_ds_pins[] = {
1404 /* MMC_DS */
1405 RCAR_GP_PIN(3, 6),
1406};
1407static const unsigned int mmc_ds_mux[] = {
1408 MMC_DS_MARK,
1409};
1410
1411/* - MSIOF0 ----------------------------------------------------------------- */
1412static const unsigned int msiof0_clk_pins[] = {
1413 /* MSIOF0_SCK */
1414 RCAR_GP_PIN(2, 21),
1415};
1416static const unsigned int msiof0_clk_mux[] = {
1417 MSIOF0_SCK_MARK,
1418};
1419static const unsigned int msiof0_sync_pins[] = {
1420 /* MSIOF0_SYNC */
1421 RCAR_GP_PIN(2, 22),
1422};
1423static const unsigned int msiof0_sync_mux[] = {
1424 MSIOF0_SYNC_MARK,
1425};
1426static const unsigned int msiof0_ss1_pins[] = {
1427 /* MSIOF0_SS1 */
1428 RCAR_GP_PIN(2, 23),
1429};
1430static const unsigned int msiof0_ss1_mux[] = {
1431 MSIOF0_SS1_MARK,
1432};
1433static const unsigned int msiof0_ss2_pins[] = {
1434 /* MSIOF0_SS2 */
1435 RCAR_GP_PIN(2, 24),
1436};
1437static const unsigned int msiof0_ss2_mux[] = {
1438 MSIOF0_SS2_MARK,
1439};
1440static const unsigned int msiof0_txd_pins[] = {
1441 /* MSIOF0_TXD */
1442 RCAR_GP_PIN(2, 20),
1443};
1444static const unsigned int msiof0_txd_mux[] = {
1445 MSIOF0_TXD_MARK,
1446};
1447static const unsigned int msiof0_rxd_pins[] = {
1448 /* MSIOF0_RXD */
1449 RCAR_GP_PIN(2, 19),
1450};
1451static const unsigned int msiof0_rxd_mux[] = {
1452 MSIOF0_RXD_MARK,
1453};
1454
1455/* - MSIOF1 ----------------------------------------------------------------- */
1456static const unsigned int msiof1_clk_pins[] = {
1457 /* MSIOF1_SCK */
1458 RCAR_GP_PIN(3, 2),
1459};
1460static const unsigned int msiof1_clk_mux[] = {
1461 MSIOF1_SCK_MARK,
1462};
1463static const unsigned int msiof1_sync_pins[] = {
1464 /* MSIOF1_SYNC */
1465 RCAR_GP_PIN(3, 3),
1466};
1467static const unsigned int msiof1_sync_mux[] = {
1468 MSIOF1_SYNC_MARK,
1469};
1470static const unsigned int msiof1_ss1_pins[] = {
1471 /* MSIOF1_SS1 */
1472 RCAR_GP_PIN(3, 4),
1473};
1474static const unsigned int msiof1_ss1_mux[] = {
1475 MSIOF1_SS1_MARK,
1476};
1477static const unsigned int msiof1_ss2_pins[] = {
1478 /* MSIOF1_SS2 */
1479 RCAR_GP_PIN(3, 5),
1480};
1481static const unsigned int msiof1_ss2_mux[] = {
1482 MSIOF1_SS2_MARK,
1483};
1484static const unsigned int msiof1_txd_pins[] = {
1485 /* MSIOF1_TXD */
1486 RCAR_GP_PIN(3, 1),
1487};
1488static const unsigned int msiof1_txd_mux[] = {
1489 MSIOF1_TXD_MARK,
1490};
1491static const unsigned int msiof1_rxd_pins[] = {
1492 /* MSIOF1_RXD */
1493 RCAR_GP_PIN(3, 0),
1494};
1495static const unsigned int msiof1_rxd_mux[] = {
1496 MSIOF1_RXD_MARK,
1497};
1498
1499/* - MSIOF2 ----------------------------------------------------------------- */
1500static const unsigned int msiof2_clk_pins[] = {
1501 /* MSIOF2_SCK */
1502 RCAR_GP_PIN(2, 0),
1503};
1504static const unsigned int msiof2_clk_mux[] = {
1505 MSIOF2_SCK_MARK,
1506};
1507static const unsigned int msiof2_sync_pins[] = {
1508 /* MSIOF2_SYNC */
1509 RCAR_GP_PIN(2, 3),
1510};
1511static const unsigned int msiof2_sync_mux[] = {
1512 MSIOF2_SYNC_MARK,
1513};
1514static const unsigned int msiof2_ss1_pins[] = {
1515 /* MSIOF2_SS1 */
1516 RCAR_GP_PIN(2, 4),
1517};
1518static const unsigned int msiof2_ss1_mux[] = {
1519 MSIOF2_SS1_MARK,
1520};
1521static const unsigned int msiof2_ss2_pins[] = {
1522 /* MSIOF2_SS2 */
1523 RCAR_GP_PIN(2, 5),
1524};
1525static const unsigned int msiof2_ss2_mux[] = {
1526 MSIOF2_SS2_MARK,
1527};
1528static const unsigned int msiof2_txd_pins[] = {
1529 /* MSIOF2_TXD */
1530 RCAR_GP_PIN(2, 2),
1531};
1532static const unsigned int msiof2_txd_mux[] = {
1533 MSIOF2_TXD_MARK,
1534};
1535static const unsigned int msiof2_rxd_pins[] = {
1536 /* MSIOF2_RXD */
1537 RCAR_GP_PIN(2, 1),
1538};
1539static const unsigned int msiof2_rxd_mux[] = {
1540 MSIOF2_RXD_MARK,
1541};
1542
1543/* - MSIOF3 ----------------------------------------------------------------- */
1544static const unsigned int msiof3_clk_pins[] = {
1545 /* MSIOF3_SCK */
1546 RCAR_GP_PIN(0, 20),
1547};
1548static const unsigned int msiof3_clk_mux[] = {
1549 MSIOF3_SCK_MARK,
1550};
1551static const unsigned int msiof3_sync_pins[] = {
1552 /* MSIOF3_SYNC */
1553 RCAR_GP_PIN(0, 21),
1554};
1555static const unsigned int msiof3_sync_mux[] = {
1556 MSIOF3_SYNC_MARK,
1557};
1558static const unsigned int msiof3_ss1_pins[] = {
1559 /* MSIOF3_SS1 */
1560 RCAR_GP_PIN(0, 18),
1561};
1562static const unsigned int msiof3_ss1_mux[] = {
1563 MSIOF3_SS1_MARK,
1564};
1565static const unsigned int msiof3_ss2_pins[] = {
1566 /* MSIOF3_SS2 */
1567 RCAR_GP_PIN(0, 19),
1568};
1569static const unsigned int msiof3_ss2_mux[] = {
1570 MSIOF3_SS2_MARK,
1571};
1572static const unsigned int msiof3_txd_pins[] = {
1573 /* MSIOF3_TXD */
1574 RCAR_GP_PIN(0, 17),
1575};
1576static const unsigned int msiof3_txd_mux[] = {
1577 MSIOF3_TXD_MARK,
1578};
1579static const unsigned int msiof3_rxd_pins[] = {
1580 /* MSIOF3_RXD */
1581 RCAR_GP_PIN(0, 16),
1582};
1583static const unsigned int msiof3_rxd_mux[] = {
1584 MSIOF3_RXD_MARK,
1585};
1586
1587/* - PWM0 ------------------------------------------------------------------- */
1588static const unsigned int pwm0_a_pins[] = {
1589 /* PWM0 */
1590 RCAR_GP_PIN(0, 15),
1591};
1592static const unsigned int pwm0_a_mux[] = {
1593 PWM0_A_MARK,
1594};
1595static const unsigned int pwm0_b_pins[] = {
1596 /* PWM0 */
1597 RCAR_GP_PIN(1, 21),
1598};
1599static const unsigned int pwm0_b_mux[] = {
1600 PWM0_B_MARK,
1601};
1602
1603/* - PWM1 ------------------------------------------------------------------- */
1604static const unsigned int pwm1_a_pins[] = {
1605 /* PWM1 */
1606 RCAR_GP_PIN(2, 13),
1607};
1608static const unsigned int pwm1_a_mux[] = {
1609 PWM1_A_MARK,
1610};
1611static const unsigned int pwm1_b_pins[] = {
1612 /* PWM1 */
1613 RCAR_GP_PIN(1, 22),
1614};
1615static const unsigned int pwm1_b_mux[] = {
1616 PWM1_B_MARK,
1617};
1618
1619/* - PWM2 ------------------------------------------------------------------- */
1620static const unsigned int pwm2_a_pins[] = {
1621 /* PWM2 */
1622 RCAR_GP_PIN(2, 14),
1623};
1624static const unsigned int pwm2_a_mux[] = {
1625 PWM2_A_MARK,
1626};
1627static const unsigned int pwm2_b_pins[] = {
1628 /* PWM2 */
1629 RCAR_GP_PIN(1, 23),
1630};
1631static const unsigned int pwm2_b_mux[] = {
1632 PWM2_B_MARK,
1633};
1634
1635/* - PWM3 ------------------------------------------------------------------- */
1636static const unsigned int pwm3_a_pins[] = {
1637 /* PWM3 */
1638 RCAR_GP_PIN(2, 15),
1639};
1640static const unsigned int pwm3_a_mux[] = {
1641 PWM3_A_MARK,
1642};
1643static const unsigned int pwm3_b_pins[] = {
1644 /* PWM3 */
1645 RCAR_GP_PIN(1, 24),
1646};
1647static const unsigned int pwm3_b_mux[] = {
1648 PWM3_B_MARK,
1649};
1650
1651/* - PWM4 ------------------------------------------------------------------- */
1652static const unsigned int pwm4_a_pins[] = {
1653 /* PWM4 */
1654 RCAR_GP_PIN(2, 16),
1655};
1656static const unsigned int pwm4_a_mux[] = {
1657 PWM4_A_MARK,
1658};
1659static const unsigned int pwm4_b_pins[] = {
1660 /* PWM4 */
1661 RCAR_GP_PIN(1, 25),
1662};
1663static const unsigned int pwm4_b_mux[] = {
1664 PWM4_B_MARK,
1665};
1666
1667/* - QSPI0 ------------------------------------------------------------------ */
1668static const unsigned int qspi0_ctrl_pins[] = {
1669 /* SPCLK, SSL */
1670 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
1671};
1672static const unsigned int qspi0_ctrl_mux[] = {
1673 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1674};
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]1675
1676/* - QSPI1 ------------------------------------------------------------------ */
1677static const unsigned int qspi1_ctrl_pins[] = {
1678 /* SPCLK, SSL */
1679 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
1680};
1681static const unsigned int qspi1_ctrl_mux[] = {
1682 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1683};
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]1684
Marek Vasuta2a14852021-04-26 22:04:11 +0200[diff] [blame]1685/* - RPC -------------------------------------------------------------------- */
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]1686static const unsigned int rpc_clk_pins[] = {
Marek Vasuta2a14852021-04-26 22:04:11 +0200[diff] [blame]1687 /* Octal-SPI flash: C/SCLK */
Marek Vasuta2a14852021-04-26 22:04:11 +0200[diff] [blame]1688 /* HyperFlash: CK, CK# */
1689 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
1690};
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]1691static const unsigned int rpc_clk_mux[] = {
Marek Vasuta2a14852021-04-26 22:04:11 +0200[diff] [blame]1692 QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
1693};
1694static const unsigned int rpc_ctrl_pins[] = {
1695 /* Octal-SPI flash: S#/CS, DQS */
1696 /* HyperFlash: CS#, RDS */
1697 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1698};
1699static const unsigned int rpc_ctrl_mux[] = {
1700 QSPI0_SSL_MARK, QSPI1_SSL_MARK,
1701};
1702static const unsigned int rpc_data_pins[] = {
1703 /* DQ[0:7] */
1704 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1705 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1706 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1707 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1708};
1709static const unsigned int rpc_data_mux[] = {
1710 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1711 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
1712 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1713 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
1714};
1715static const unsigned int rpc_reset_pins[] = {
1716 /* RPC_RESET# */
1717 RCAR_GP_PIN(5, 12),
1718};
1719static const unsigned int rpc_reset_mux[] = {
1720 RPC_RESET_N_MARK,
1721};
1722static const unsigned int rpc_int_pins[] = {
1723 /* RPC_INT# */
1724 RCAR_GP_PIN(5, 14),
1725};
1726static const unsigned int rpc_int_mux[] = {
1727 RPC_INT_N_MARK,
1728};
1729static const unsigned int rpc_wp_pins[] = {
1730 /* RPC_WP# */
1731 RCAR_GP_PIN(5, 13),
1732};
1733static const unsigned int rpc_wp_mux[] = {
1734 RPC_WP_N_MARK,
1735};
1736
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]1737/* - SCIF0 ------------------------------------------------------------------ */
1738static const unsigned int scif0_data_pins[] = {
1739 /* RX0, TX0 */
1740 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1741};
1742static const unsigned int scif0_data_mux[] = {
1743 RX0_MARK, TX0_MARK,
1744};
1745static const unsigned int scif0_clk_pins[] = {
1746 /* SCK0 */
1747 RCAR_GP_PIN(4, 1),
1748};
1749static const unsigned int scif0_clk_mux[] = {
1750 SCK0_MARK,
1751};
1752static const unsigned int scif0_ctrl_pins[] = {
1753 /* RTS0#, CTS0# */
1754 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1755};
1756static const unsigned int scif0_ctrl_mux[] = {
1757 RTS0_N_MARK, CTS0_N_MARK,
1758};
1759
1760/* - SCIF1 ------------------------------------------------------------------ */
1761static const unsigned int scif1_data_a_pins[] = {
1762 /* RX1, TX1 */
1763 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1764};
1765static const unsigned int scif1_data_a_mux[] = {
1766 RX1_A_MARK, TX1_A_MARK,
1767};
1768static const unsigned int scif1_clk_pins[] = {
1769 /* SCK1 */
1770 RCAR_GP_PIN(2, 5),
1771};
1772static const unsigned int scif1_clk_mux[] = {
1773 SCK1_MARK,
1774};
1775static const unsigned int scif1_ctrl_pins[] = {
1776 /* RTS1#, CTS1# */
1777 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1778};
1779static const unsigned int scif1_ctrl_mux[] = {
1780 RTS1_N_MARK, CTS1_N_MARK,
1781};
1782static const unsigned int scif1_data_b_pins[] = {
1783 /* RX1, TX1 */
1784 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1785};
1786static const unsigned int scif1_data_b_mux[] = {
1787 RX1_B_MARK, TX1_B_MARK,
1788};
1789
1790/* - SCIF3 ------------------------------------------------------------------ */
1791static const unsigned int scif3_data_pins[] = {
1792 /* RX3, TX3 */
1793 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1794};
1795static const unsigned int scif3_data_mux[] = {
1796 RX3_MARK, TX3_MARK,
1797};
1798static const unsigned int scif3_clk_pins[] = {
1799 /* SCK3 */
1800 RCAR_GP_PIN(2, 0),
1801};
1802static const unsigned int scif3_clk_mux[] = {
1803 SCK3_MARK,
1804};
1805static const unsigned int scif3_ctrl_pins[] = {
1806 /* RTS3#, CTS3# */
1807 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1808};
1809static const unsigned int scif3_ctrl_mux[] = {
1810 RTS3_N_MARK, CTS3_N_MARK,
1811};
1812
1813/* - SCIF4 ------------------------------------------------------------------ */
1814static const unsigned int scif4_data_pins[] = {
1815 /* RX4, TX4 */
1816 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
1817};
1818static const unsigned int scif4_data_mux[] = {
1819 RX4_MARK, TX4_MARK,
1820};
1821static const unsigned int scif4_clk_pins[] = {
1822 /* SCK4 */
1823 RCAR_GP_PIN(0, 0),
1824};
1825static const unsigned int scif4_clk_mux[] = {
1826 SCK4_MARK,
1827};
1828static const unsigned int scif4_ctrl_pins[] = {
1829 /* RTS4#, CTS4# */
1830 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
1831};
1832static const unsigned int scif4_ctrl_mux[] = {
1833 RTS4_N_MARK, CTS4_N_MARK,
1834};
1835
1836/* - SCIF Clock ------------------------------------------------------------- */
1837static const unsigned int scif_clk_a_pins[] = {
1838 /* SCIF_CLK */
1839 RCAR_GP_PIN(0, 10),
1840};
1841static const unsigned int scif_clk_a_mux[] = {
1842 SCIF_CLK_A_MARK,
1843};
1844static const unsigned int scif_clk_b_pins[] = {
1845 /* SCIF_CLK */
1846 RCAR_GP_PIN(1, 25),
1847};
1848static const unsigned int scif_clk_b_mux[] = {
1849 SCIF_CLK_B_MARK,
1850};
1851
1852/* - TMU -------------------------------------------------------------------- */
1853static const unsigned int tmu_tclk1_a_pins[] = {
1854 /* TCLK1 */
1855 RCAR_GP_PIN(3, 13),
1856};
1857static const unsigned int tmu_tclk1_a_mux[] = {
1858 TCLK1_A_MARK,
1859};
1860static const unsigned int tmu_tclk1_b_pins[] = {
1861 /* TCLK1 */
1862 RCAR_GP_PIN(1, 23),
1863};
1864static const unsigned int tmu_tclk1_b_mux[] = {
1865 TCLK1_B_MARK,
1866};
1867static const unsigned int tmu_tclk2_a_pins[] = {
1868 /* TCLK2 */
1869 RCAR_GP_PIN(3, 14),
1870};
1871static const unsigned int tmu_tclk2_a_mux[] = {
1872 TCLK2_A_MARK,
1873};
1874static const unsigned int tmu_tclk2_b_pins[] = {
1875 /* TCLK2 */
1876 RCAR_GP_PIN(1, 24),
1877};
1878static const unsigned int tmu_tclk2_b_mux[] = {
1879 TCLK2_B_MARK,
1880};
1881
1882/* - TPU ------------------------------------------------------------------- */
1883static const unsigned int tpu_to0_pins[] = {
1884 /* TPU0TO0 */
1885 RCAR_GP_PIN(1, 19),
1886};
1887static const unsigned int tpu_to0_mux[] = {
1888 TPU0TO0_MARK,
1889};
1890static const unsigned int tpu_to1_pins[] = {
1891 /* TPU0TO1 */
1892 RCAR_GP_PIN(1, 20),
1893};
1894static const unsigned int tpu_to1_mux[] = {
1895 TPU0TO1_MARK,
1896};
1897static const unsigned int tpu_to2_pins[] = {
1898 /* TPU0TO2 */
1899 RCAR_GP_PIN(4, 2),
1900};
1901static const unsigned int tpu_to2_mux[] = {
1902 TPU0TO2_MARK,
1903};
1904static const unsigned int tpu_to3_pins[] = {
1905 /* TPU0TO3 */
1906 RCAR_GP_PIN(4, 3),
1907};
1908static const unsigned int tpu_to3_mux[] = {
1909 TPU0TO3_MARK,
1910};
1911
1912/* - VIN0 ------------------------------------------------------------------- */
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]1913static const unsigned int vin0_data_pins[] = {
1914 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1915 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1916 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1917 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1918 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1919 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1920 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1921 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1922 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1923 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1924 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
1925 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]1926};
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]1927static const unsigned int vin0_data_mux[] = {
1928 VI0_DATA0_MARK, VI0_DATA1_MARK,
1929 VI0_DATA2_MARK, VI0_DATA3_MARK,
1930 VI0_DATA4_MARK, VI0_DATA5_MARK,
1931 VI0_DATA6_MARK, VI0_DATA7_MARK,
1932 VI0_DATA8_MARK, VI0_DATA9_MARK,
1933 VI0_DATA10_MARK, VI0_DATA11_MARK,
1934 VI0_DATA12_MARK, VI0_DATA13_MARK,
1935 VI0_DATA14_MARK, VI0_DATA15_MARK,
1936 VI0_DATA16_MARK, VI0_DATA17_MARK,
1937 VI0_DATA18_MARK, VI0_DATA19_MARK,
1938 VI0_DATA20_MARK, VI0_DATA21_MARK,
1939 VI0_DATA22_MARK, VI0_DATA23_MARK,
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]1940};
1941static const unsigned int vin0_data18_pins[] = {
1942 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1943 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1944 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1945 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1946 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1947 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1948 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1949 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
1950 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
1951};
1952static const unsigned int vin0_data18_mux[] = {
1953 VI0_DATA2_MARK, VI0_DATA3_MARK,
1954 VI0_DATA4_MARK, VI0_DATA5_MARK,
1955 VI0_DATA6_MARK, VI0_DATA7_MARK,
1956 VI0_DATA10_MARK, VI0_DATA11_MARK,
1957 VI0_DATA12_MARK, VI0_DATA13_MARK,
1958 VI0_DATA14_MARK, VI0_DATA15_MARK,
1959 VI0_DATA18_MARK, VI0_DATA19_MARK,
1960 VI0_DATA20_MARK, VI0_DATA21_MARK,
1961 VI0_DATA22_MARK, VI0_DATA23_MARK,
1962};
1963static const unsigned int vin0_sync_pins[] = {
1964 /* VI0_VSYNC#, VI0_HSYNC# */
1965 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1966};
1967static const unsigned int vin0_sync_mux[] = {
1968 VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK,
1969};
1970static const unsigned int vin0_field_pins[] = {
1971 /* VI0_FIELD */
1972 RCAR_GP_PIN(2, 16),
1973};
1974static const unsigned int vin0_field_mux[] = {
1975 VI0_FIELD_MARK,
1976};
1977static const unsigned int vin0_clkenb_pins[] = {
1978 /* VI0_CLKENB */
1979 RCAR_GP_PIN(2, 1),
1980};
1981static const unsigned int vin0_clkenb_mux[] = {
1982 VI0_CLKENB_MARK,
1983};
1984static const unsigned int vin0_clk_pins[] = {
1985 /* VI0_CLK */
1986 RCAR_GP_PIN(2, 0),
1987};
1988static const unsigned int vin0_clk_mux[] = {
1989 VI0_CLK_MARK,
1990};
1991
1992/* - VIN1 ------------------------------------------------------------------- */
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]1993static const unsigned int vin1_data_pins[] = {
1994 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1995 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1996 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1997 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1998 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1999 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2000};
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]2001static const unsigned int vin1_data_mux[] = {
2002 VI1_DATA0_MARK, VI1_DATA1_MARK,
2003 VI1_DATA2_MARK, VI1_DATA3_MARK,
2004 VI1_DATA4_MARK, VI1_DATA5_MARK,
2005 VI1_DATA6_MARK, VI1_DATA7_MARK,
2006 VI1_DATA8_MARK, VI1_DATA9_MARK,
2007 VI1_DATA10_MARK, VI1_DATA11_MARK,
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2008};
2009static const unsigned int vin1_sync_pins[] = {
2010 /* VI1_VSYNC#, VI1_HSYNC# */
2011 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
2012};
2013static const unsigned int vin1_sync_mux[] = {
2014 VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK,
2015};
2016static const unsigned int vin1_field_pins[] = {
2017 /* VI1_FIELD */
2018 RCAR_GP_PIN(3, 16),
2019};
2020static const unsigned int vin1_field_mux[] = {
2021 VI1_FIELD_MARK,
2022};
2023static const unsigned int vin1_clkenb_pins[] = {
2024 /* VI1_CLKENB */
2025 RCAR_GP_PIN(3, 1),
2026};
2027static const unsigned int vin1_clkenb_mux[] = {
2028 VI1_CLKENB_MARK,
2029};
2030static const unsigned int vin1_clk_pins[] = {
2031 /* VI1_CLK */
2032 RCAR_GP_PIN(3, 0),
2033};
2034static const unsigned int vin1_clk_mux[] = {
2035 VI1_CLK_MARK,
2036};
2037
2038static const struct sh_pfc_pin_group pinmux_groups[] = {
2039 SH_PFC_PIN_GROUP(avb_link),
2040 SH_PFC_PIN_GROUP(avb_magic),
2041 SH_PFC_PIN_GROUP(avb_phy_int),
2042 SH_PFC_PIN_GROUP(avb_mdio),
2043 SH_PFC_PIN_GROUP(avb_rgmii),
2044 SH_PFC_PIN_GROUP(avb_txcrefclk),
2045 SH_PFC_PIN_GROUP(avb_avtp_pps),
2046 SH_PFC_PIN_GROUP(avb_avtp_capture),
2047 SH_PFC_PIN_GROUP(avb_avtp_match),
2048 SH_PFC_PIN_GROUP(canfd0_data_a),
2049 SH_PFC_PIN_GROUP(canfd0_data_b),
2050 SH_PFC_PIN_GROUP(canfd1_data),
2051 SH_PFC_PIN_GROUP(canfd_clk_a),
2052 SH_PFC_PIN_GROUP(canfd_clk_b),
2053 SH_PFC_PIN_GROUP(du_rgb666),
2054 SH_PFC_PIN_GROUP(du_rgb888),
2055 SH_PFC_PIN_GROUP(du_clk_out),
2056 SH_PFC_PIN_GROUP(du_sync),
2057 SH_PFC_PIN_GROUP(du_oddf),
2058 SH_PFC_PIN_GROUP(du_cde),
2059 SH_PFC_PIN_GROUP(du_disp),
2060 SH_PFC_PIN_GROUP(gether_link_a),
2061 SH_PFC_PIN_GROUP(gether_phy_int_a),
2062 SH_PFC_PIN_GROUP(gether_mdio_a),
2063 SH_PFC_PIN_GROUP(gether_link_b),
2064 SH_PFC_PIN_GROUP(gether_phy_int_b),
2065 SH_PFC_PIN_GROUP(gether_mdio_b),
2066 SH_PFC_PIN_GROUP(gether_magic),
2067 SH_PFC_PIN_GROUP(gether_rgmii),
2068 SH_PFC_PIN_GROUP(gether_txcrefclk),
2069 SH_PFC_PIN_GROUP(gether_txcrefclk_mega),
2070 SH_PFC_PIN_GROUP(gether_rmii),
2071 SH_PFC_PIN_GROUP(hscif0_data_a),
2072 SH_PFC_PIN_GROUP(hscif0_clk_a),
2073 SH_PFC_PIN_GROUP(hscif0_ctrl_a),
2074 SH_PFC_PIN_GROUP(hscif0_data_b),
2075 SH_PFC_PIN_GROUP(hscif0_clk_b),
2076 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
2077 SH_PFC_PIN_GROUP(hscif1_data),
2078 SH_PFC_PIN_GROUP(hscif1_clk),
2079 SH_PFC_PIN_GROUP(hscif1_ctrl),
2080 SH_PFC_PIN_GROUP(hscif2_data),
2081 SH_PFC_PIN_GROUP(hscif2_clk),
2082 SH_PFC_PIN_GROUP(hscif2_ctrl),
2083 SH_PFC_PIN_GROUP(hscif3_data),
2084 SH_PFC_PIN_GROUP(hscif3_clk),
2085 SH_PFC_PIN_GROUP(hscif3_ctrl),
2086 SH_PFC_PIN_GROUP(i2c0),
2087 SH_PFC_PIN_GROUP(i2c1),
2088 SH_PFC_PIN_GROUP(i2c2),
2089 SH_PFC_PIN_GROUP(i2c3),
2090 SH_PFC_PIN_GROUP(i2c4),
2091 SH_PFC_PIN_GROUP(i2c5),
2092 SH_PFC_PIN_GROUP(intc_ex_irq0),
2093 SH_PFC_PIN_GROUP(intc_ex_irq1),
2094 SH_PFC_PIN_GROUP(intc_ex_irq2),
2095 SH_PFC_PIN_GROUP(intc_ex_irq3),
2096 SH_PFC_PIN_GROUP(intc_ex_irq4),
2097 SH_PFC_PIN_GROUP(intc_ex_irq5),
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]2098 BUS_DATA_PIN_GROUP(mmc_data, 1),
2099 BUS_DATA_PIN_GROUP(mmc_data, 4),
2100 BUS_DATA_PIN_GROUP(mmc_data, 8),
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2101 SH_PFC_PIN_GROUP(mmc_ctrl),
2102 SH_PFC_PIN_GROUP(mmc_cd),
2103 SH_PFC_PIN_GROUP(mmc_wp),
2104 SH_PFC_PIN_GROUP(mmc_ds),
2105 SH_PFC_PIN_GROUP(msiof0_clk),
2106 SH_PFC_PIN_GROUP(msiof0_sync),
2107 SH_PFC_PIN_GROUP(msiof0_ss1),
2108 SH_PFC_PIN_GROUP(msiof0_ss2),
2109 SH_PFC_PIN_GROUP(msiof0_txd),
2110 SH_PFC_PIN_GROUP(msiof0_rxd),
2111 SH_PFC_PIN_GROUP(msiof1_clk),
2112 SH_PFC_PIN_GROUP(msiof1_sync),
2113 SH_PFC_PIN_GROUP(msiof1_ss1),
2114 SH_PFC_PIN_GROUP(msiof1_ss2),
2115 SH_PFC_PIN_GROUP(msiof1_txd),
2116 SH_PFC_PIN_GROUP(msiof1_rxd),
2117 SH_PFC_PIN_GROUP(msiof2_clk),
2118 SH_PFC_PIN_GROUP(msiof2_sync),
2119 SH_PFC_PIN_GROUP(msiof2_ss1),
2120 SH_PFC_PIN_GROUP(msiof2_ss2),
2121 SH_PFC_PIN_GROUP(msiof2_txd),
2122 SH_PFC_PIN_GROUP(msiof2_rxd),
2123 SH_PFC_PIN_GROUP(msiof3_clk),
2124 SH_PFC_PIN_GROUP(msiof3_sync),
2125 SH_PFC_PIN_GROUP(msiof3_ss1),
2126 SH_PFC_PIN_GROUP(msiof3_ss2),
2127 SH_PFC_PIN_GROUP(msiof3_txd),
2128 SH_PFC_PIN_GROUP(msiof3_rxd),
2129 SH_PFC_PIN_GROUP(pwm0_a),
2130 SH_PFC_PIN_GROUP(pwm0_b),
2131 SH_PFC_PIN_GROUP(pwm1_a),
2132 SH_PFC_PIN_GROUP(pwm1_b),
2133 SH_PFC_PIN_GROUP(pwm2_a),
2134 SH_PFC_PIN_GROUP(pwm2_b),
2135 SH_PFC_PIN_GROUP(pwm3_a),
2136 SH_PFC_PIN_GROUP(pwm3_b),
2137 SH_PFC_PIN_GROUP(pwm4_a),
2138 SH_PFC_PIN_GROUP(pwm4_b),
2139 SH_PFC_PIN_GROUP(qspi0_ctrl),
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]2140 SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
2141 SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2142 SH_PFC_PIN_GROUP(qspi1_ctrl),
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]2143 SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
2144 SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
2145 BUS_DATA_PIN_GROUP(rpc_clk, 1),
2146 BUS_DATA_PIN_GROUP(rpc_clk, 2),
Marek Vasuta2a14852021-04-26 22:04:11 +0200[diff] [blame]2147 SH_PFC_PIN_GROUP(rpc_ctrl),
2148 SH_PFC_PIN_GROUP(rpc_data),
2149 SH_PFC_PIN_GROUP(rpc_reset),
2150 SH_PFC_PIN_GROUP(rpc_int),
2151 SH_PFC_PIN_GROUP(rpc_wp),
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2152 SH_PFC_PIN_GROUP(scif0_data),
2153 SH_PFC_PIN_GROUP(scif0_clk),
2154 SH_PFC_PIN_GROUP(scif0_ctrl),
2155 SH_PFC_PIN_GROUP(scif1_data_a),
2156 SH_PFC_PIN_GROUP(scif1_clk),
2157 SH_PFC_PIN_GROUP(scif1_ctrl),
2158 SH_PFC_PIN_GROUP(scif1_data_b),
2159 SH_PFC_PIN_GROUP(scif3_data),
2160 SH_PFC_PIN_GROUP(scif3_clk),
2161 SH_PFC_PIN_GROUP(scif3_ctrl),
2162 SH_PFC_PIN_GROUP(scif4_data),
2163 SH_PFC_PIN_GROUP(scif4_clk),
2164 SH_PFC_PIN_GROUP(scif4_ctrl),
2165 SH_PFC_PIN_GROUP(scif_clk_a),
2166 SH_PFC_PIN_GROUP(scif_clk_b),
2167 SH_PFC_PIN_GROUP(tmu_tclk1_a),
2168 SH_PFC_PIN_GROUP(tmu_tclk1_b),
2169 SH_PFC_PIN_GROUP(tmu_tclk2_a),
2170 SH_PFC_PIN_GROUP(tmu_tclk2_b),
2171 SH_PFC_PIN_GROUP(tpu_to0),
2172 SH_PFC_PIN_GROUP(tpu_to1),
2173 SH_PFC_PIN_GROUP(tpu_to2),
2174 SH_PFC_PIN_GROUP(tpu_to3),
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]2175 BUS_DATA_PIN_GROUP(vin0_data, 8),
2176 BUS_DATA_PIN_GROUP(vin0_data, 10),
2177 BUS_DATA_PIN_GROUP(vin0_data, 12),
2178 BUS_DATA_PIN_GROUP(vin0_data, 16),
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2179 SH_PFC_PIN_GROUP(vin0_data18),
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]2180 BUS_DATA_PIN_GROUP(vin0_data, 20),
2181 BUS_DATA_PIN_GROUP(vin0_data, 24),
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2182 SH_PFC_PIN_GROUP(vin0_sync),
2183 SH_PFC_PIN_GROUP(vin0_field),
2184 SH_PFC_PIN_GROUP(vin0_clkenb),
2185 SH_PFC_PIN_GROUP(vin0_clk),
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]2186 BUS_DATA_PIN_GROUP(vin1_data, 8),
2187 BUS_DATA_PIN_GROUP(vin1_data, 10),
2188 BUS_DATA_PIN_GROUP(vin1_data, 12),
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2189 SH_PFC_PIN_GROUP(vin1_sync),
2190 SH_PFC_PIN_GROUP(vin1_field),
2191 SH_PFC_PIN_GROUP(vin1_clkenb),
2192 SH_PFC_PIN_GROUP(vin1_clk),
2193};
2194
2195static const char * const avb_groups[] = {
2196 "avb_link",
2197 "avb_magic",
2198 "avb_phy_int",
2199 "avb_mdio",
2200 "avb_rgmii",
2201 "avb_txcrefclk",
2202 "avb_avtp_pps",
2203 "avb_avtp_capture",
2204 "avb_avtp_match",
2205};
2206
2207static const char * const canfd0_groups[] = {
2208 "canfd0_data_a",
2209 "canfd0_data_b",
2210};
2211
2212static const char * const canfd1_groups[] = {
2213 "canfd1_data",
2214};
2215
2216static const char * const canfd_clk_groups[] = {
2217 "canfd_clk_a",
2218 "canfd_clk_b",
2219};
2220
2221static const char * const du_groups[] = {
2222 "du_rgb666",
2223 "du_rgb888",
2224 "du_clk_out",
2225 "du_sync",
2226 "du_oddf",
2227 "du_cde",
2228 "du_disp",
2229};
2230
2231static const char * const gether_groups[] = {
2232 "gether_link_a",
2233 "gether_phy_int_a",
2234 "gether_mdio_a",
2235 "gether_link_b",
2236 "gether_phy_int_b",
2237 "gether_mdio_b",
2238 "gether_magic",
2239 "gether_rgmii",
2240 "gether_txcrefclk",
2241 "gether_txcrefclk_mega",
2242 "gether_rmii",
2243};
2244
2245static const char * const hscif0_groups[] = {
2246 "hscif0_data_a",
2247 "hscif0_clk_a",
2248 "hscif0_ctrl_a",
2249 "hscif0_data_b",
2250 "hscif0_clk_b",
2251 "hscif0_ctrl_b",
2252};
2253
2254static const char * const hscif1_groups[] = {
2255 "hscif1_data",
2256 "hscif1_clk",
2257 "hscif1_ctrl",
2258};
2259
2260static const char * const hscif2_groups[] = {
2261 "hscif2_data",
2262 "hscif2_clk",
2263 "hscif2_ctrl",
2264};
2265
2266static const char * const hscif3_groups[] = {
2267 "hscif3_data",
2268 "hscif3_clk",
2269 "hscif3_ctrl",
2270};
2271
2272static const char * const i2c0_groups[] = {
2273 "i2c0",
2274};
2275
2276static const char * const i2c1_groups[] = {
2277 "i2c1",
2278};
2279
2280static const char * const i2c2_groups[] = {
2281 "i2c2",
2282};
2283
2284static const char * const i2c3_groups[] = {
2285 "i2c3",
2286};
2287
2288static const char * const i2c4_groups[] = {
2289 "i2c4",
2290};
2291
2292static const char * const i2c5_groups[] = {
2293 "i2c5",
2294};
2295
2296static const char * const intc_ex_groups[] = {
2297 "intc_ex_irq0",
2298 "intc_ex_irq1",
2299 "intc_ex_irq2",
2300 "intc_ex_irq3",
2301 "intc_ex_irq4",
2302 "intc_ex_irq5",
2303};
2304
2305static const char * const mmc_groups[] = {
2306 "mmc_data1",
2307 "mmc_data4",
2308 "mmc_data8",
2309 "mmc_ctrl",
2310 "mmc_cd",
2311 "mmc_wp",
2312 "mmc_ds",
2313};
2314
2315static const char * const msiof0_groups[] = {
2316 "msiof0_clk",
2317 "msiof0_sync",
2318 "msiof0_ss1",
2319 "msiof0_ss2",
2320 "msiof0_txd",
2321 "msiof0_rxd",
2322};
2323
2324static const char * const msiof1_groups[] = {
2325 "msiof1_clk",
2326 "msiof1_sync",
2327 "msiof1_ss1",
2328 "msiof1_ss2",
2329 "msiof1_txd",
2330 "msiof1_rxd",
2331};
2332
2333static const char * const msiof2_groups[] = {
2334 "msiof2_clk",
2335 "msiof2_sync",
2336 "msiof2_ss1",
2337 "msiof2_ss2",
2338 "msiof2_txd",
2339 "msiof2_rxd",
2340};
2341
2342static const char * const msiof3_groups[] = {
2343 "msiof3_clk",
2344 "msiof3_sync",
2345 "msiof3_ss1",
2346 "msiof3_ss2",
2347 "msiof3_txd",
2348 "msiof3_rxd",
2349};
2350
2351static const char * const pwm0_groups[] = {
2352 "pwm0_a",
2353 "pwm0_b",
2354};
2355
2356static const char * const pwm1_groups[] = {
2357 "pwm1_a",
2358 "pwm1_b",
2359};
2360
2361static const char * const pwm2_groups[] = {
2362 "pwm2_a",
2363 "pwm2_b",
2364};
2365
2366static const char * const pwm3_groups[] = {
2367 "pwm3_a",
2368 "pwm3_b",
2369};
2370
2371static const char * const pwm4_groups[] = {
2372 "pwm4_a",
2373 "pwm4_b",
2374};
2375
2376static const char * const qspi0_groups[] = {
2377 "qspi0_ctrl",
2378 "qspi0_data2",
2379 "qspi0_data4",
2380};
2381
2382static const char * const qspi1_groups[] = {
2383 "qspi1_ctrl",
2384 "qspi1_data2",
2385 "qspi1_data4",
2386};
2387
Marek Vasuta2a14852021-04-26 22:04:11 +0200[diff] [blame]2388static const char * const rpc_groups[] = {
2389 "rpc_clk1",
2390 "rpc_clk2",
2391 "rpc_ctrl",
2392 "rpc_data",
2393 "rpc_reset",
2394 "rpc_int",
2395 "rpc_wp",
2396};
2397
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2398static const char * const scif0_groups[] = {
2399 "scif0_data",
2400 "scif0_clk",
2401 "scif0_ctrl",
2402};
2403
2404static const char * const scif1_groups[] = {
2405 "scif1_data_a",
2406 "scif1_clk",
2407 "scif1_ctrl",
2408 "scif1_data_b",
2409};
2410
2411static const char * const scif3_groups[] = {
2412 "scif3_data",
2413 "scif3_clk",
2414 "scif3_ctrl",
2415};
2416
2417static const char * const scif4_groups[] = {
2418 "scif4_data",
2419 "scif4_clk",
2420 "scif4_ctrl",
2421};
2422
2423static const char * const scif_clk_groups[] = {
2424 "scif_clk_a",
2425 "scif_clk_b",
2426};
2427
2428static const char * const tmu_groups[] = {
2429 "tmu_tclk1_a",
2430 "tmu_tclk1_b",
2431 "tmu_tclk2_a",
2432 "tmu_tclk2_b",
2433};
2434
2435static const char * const tpu_groups[] = {
2436 "tpu_to0",
2437 "tpu_to1",
2438 "tpu_to2",
2439 "tpu_to3",
2440};
2441
2442static const char * const vin0_groups[] = {
2443 "vin0_data8",
2444 "vin0_data10",
2445 "vin0_data12",
2446 "vin0_data16",
2447 "vin0_data18",
2448 "vin0_data20",
2449 "vin0_data24",
2450 "vin0_sync",
2451 "vin0_field",
2452 "vin0_clkenb",
2453 "vin0_clk",
2454};
2455
2456static const char * const vin1_groups[] = {
2457 "vin1_data8",
2458 "vin1_data10",
2459 "vin1_data12",
2460 "vin1_sync",
2461 "vin1_field",
2462 "vin1_clkenb",
2463 "vin1_clk",
2464};
2465
2466static const struct sh_pfc_function pinmux_functions[] = {
2467 SH_PFC_FUNCTION(avb),
2468 SH_PFC_FUNCTION(canfd0),
2469 SH_PFC_FUNCTION(canfd1),
2470 SH_PFC_FUNCTION(canfd_clk),
2471 SH_PFC_FUNCTION(du),
2472 SH_PFC_FUNCTION(gether),
2473 SH_PFC_FUNCTION(hscif0),
2474 SH_PFC_FUNCTION(hscif1),
2475 SH_PFC_FUNCTION(hscif2),
2476 SH_PFC_FUNCTION(hscif3),
2477 SH_PFC_FUNCTION(i2c0),
2478 SH_PFC_FUNCTION(i2c1),
2479 SH_PFC_FUNCTION(i2c2),
2480 SH_PFC_FUNCTION(i2c3),
2481 SH_PFC_FUNCTION(i2c4),
2482 SH_PFC_FUNCTION(i2c5),
2483 SH_PFC_FUNCTION(intc_ex),
2484 SH_PFC_FUNCTION(mmc),
2485 SH_PFC_FUNCTION(msiof0),
2486 SH_PFC_FUNCTION(msiof1),
2487 SH_PFC_FUNCTION(msiof2),
2488 SH_PFC_FUNCTION(msiof3),
2489 SH_PFC_FUNCTION(pwm0),
2490 SH_PFC_FUNCTION(pwm1),
2491 SH_PFC_FUNCTION(pwm2),
2492 SH_PFC_FUNCTION(pwm3),
2493 SH_PFC_FUNCTION(pwm4),
2494 SH_PFC_FUNCTION(qspi0),
2495 SH_PFC_FUNCTION(qspi1),
Marek Vasuta2a14852021-04-26 22:04:11 +0200[diff] [blame]2496 SH_PFC_FUNCTION(rpc),
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2497 SH_PFC_FUNCTION(scif0),
2498 SH_PFC_FUNCTION(scif1),
2499 SH_PFC_FUNCTION(scif3),
2500 SH_PFC_FUNCTION(scif4),
2501 SH_PFC_FUNCTION(scif_clk),
2502 SH_PFC_FUNCTION(tmu),
2503 SH_PFC_FUNCTION(tpu),
2504 SH_PFC_FUNCTION(vin0),
2505 SH_PFC_FUNCTION(vin1),
2506};
2507
2508static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2509#define F_(x, y) FN_##y
2510#define FM(x) FN_##x
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]2511 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
2512 GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2513 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2514 GROUP(
2515 /* GP0_31_22 RESERVED */
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2516 GP_0_21_FN, GPSR0_21,
2517 GP_0_20_FN, GPSR0_20,
2518 GP_0_19_FN, GPSR0_19,
2519 GP_0_18_FN, GPSR0_18,
2520 GP_0_17_FN, GPSR0_17,
2521 GP_0_16_FN, GPSR0_16,
2522 GP_0_15_FN, GPSR0_15,
2523 GP_0_14_FN, GPSR0_14,
2524 GP_0_13_FN, GPSR0_13,
2525 GP_0_12_FN, GPSR0_12,
2526 GP_0_11_FN, GPSR0_11,
2527 GP_0_10_FN, GPSR0_10,
2528 GP_0_9_FN, GPSR0_9,
2529 GP_0_8_FN, GPSR0_8,
2530 GP_0_7_FN, GPSR0_7,
2531 GP_0_6_FN, GPSR0_6,
2532 GP_0_5_FN, GPSR0_5,
2533 GP_0_4_FN, GPSR0_4,
2534 GP_0_3_FN, GPSR0_3,
2535 GP_0_2_FN, GPSR0_2,
2536 GP_0_1_FN, GPSR0_1,
2537 GP_0_0_FN, GPSR0_0, ))
2538 },
2539 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2540 0, 0,
2541 0, 0,
2542 0, 0,
2543 0, 0,
2544 GP_1_27_FN, GPSR1_27,
2545 GP_1_26_FN, GPSR1_26,
2546 GP_1_25_FN, GPSR1_25,
2547 GP_1_24_FN, GPSR1_24,
2548 GP_1_23_FN, GPSR1_23,
2549 GP_1_22_FN, GPSR1_22,
2550 GP_1_21_FN, GPSR1_21,
2551 GP_1_20_FN, GPSR1_20,
2552 GP_1_19_FN, GPSR1_19,
2553 GP_1_18_FN, GPSR1_18,
2554 GP_1_17_FN, GPSR1_17,
2555 GP_1_16_FN, GPSR1_16,
2556 GP_1_15_FN, GPSR1_15,
2557 GP_1_14_FN, GPSR1_14,
2558 GP_1_13_FN, GPSR1_13,
2559 GP_1_12_FN, GPSR1_12,
2560 GP_1_11_FN, GPSR1_11,
2561 GP_1_10_FN, GPSR1_10,
2562 GP_1_9_FN, GPSR1_9,
2563 GP_1_8_FN, GPSR1_8,
2564 GP_1_7_FN, GPSR1_7,
2565 GP_1_6_FN, GPSR1_6,
2566 GP_1_5_FN, GPSR1_5,
2567 GP_1_4_FN, GPSR1_4,
2568 GP_1_3_FN, GPSR1_3,
2569 GP_1_2_FN, GPSR1_2,
2570 GP_1_1_FN, GPSR1_1,
2571 GP_1_0_FN, GPSR1_0, ))
2572 },
2573 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2574 0, 0,
2575 0, 0,
2576 GP_2_29_FN, GPSR2_29,
2577 GP_2_28_FN, GPSR2_28,
2578 GP_2_27_FN, GPSR2_27,
2579 GP_2_26_FN, GPSR2_26,
2580 GP_2_25_FN, GPSR2_25,
2581 GP_2_24_FN, GPSR2_24,
2582 GP_2_23_FN, GPSR2_23,
2583 GP_2_22_FN, GPSR2_22,
2584 GP_2_21_FN, GPSR2_21,
2585 GP_2_20_FN, GPSR2_20,
2586 GP_2_19_FN, GPSR2_19,
2587 GP_2_18_FN, GPSR2_18,
2588 GP_2_17_FN, GPSR2_17,
2589 GP_2_16_FN, GPSR2_16,
2590 GP_2_15_FN, GPSR2_15,
2591 GP_2_14_FN, GPSR2_14,
2592 GP_2_13_FN, GPSR2_13,
2593 GP_2_12_FN, GPSR2_12,
2594 GP_2_11_FN, GPSR2_11,
2595 GP_2_10_FN, GPSR2_10,
2596 GP_2_9_FN, GPSR2_9,
2597 GP_2_8_FN, GPSR2_8,
2598 GP_2_7_FN, GPSR2_7,
2599 GP_2_6_FN, GPSR2_6,
2600 GP_2_5_FN, GPSR2_5,
2601 GP_2_4_FN, GPSR2_4,
2602 GP_2_3_FN, GPSR2_3,
2603 GP_2_2_FN, GPSR2_2,
2604 GP_2_1_FN, GPSR2_1,
2605 GP_2_0_FN, GPSR2_0, ))
2606 },
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]2607 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
2608 GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2609 1, 1, 1, 1, 1, 1),
2610 GROUP(
2611 /* GP3_31_17 RESERVED */
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2612 GP_3_16_FN, GPSR3_16,
2613 GP_3_15_FN, GPSR3_15,
2614 GP_3_14_FN, GPSR3_14,
2615 GP_3_13_FN, GPSR3_13,
2616 GP_3_12_FN, GPSR3_12,
2617 GP_3_11_FN, GPSR3_11,
2618 GP_3_10_FN, GPSR3_10,
2619 GP_3_9_FN, GPSR3_9,
2620 GP_3_8_FN, GPSR3_8,
2621 GP_3_7_FN, GPSR3_7,
2622 GP_3_6_FN, GPSR3_6,
2623 GP_3_5_FN, GPSR3_5,
2624 GP_3_4_FN, GPSR3_4,
2625 GP_3_3_FN, GPSR3_3,
2626 GP_3_2_FN, GPSR3_2,
2627 GP_3_1_FN, GPSR3_1,
2628 GP_3_0_FN, GPSR3_0, ))
2629 },
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]2630 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
2631 GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2632 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2633 1, 1),
2634 GROUP(
2635 /* GP4_31_25 RESERVED */
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2636 GP_4_24_FN, GPSR4_24,
2637 GP_4_23_FN, GPSR4_23,
2638 GP_4_22_FN, GPSR4_22,
2639 GP_4_21_FN, GPSR4_21,
2640 GP_4_20_FN, GPSR4_20,
2641 GP_4_19_FN, GPSR4_19,
2642 GP_4_18_FN, GPSR4_18,
2643 GP_4_17_FN, GPSR4_17,
2644 GP_4_16_FN, GPSR4_16,
2645 GP_4_15_FN, GPSR4_15,
2646 GP_4_14_FN, GPSR4_14,
2647 GP_4_13_FN, GPSR4_13,
2648 GP_4_12_FN, GPSR4_12,
2649 GP_4_11_FN, GPSR4_11,
2650 GP_4_10_FN, GPSR4_10,
2651 GP_4_9_FN, GPSR4_9,
2652 GP_4_8_FN, GPSR4_8,
2653 GP_4_7_FN, GPSR4_7,
2654 GP_4_6_FN, GPSR4_6,
2655 GP_4_5_FN, GPSR4_5,
2656 GP_4_4_FN, GPSR4_4,
2657 GP_4_3_FN, GPSR4_3,
2658 GP_4_2_FN, GPSR4_2,
2659 GP_4_1_FN, GPSR4_1,
2660 GP_4_0_FN, GPSR4_0, ))
2661 },
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]2662 { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
2663 GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2664 1, 1, 1, 1),
2665 GROUP(
2666 /* GP5_31_15 RESERVED */
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2667 GP_5_14_FN, GPSR5_14,
2668 GP_5_13_FN, GPSR5_13,
2669 GP_5_12_FN, GPSR5_12,
2670 GP_5_11_FN, GPSR5_11,
2671 GP_5_10_FN, GPSR5_10,
2672 GP_5_9_FN, GPSR5_9,
2673 GP_5_8_FN, GPSR5_8,
2674 GP_5_7_FN, GPSR5_7,
2675 GP_5_6_FN, GPSR5_6,
2676 GP_5_5_FN, GPSR5_5,
2677 GP_5_4_FN, GPSR5_4,
2678 GP_5_3_FN, GPSR5_3,
2679 GP_5_2_FN, GPSR5_2,
2680 GP_5_1_FN, GPSR5_1,
2681 GP_5_0_FN, GPSR5_0, ))
2682 },
2683#undef F_
2684#undef FM
2685
2686#define F_(x, y) x,
2687#define FM(x) FN_##x,
2688 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2689 IP0_31_28
2690 IP0_27_24
2691 IP0_23_20
2692 IP0_19_16
2693 IP0_15_12
2694 IP0_11_8
2695 IP0_7_4
2696 IP0_3_0 ))
2697 },
2698 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2699 IP1_31_28
2700 IP1_27_24
2701 IP1_23_20
2702 IP1_19_16
2703 IP1_15_12
2704 IP1_11_8
2705 IP1_7_4
2706 IP1_3_0 ))
2707 },
2708 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2709 IP2_31_28
2710 IP2_27_24
2711 IP2_23_20
2712 IP2_19_16
2713 IP2_15_12
2714 IP2_11_8
2715 IP2_7_4
2716 IP2_3_0 ))
2717 },
2718 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2719 IP3_31_28
2720 IP3_27_24
2721 IP3_23_20
2722 IP3_19_16
2723 IP3_15_12
2724 IP3_11_8
2725 IP3_7_4
2726 IP3_3_0 ))
2727 },
2728 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2729 IP4_31_28
2730 IP4_27_24
2731 IP4_23_20
2732 IP4_19_16
2733 IP4_15_12
2734 IP4_11_8
2735 IP4_7_4
2736 IP4_3_0 ))
2737 },
2738 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2739 IP5_31_28
2740 IP5_27_24
2741 IP5_23_20
2742 IP5_19_16
2743 IP5_15_12
2744 IP5_11_8
2745 IP5_7_4
2746 IP5_3_0 ))
2747 },
2748 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2749 IP6_31_28
2750 IP6_27_24
2751 IP6_23_20
2752 IP6_19_16
2753 IP6_15_12
2754 IP6_11_8
2755 IP6_7_4
2756 IP6_3_0 ))
2757 },
2758 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2759 IP7_31_28
2760 IP7_27_24
2761 IP7_23_20
2762 IP7_19_16
2763 IP7_15_12
2764 IP7_11_8
2765 IP7_7_4
2766 IP7_3_0 ))
2767 },
2768 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2769 IP8_31_28
2770 IP8_27_24
2771 IP8_23_20
2772 IP8_19_16
2773 IP8_15_12
2774 IP8_11_8
2775 IP8_7_4
2776 IP8_3_0 ))
2777 },
2778 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
2779 IP9_31_28
2780 IP9_27_24
2781 IP9_23_20
2782 IP9_19_16
2783 IP9_15_12
2784 IP9_11_8
2785 IP9_7_4
2786 IP9_3_0 ))
2787 },
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]2788 { PINMUX_CFG_REG_VAR("IPSR10", 0xe6060228, 32,
2789 GROUP(-12, 4, 4, 4, 4, 4),
2790 GROUP(
2791 /* IP10_31_20 RESERVED */
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2792 IP10_19_16
2793 IP10_15_12
2794 IP10_11_8
2795 IP10_7_4
2796 IP10_3_0 ))
2797 },
2798#undef F_
2799#undef FM
2800
2801#define F_(x, y) x,
2802#define FM(x) FN_##x,
2803 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]2804 GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, -1, 1, 1, 1),
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2805 GROUP(
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]2806 /* RESERVED 31-12 */
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2807 MOD_SEL0_11
2808 MOD_SEL0_10
2809 MOD_SEL0_9
2810 MOD_SEL0_8
2811 MOD_SEL0_7
2812 MOD_SEL0_6
2813 MOD_SEL0_5
2814 MOD_SEL0_4
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]2815 /* RESERVED 3 */
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2816 MOD_SEL0_2
2817 MOD_SEL0_1
2818 MOD_SEL0_0 ))
2819 },
Marek Vasut827cece2023-09-17 16:08:44 +0200[diff] [blame]2820 { /* sentinel */ }
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2821};
2822
2823enum ioctrl_regs {
2824 POCCTRL0,
2825 POCCTRL1,
2826 POCCTRL2,
2827 POCCTRL3,
2828 TDSELCTRL,
2829};
2830
2831static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2832 [POCCTRL0] = { 0xe6060380, },
2833 [POCCTRL1] = { 0xe6060384, },
2834 [POCCTRL2] = { 0xe6060388, },
2835 [POCCTRL3] = { 0xe606038c, },
2836 [TDSELCTRL] = { 0xe60603c0, },
Marek Vasut827cece2023-09-17 16:08:44 +0200[diff] [blame]2837 { /* sentinel */ }
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2838};
2839
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]2840static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2841{
2842 int bit = pin & 0x1f;
2843
Marek Vasut827cece2023-09-17 16:08:44 +0200[diff] [blame]2844 switch (pin) {
2845 case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21):
2846 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2847 return bit;
Marek Vasut827cece2023-09-17 16:08:44 +0200[diff] [blame]2848
2849 case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9):
2850 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2851 return bit + 22;
2852
Marek Vasut827cece2023-09-17 16:08:44 +0200[diff] [blame]2853 case RCAR_GP_PIN(2, 10) ... RCAR_GP_PIN(2, 16):
2854 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2855 return bit - 10;
Marek Vasut827cece2023-09-17 16:08:44 +0200[diff] [blame]2856
2857 case RCAR_GP_PIN(2, 17) ... RCAR_GP_PIN(2, 24):
2858 case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 16):
2859 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2860 return bit + 7;
2861
Marek Vasut827cece2023-09-17 16:08:44 +0200[diff] [blame]2862 case RCAR_GP_PIN(2, 25) ... RCAR_GP_PIN(2, 29):
2863 *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2864 return pin - 25;
2865
Marek Vasut827cece2023-09-17 16:08:44 +0200[diff] [blame]2866 case PIN_VDDQ_AVB:
2867 *pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
2868 return 0;
2869
2870 case PIN_VDDQ_GE:
2871 *pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
2872 return 1;
2873
2874 default:
2875 return -EINVAL;
2876 }
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]2877}
2878
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]2879static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2880 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
2881 [ 0] = RCAR_GP_PIN(0, 0), /* DU_DR2 */
2882 [ 1] = RCAR_GP_PIN(0, 1), /* DU_DR3 */
2883 [ 2] = RCAR_GP_PIN(0, 2), /* DU_DR4 */
2884 [ 3] = RCAR_GP_PIN(0, 3), /* DU_DR5 */
2885 [ 4] = RCAR_GP_PIN(0, 4), /* DU_DR6 */
2886 [ 5] = RCAR_GP_PIN(0, 5), /* DU_DR7 */
2887 [ 6] = RCAR_GP_PIN(0, 6), /* DU_DG2 */
2888 [ 7] = RCAR_GP_PIN(0, 7), /* DU_DG3 */
2889 [ 8] = RCAR_GP_PIN(0, 8), /* DU_DG4 */
2890 [ 9] = RCAR_GP_PIN(0, 9), /* DU_DG5 */
2891 [10] = RCAR_GP_PIN(0, 10), /* DU_DG6 */
2892 [11] = RCAR_GP_PIN(0, 11), /* DU_DG7 */
2893 [12] = RCAR_GP_PIN(0, 12), /* DU_DB2 */
2894 [13] = RCAR_GP_PIN(0, 13), /* DU_DB3 */
2895 [14] = RCAR_GP_PIN(0, 14), /* DU_DB4 */
2896 [15] = RCAR_GP_PIN(0, 15), /* DU_DB5 */
2897 [16] = RCAR_GP_PIN(0, 16), /* DU_DB6 */
2898 [17] = RCAR_GP_PIN(0, 17), /* DU_DB7 */
2899 [18] = RCAR_GP_PIN(0, 18), /* DU_DOTCLKOUT */
2900 [19] = RCAR_GP_PIN(0, 19), /* DU_EXHSYNC/DU_HSYNC */
2901 [20] = RCAR_GP_PIN(0, 20), /* DU_EXVSYNC/DU_VSYNC */
2902 [21] = RCAR_GP_PIN(0, 21), /* DU_EXODDF/DU_ODDF/DISP/CDE */
2903 [22] = SH_PFC_PIN_NONE,
2904 [23] = SH_PFC_PIN_NONE,
2905 [24] = PIN_DU_DOTCLKIN, /* DU_DOTCLKIN */
2906 [25] = SH_PFC_PIN_NONE,
2907 [26] = PIN_PRESETOUT_N, /* PRESETOUT# */
2908 [27] = SH_PFC_PIN_NONE,
2909 [28] = SH_PFC_PIN_NONE,
2910 [29] = SH_PFC_PIN_NONE,
2911 [30] = PIN_EXTALR, /* EXTALR */
2912 [31] = PIN_FSCLKST_N, /* FSCLKST# */
2913 } },
2914 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
2915 [ 0] = PIN_FSCLKST, /* FSCLKST */
2916 [ 1] = SH_PFC_PIN_NONE,
2917 [ 2] = RCAR_GP_PIN(1, 0), /* IRQ0 */
2918 [ 3] = PIN_DCUTRST_N, /* DCUTRST# */
2919 [ 4] = PIN_DCUTCK_LPDCLK, /* DCUTCK_LPDCLK */
2920 [ 5] = PIN_DCUTMS, /* DCUTMS */
2921 [ 6] = PIN_DCUTDI_LPDI, /* DCUTDI_LPDI */
2922 [ 7] = SH_PFC_PIN_NONE,
2923 [ 8] = RCAR_GP_PIN(2, 0), /* VI0_CLK */
2924 [ 9] = RCAR_GP_PIN(2, 1), /* VI0_CLKENB */
2925 [10] = RCAR_GP_PIN(2, 2), /* VI0_HSYNC# */
2926 [11] = RCAR_GP_PIN(2, 3), /* VI0_VSYNC# */
2927 [12] = RCAR_GP_PIN(2, 4), /* VI0_DATA0 */
2928 [13] = RCAR_GP_PIN(2, 5), /* VI0_DATA1 */
2929 [14] = RCAR_GP_PIN(2, 6), /* VI0_DATA2 */
2930 [15] = RCAR_GP_PIN(2, 7), /* VI0_DATA3 */
2931 [16] = RCAR_GP_PIN(2, 8), /* VI0_DATA4 */
2932 [17] = RCAR_GP_PIN(2, 9), /* VI0_DATA5 */
2933 [18] = RCAR_GP_PIN(2, 10), /* VI0_DATA6 */
2934 [19] = RCAR_GP_PIN(2, 11), /* VI0_DATA7 */
2935 [20] = RCAR_GP_PIN(2, 12), /* VI0_DATA8 */
2936 [21] = RCAR_GP_PIN(2, 13), /* VI0_DATA9 */
2937 [22] = RCAR_GP_PIN(2, 14), /* VI0_DATA10 */
2938 [23] = RCAR_GP_PIN(2, 15), /* VI0_DATA11 */
2939 [24] = RCAR_GP_PIN(2, 16), /* VI0_FIELD */
2940 [25] = RCAR_GP_PIN(3, 0), /* VI1_CLK */
2941 [26] = RCAR_GP_PIN(3, 1), /* VI1_CLKENB */
2942 [27] = RCAR_GP_PIN(3, 2), /* VI1_HSYNC# */
2943 [28] = RCAR_GP_PIN(3, 3), /* VI1_VSYNC# */
2944 [29] = RCAR_GP_PIN(3, 4), /* VI1_DATA0 */
2945 [30] = RCAR_GP_PIN(3, 5), /* VI1_DATA1 */
2946 [31] = RCAR_GP_PIN(3, 6), /* VI1_DATA2 */
2947 } },
2948 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
2949 [ 0] = RCAR_GP_PIN(3, 7), /* VI1_DATA3 */
2950 [ 1] = RCAR_GP_PIN(3, 8), /* VI1_DATA4 */
2951 [ 2] = RCAR_GP_PIN(3, 9), /* VI1_DATA5 */
2952 [ 3] = RCAR_GP_PIN(3, 10), /* VI1_DATA6 */
2953 [ 4] = RCAR_GP_PIN(3, 11), /* VI1_DATA7 */
2954 [ 5] = RCAR_GP_PIN(3, 12), /* VI1_DATA8 */
2955 [ 6] = RCAR_GP_PIN(3, 13), /* VI1_DATA9 */
2956 [ 7] = RCAR_GP_PIN(3, 14), /* VI1_DATA10 */
2957 [ 8] = RCAR_GP_PIN(3, 15), /* VI1_DATA11 */
2958 [ 9] = RCAR_GP_PIN(3, 16), /* VI1_FIELD */
2959 [10] = RCAR_GP_PIN(4, 0), /* SCL0 */
2960 [11] = RCAR_GP_PIN(4, 1), /* SDA0 */
2961 [12] = RCAR_GP_PIN(4, 2), /* SCL1 */
2962 [13] = RCAR_GP_PIN(4, 3), /* SDA1 */
2963 [14] = RCAR_GP_PIN(4, 4), /* SCL2 */
2964 [15] = RCAR_GP_PIN(4, 5), /* SDA2 */
2965 [16] = RCAR_GP_PIN(1, 1), /* AVB_RX_CTL */
2966 [17] = RCAR_GP_PIN(1, 2), /* AVB_RXC */
2967 [18] = RCAR_GP_PIN(1, 3), /* AVB_RD0 */
2968 [19] = RCAR_GP_PIN(1, 4), /* AVB_RD1 */
2969 [20] = RCAR_GP_PIN(1, 5), /* AVB_RD2 */
2970 [21] = RCAR_GP_PIN(1, 6), /* AVB_RD3 */
2971 [22] = RCAR_GP_PIN(1, 7), /* AVB_TX_CTL */
2972 [23] = RCAR_GP_PIN(1, 8), /* AVB_TXC */
2973 [24] = RCAR_GP_PIN(1, 9), /* AVB_TD0 */
2974 [25] = RCAR_GP_PIN(1, 10), /* AVB_TD1 */
2975 [26] = RCAR_GP_PIN(1, 11), /* AVB_TD2 */
2976 [27] = RCAR_GP_PIN(1, 12), /* AVB_TD3 */
2977 [28] = RCAR_GP_PIN(1, 13), /* AVB_TXCREFCLK */
2978 [29] = RCAR_GP_PIN(1, 14), /* AVB_MDIO */
2979 [30] = RCAR_GP_PIN(1, 15), /* AVB_MDC */
2980 [31] = RCAR_GP_PIN(1, 16), /* AVB_MAGIC */
2981 } },
2982 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
2983 [ 0] = RCAR_GP_PIN(1, 17), /* AVB_PHY_INT */
2984 [ 1] = RCAR_GP_PIN(1, 18), /* AVB_LINK */
2985 [ 2] = RCAR_GP_PIN(1, 19), /* AVB_AVTP_MATCH */
2986 [ 3] = RCAR_GP_PIN(1, 20), /* AVTP_CAPTURE */
2987 [ 4] = RCAR_GP_PIN(4, 6), /* GETHER_RX_CTL */
2988 [ 5] = RCAR_GP_PIN(4, 7), /* GETHER_RXC */
2989 [ 6] = RCAR_GP_PIN(4, 8), /* GETHER_RD0 */
2990 [ 7] = RCAR_GP_PIN(4, 9), /* GETHER_RD1 */
2991 [ 8] = RCAR_GP_PIN(4, 10), /* GETHER_RD2 */
2992 [ 9] = RCAR_GP_PIN(4, 11), /* GETHER_RD3 */
2993 [10] = RCAR_GP_PIN(4, 12), /* GETHER_TX_CTL */
2994 [11] = RCAR_GP_PIN(4, 13), /* GETHER_TXC */
2995 [12] = RCAR_GP_PIN(4, 14), /* GETHER_TD0 */
2996 [13] = RCAR_GP_PIN(4, 15), /* GETHER_TD1 */
2997 [14] = RCAR_GP_PIN(4, 16), /* GETHER_TD2 */
2998 [15] = RCAR_GP_PIN(4, 17), /* GETHER_TD3 */
2999 [16] = RCAR_GP_PIN(4, 18), /* GETHER_TXCREFCLK */
3000 [17] = RCAR_GP_PIN(4, 19), /* GETHER_TXCREFCLK_MEGA */
3001 [18] = RCAR_GP_PIN(4, 20), /* GETHER_MDIO_A */
3002 [19] = RCAR_GP_PIN(4, 21), /* GETHER_MDC_A */
3003 [20] = RCAR_GP_PIN(4, 22), /* GETHER_MAGIC */
3004 [21] = RCAR_GP_PIN(4, 23), /* GETHER_PHY_INT_A */
3005 [22] = RCAR_GP_PIN(4, 24), /* GETHER_LINK_A */
3006 [23] = RCAR_GP_PIN(1, 21), /* CANFD0_TX_A */
3007 [24] = RCAR_GP_PIN(1, 22), /* CANFD0_RX_A */
3008 [25] = RCAR_GP_PIN(1, 23), /* CANFD1_TX */
3009 [26] = RCAR_GP_PIN(1, 24), /* CANFD1_RX */
3010 [27] = RCAR_GP_PIN(1, 25), /* CAN_CLK_A */
3011 [28] = RCAR_GP_PIN(5, 0), /* QSPI0_SPCLK */
3012 [29] = RCAR_GP_PIN(5, 1), /* QSPI0_MOSI_IO0 */
3013 [30] = RCAR_GP_PIN(5, 2), /* QSPI0_MISO_IO1 */
3014 [31] = RCAR_GP_PIN(5, 3), /* QSPI0_IO2 */
3015 } },
3016 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
3017 [ 0] = RCAR_GP_PIN(5, 4), /* QSPI0_IO3 */
3018 [ 1] = RCAR_GP_PIN(5, 5), /* QSPI0_SSL */
3019 [ 2] = RCAR_GP_PIN(5, 6), /* QSPI1_SPCLK */
3020 [ 3] = RCAR_GP_PIN(5, 7), /* QSPI1_MOSI_IO0 */
3021 [ 4] = RCAR_GP_PIN(5, 8), /* QSPI1_MISO_IO1 */
3022 [ 5] = RCAR_GP_PIN(5, 9), /* QSPI1_IO2 */
3023 [ 6] = RCAR_GP_PIN(5, 10), /* QSPI1_IO3 */
3024 [ 7] = RCAR_GP_PIN(5, 11), /* QSPI1_SSL */
3025 [ 8] = RCAR_GP_PIN(5, 12), /* RPC_RESET# */
3026 [ 9] = RCAR_GP_PIN(5, 13), /* RPC_WP# */
3027 [10] = RCAR_GP_PIN(5, 14), /* RPC_INT# */
3028 [11] = RCAR_GP_PIN(1, 26), /* DIGRF_CLKIN */
3029 [12] = RCAR_GP_PIN(1, 27), /* DIGRF_CLKOUT */
3030 [13] = RCAR_GP_PIN(2, 17), /* IRQ4 */
3031 [14] = RCAR_GP_PIN(2, 18), /* IRQ5 */
3032 [15] = RCAR_GP_PIN(2, 25), /* SCL3 */
3033 [16] = RCAR_GP_PIN(2, 26), /* SDA3 */
3034 [17] = RCAR_GP_PIN(2, 19), /* MSIOF0_RXD */
3035 [18] = RCAR_GP_PIN(2, 20), /* MSIOF0_TXD */
3036 [19] = RCAR_GP_PIN(2, 21), /* MSIOF0_SCK */
3037 [20] = RCAR_GP_PIN(2, 22), /* MSIOF0_SYNC */
3038 [21] = RCAR_GP_PIN(2, 23), /* MSIOF0_SS1 */
3039 [22] = RCAR_GP_PIN(2, 24), /* MSIOF0_SS2 */
3040 [23] = RCAR_GP_PIN(2, 27), /* FSO_CFE_0# */
3041 [24] = RCAR_GP_PIN(2, 28), /* FSO_CFE_1# */
3042 [25] = RCAR_GP_PIN(2, 29), /* FSO_TOE# */
3043 [26] = SH_PFC_PIN_NONE,
3044 [27] = SH_PFC_PIN_NONE,
3045 [28] = SH_PFC_PIN_NONE,
3046 [29] = SH_PFC_PIN_NONE,
3047 [30] = SH_PFC_PIN_NONE,
3048 [31] = SH_PFC_PIN_NONE,
3049 } },
3050 { /* sentinel */ }
3051};
3052
3053static const struct sh_pfc_soc_operations r8a77980_pfc_ops = {
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]3054 .pin_to_pocctrl = r8a77980_pin_to_pocctrl,
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]3055 .get_bias = rcar_pinmux_get_bias,
3056 .set_bias = rcar_pinmux_set_bias,
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]3057};
3058
3059const struct sh_pfc_soc_info r8a77980_pinmux_info = {
3060 .name = "r8a77980_pfc",
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]3061 .ops = &r8a77980_pfc_ops,
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]3062 .unlock_reg = 0xe6060000, /* PMMR */
3063
3064 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3065
3066 .pins = pinmux_pins,
3067 .nr_pins = ARRAY_SIZE(pinmux_pins),
3068 .groups = pinmux_groups,
3069 .nr_groups = ARRAY_SIZE(pinmux_groups),
3070 .functions = pinmux_functions,
3071 .nr_functions = ARRAY_SIZE(pinmux_functions),
3072
3073 .cfg_regs = pinmux_config_regs,
Marek Vasut3bf49332023-01-26 21:01:44 +0100[diff] [blame]3074 .bias_regs = pinmux_bias_regs,
Marek Vasutf497ec32019-07-29 19:59:44 +0200[diff] [blame]3075 .ioctrl_regs = pinmux_ioctrl_regs,
3076
3077 .pinmux_data = pinmux_data,
3078 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3079};