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wdenk945af8d2003-07-16 21:53:01 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
wdenke35745b2004-04-18 23:32:11 +00005 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
wdenk945af8d2003-07-16 21:53:01 +00008 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <mpc5xxx.h>
wdenk96e48cf2003-08-05 18:22:44 +000029#include <pci.h>
Rafal Jaworowskib66a9382006-03-29 13:17:09 +020030#include <asm/processor.h>
wdenk945af8d2003-07-16 21:53:01 +000031
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010032#if defined(CONFIG_LITE5200B)
33#include "mt46v32m16.h"
wdenke35745b2004-04-18 23:32:11 +000034#else
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010035# if defined(CONFIG_MPC5200_DDR)
36# include "mt46v16m16-75.h"
37# else
wdenke35745b2004-04-18 23:32:11 +000038#include "mt48lc16m16a2-75.h"
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010039# endif
wdenke35745b2004-04-18 23:32:11 +000040#endif
wdenkd94f92c2003-08-28 09:41:22 +000041#ifndef CFG_RAMBOOT
wdenke0ac62d2003-08-17 18:55:18 +000042static void sdram_start (int hi_addr)
43{
44 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
45
wdenkb2001f22003-12-20 22:45:10 +000046 /* unlock mode register */
wdenke35745b2004-04-18 23:32:11 +000047 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
48 __asm__ volatile ("sync");
wdenk5cf91d62004-04-23 20:32:05 +000049
wdenkb2001f22003-12-20 22:45:10 +000050 /* precharge all banks */
wdenke35745b2004-04-18 23:32:11 +000051 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
52 __asm__ volatile ("sync");
53
54#if SDRAM_DDR
wdenkb2001f22003-12-20 22:45:10 +000055 /* set mode register: extended mode */
wdenke35745b2004-04-18 23:32:11 +000056 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
57 __asm__ volatile ("sync");
58
wdenkb2001f22003-12-20 22:45:10 +000059 /* set mode register: reset DLL */
wdenke35745b2004-04-18 23:32:11 +000060 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
61 __asm__ volatile ("sync");
wdenke0ac62d2003-08-17 18:55:18 +000062#endif
wdenke35745b2004-04-18 23:32:11 +000063
64 /* precharge all banks */
65 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
66 __asm__ volatile ("sync");
67
wdenkf8d813e2004-03-02 14:05:39 +000068 /* auto refresh */
wdenke35745b2004-04-18 23:32:11 +000069 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
70 __asm__ volatile ("sync");
71
wdenke0ac62d2003-08-17 18:55:18 +000072 /* set mode register */
wdenke35745b2004-04-18 23:32:11 +000073 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
74 __asm__ volatile ("sync");
wdenk5cf91d62004-04-23 20:32:05 +000075
wdenke0ac62d2003-08-17 18:55:18 +000076 /* normal operation */
wdenke35745b2004-04-18 23:32:11 +000077 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
78 __asm__ volatile ("sync");
wdenke0ac62d2003-08-17 18:55:18 +000079}
wdenkd94f92c2003-08-28 09:41:22 +000080#endif
wdenke0ac62d2003-08-17 18:55:18 +000081
wdenke35745b2004-04-18 23:32:11 +000082/*
83 * ATTENTION: Although partially referenced initdram does NOT make real use
84 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
85 * is something else than 0x00000000.
86 */
87
88#if defined(CONFIG_MPC5200)
wdenk945af8d2003-07-16 21:53:01 +000089long int initdram (int board_type)
90{
wdenkd94f92c2003-08-28 09:41:22 +000091 ulong dramsize = 0;
wdenkb2001f22003-12-20 22:45:10 +000092 ulong dramsize2 = 0;
Rafal Jaworowskib66a9382006-03-29 13:17:09 +020093 uint svr, pvr;
94
wdenk945af8d2003-07-16 21:53:01 +000095#ifndef CFG_RAMBOOT
wdenkd94f92c2003-08-28 09:41:22 +000096 ulong test1, test2;
wdenk5cf91d62004-04-23 20:32:05 +000097
wdenke35745b2004-04-18 23:32:11 +000098 /* setup SDRAM chip selects */
wdenke0ac62d2003-08-17 18:55:18 +000099 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
100 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
wdenke35745b2004-04-18 23:32:11 +0000101 __asm__ volatile ("sync");
wdenk945af8d2003-07-16 21:53:01 +0000102
wdenkb2001f22003-12-20 22:45:10 +0000103 /* setup config registers */
wdenke35745b2004-04-18 23:32:11 +0000104 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
105 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
106 __asm__ volatile ("sync");
wdenkd4ca31c2004-01-02 14:00:00 +0000107
wdenke35745b2004-04-18 23:32:11 +0000108#if SDRAM_DDR
109 /* set tap delay */
110 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
111 __asm__ volatile ("sync");
wdenkb2001f22003-12-20 22:45:10 +0000112#endif
wdenk945af8d2003-07-16 21:53:01 +0000113
wdenke35745b2004-04-18 23:32:11 +0000114 /* find RAM size using SDRAM CS0 only */
wdenke0ac62d2003-08-17 18:55:18 +0000115 sdram_start(0);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200116 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
wdenke0ac62d2003-08-17 18:55:18 +0000117 sdram_start(1);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200118 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
wdenke0ac62d2003-08-17 18:55:18 +0000119 if (test1 > test2) {
120 sdram_start(0);
121 dramsize = test1;
122 } else {
123 dramsize = test2;
124 }
wdenke35745b2004-04-18 23:32:11 +0000125
126 /* memory smaller than 1MB is impossible */
127 if (dramsize < (1 << 20)) {
128 dramsize = 0;
129 }
wdenk5cf91d62004-04-23 20:32:05 +0000130
wdenke35745b2004-04-18 23:32:11 +0000131 /* set SDRAM CS0 size according to the amount of RAM found */
132 if (dramsize > 0) {
133 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
134 } else {
135 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
136 }
137
wdenke35745b2004-04-18 23:32:11 +0000138 /* let SDRAM CS1 start right after CS0 */
wdenkb2001f22003-12-20 22:45:10 +0000139 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
wdenke35745b2004-04-18 23:32:11 +0000140
141 /* find RAM size using SDRAM CS1 only */
wdenk07cc0992005-05-05 00:04:14 +0000142 if (!dramsize)
wdenka6310922005-04-21 21:10:22 +0000143 sdram_start(0);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200144 test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
wdenka6310922005-04-21 21:10:22 +0000145 if (!dramsize) {
146 sdram_start(1);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200147 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
wdenka6310922005-04-21 21:10:22 +0000148 }
wdenkb2001f22003-12-20 22:45:10 +0000149 if (test1 > test2) {
150 sdram_start(0);
151 dramsize2 = test1;
152 } else {
153 dramsize2 = test2;
154 }
wdenk5cf91d62004-04-23 20:32:05 +0000155
wdenke35745b2004-04-18 23:32:11 +0000156 /* memory smaller than 1MB is impossible */
157 if (dramsize2 < (1 << 20)) {
158 dramsize2 = 0;
159 }
wdenk5cf91d62004-04-23 20:32:05 +0000160
wdenke35745b2004-04-18 23:32:11 +0000161 /* set SDRAM CS1 size according to the amount of RAM found */
162 if (dramsize2 > 0) {
163 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
164 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
165 } else {
166 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
167 }
wdenke0ac62d2003-08-17 18:55:18 +0000168
wdenke35745b2004-04-18 23:32:11 +0000169#else /* CFG_RAMBOOT */
170
171 /* retrieve size of memory connected to SDRAM CS0 */
172 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
173 if (dramsize >= 0x13) {
174 dramsize = (1 << (dramsize - 0x13)) << 20;
175 } else {
176 dramsize = 0;
177 }
178
179 /* retrieve size of memory connected to SDRAM CS1 */
180 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
181 if (dramsize2 >= 0x13) {
182 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
183 } else {
184 dramsize2 = 0;
185 }
186
wdenkd94f92c2003-08-28 09:41:22 +0000187#endif /* CFG_RAMBOOT */
wdenkb2001f22003-12-20 22:45:10 +0000188
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200189 /*
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200190 * On MPC5200B we need to set the special configuration delay in the
191 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200192 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
193 *
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200194 * "The SDelay should be written to a value of 0x00000004. It is
195 * required to account for changes caused by normal wafer processing
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200196 * parameters."
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200197 */
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200198 svr = get_svr();
199 pvr = get_pvr();
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200200 if ((SVR_MJREV(svr) >= 2) &&
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200201 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
202
203 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
204 __asm__ volatile ("sync");
205 }
206
wdenke35745b2004-04-18 23:32:11 +0000207 return dramsize + dramsize2;
208}
209
210#elif defined(CONFIG_MGT5100)
211
212long int initdram (int board_type)
213{
214 ulong dramsize = 0;
215#ifndef CFG_RAMBOOT
216 ulong test1, test2;
wdenk5cf91d62004-04-23 20:32:05 +0000217
wdenke35745b2004-04-18 23:32:11 +0000218 /* setup and enable SDRAM chip selects */
219 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
220 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
221 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
222 __asm__ volatile ("sync");
223
224 /* setup config registers */
225 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
226 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
227
228 /* address select register */
229 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
230 __asm__ volatile ("sync");
231
232 /* find RAM size */
233 sdram_start(0);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200234 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
wdenke35745b2004-04-18 23:32:11 +0000235 sdram_start(1);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200236 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
wdenke35745b2004-04-18 23:32:11 +0000237 if (test1 > test2) {
238 sdram_start(0);
239 dramsize = test1;
240 } else {
241 dramsize = test2;
242 }
243
244 /* set SDRAM end address according to size */
245 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
wdenk5cf91d62004-04-23 20:32:05 +0000246
wdenke35745b2004-04-18 23:32:11 +0000247#else /* CFG_RAMBOOT */
248
249 /* Retrieve amount of SDRAM available */
250 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
251
252#endif /* CFG_RAMBOOT */
253
wdenke0ac62d2003-08-17 18:55:18 +0000254 return dramsize;
wdenk945af8d2003-07-16 21:53:01 +0000255}
256
wdenke35745b2004-04-18 23:32:11 +0000257#else
258#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
259#endif
260
wdenk945af8d2003-07-16 21:53:01 +0000261int checkboard (void)
262{
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100263#if defined (CONFIG_LITE5200B)
264 puts ("Board: Freescale Lite5200B\n");
265#elif defined(CONFIG_MPC5200)
wdenk945af8d2003-07-16 21:53:01 +0000266 puts ("Board: Motorola MPC5200 (IceCube)\n");
267#elif defined(CONFIG_MGT5100)
268 puts ("Board: Motorola MGT5100 (IceCube)\n");
269#endif
270 return 0;
271}
272
273void flash_preinit(void)
274{
275 /*
276 * Now, when we are in RAM, enable flash write
277 * access for detection process.
278 * Note that CS_BOOT cannot be cleared when
279 * executing in flash.
280 */
281#if defined(CONFIG_MGT5100)
282 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
283 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
284#endif
285 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
286}
wdenk96e48cf2003-08-05 18:22:44 +0000287
wdenk7152b1d2003-09-05 23:19:14 +0000288void flash_afterinit(ulong size)
289{
290 if (size == 0x800000) { /* adjust mapping */
wdenk42d1f032003-10-15 23:53:47 +0000291 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
wdenk7152b1d2003-09-05 23:19:14 +0000292 START_REG(CFG_BOOTCS_START | size);
wdenk42d1f032003-10-15 23:53:47 +0000293 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
wdenk7152b1d2003-09-05 23:19:14 +0000294 STOP_REG(CFG_BOOTCS_START | size, size);
295 }
296}
297
wdenk96e48cf2003-08-05 18:22:44 +0000298#ifdef CONFIG_PCI
299static struct pci_controller hose;
300
301extern void pci_mpc5xxx_init(struct pci_controller *);
302
303void pci_init_board(void)
304{
305 pci_mpc5xxx_init(&hose);
306}
307#endif
wdenkc3f9d492004-03-14 00:59:59 +0000308
309#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
310
wdenkc3f9d492004-03-14 00:59:59 +0000311void init_ide_reset (void)
312{
wdenk4d13cba2004-03-14 14:09:05 +0000313 debug ("init_ide_reset\n");
wdenk42dfe7a2004-03-14 22:25:36 +0000314
wdenkc3f9d492004-03-14 00:59:59 +0000315 /* Configure PSC1_4 as GPIO output for ATA reset */
wdenkc3f9d492004-03-14 00:59:59 +0000316 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
wdenk4d13cba2004-03-14 14:09:05 +0000317 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
wdenk64f70be2004-09-28 20:34:50 +0000318 /* Deassert reset */
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100319 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
wdenkc3f9d492004-03-14 00:59:59 +0000320}
321
322void ide_set_reset (int idereset)
323{
wdenk4d13cba2004-03-14 14:09:05 +0000324 debug ("ide_reset(%d)\n", idereset);
325
wdenkc3f9d492004-03-14 00:59:59 +0000326 if (idereset) {
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100327 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
wdenk64f70be2004-09-28 20:34:50 +0000328 /* Make a delay. MPC5200 spec says 25 usec min */
329 udelay(500000);
wdenkc3f9d492004-03-14 00:59:59 +0000330 } else {
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100331 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
wdenkc3f9d492004-03-14 00:59:59 +0000332 }
333}
334#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */