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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / ddd104f1ed655eda50c06ba636237a83ed943f34 / . / cpu / mcf532x / start.S
blob: acd34941a9b8333205c6ec42204829322fc714ac [file] [log] [blame]
TsiChung Liew8e585f02007-06-18 13:50:13 -0500[diff] [blame]1/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <config.h>
25#include "version.h"
26
27#ifndef CONFIG_IDENT_STRING
28#define CONFIG_IDENT_STRING ""
29#endif
30
31#define _START _start
32#define _FAULT _fault
33
TsiChung Liew8e585f02007-06-18 13:50:13 -0500[diff] [blame]34#define SAVE_ALL \
35 move.w #0x2700,%sr; /* disable intrs */ \
36 subl #60,%sp; /* space for 15 regs */ \
37 moveml %d0-%d7/%a0-%a6,%sp@;
38
39#define RESTORE_ALL \
40 moveml %sp@,%d0-%d7/%a0-%a6; \
41 addl #60,%sp; /* space for 15 regs */ \
42 rte;
43
TsiChung Liew8e585f02007-06-18 13:50:13 -0500[diff] [blame]44.text
45/*
46 * Vector table. This is used for initial platform startup.
47 * These vectors are to catch any un-intended traps.
48 */
49_vectors:
50
TsiChungLiewddd104f2007-07-05 23:06:55 -0500[diff] [blame^]51INITSP: .long 0x00000000 /* Initial SP */
52INITPC: .long _START /* Initial PC */
53vector02: .long _FAULT /* Access Error */
54vector03: .long _FAULT /* Address Error */
55vector04: .long _FAULT /* Illegal Instruction */
56vector05: .long _FAULT /* Reserved */
57vector06: .long _FAULT /* Reserved */
58vector07: .long _FAULT /* Reserved */
59vector08: .long _FAULT /* Privilege Violation */
60vector09: .long _FAULT /* Trace */
61vector0A: .long _FAULT /* Unimplemented A-Line */
62vector0B: .long _FAULT /* Unimplemented F-Line */
63vector0C: .long _FAULT /* Debug Interrupt */
64vector0D: .long _FAULT /* Reserved */
65vector0E: .long _FAULT /* Format Error */
66vector0F: .long _FAULT /* Unitialized Int. */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500[diff] [blame]67
TsiChungLiewddd104f2007-07-05 23:06:55 -0500[diff] [blame^]68/* Reserved */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500[diff] [blame]69vector10_17:
70.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
71
TsiChungLiewddd104f2007-07-05 23:06:55 -0500[diff] [blame^]72vector18: .long _FAULT /* Spurious Interrupt */
73vector19: .long _FAULT /* Autovector Level 1 */
74vector1A: .long _FAULT /* Autovector Level 2 */
75vector1B: .long _FAULT /* Autovector Level 3 */
76vector1C: .long _FAULT /* Autovector Level 4 */
77vector1D: .long _FAULT /* Autovector Level 5 */
78vector1E: .long _FAULT /* Autovector Level 6 */
79vector1F: .long _FAULT /* Autovector Level 7 */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500[diff] [blame]80
81/* TRAP #0 - #15 */
82vector20_2F:
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
85
86/* Reserved */
87vector30_3F:
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90
91vector64_127:
92.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
93.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
94.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
95.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
96.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
97.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
100
101vector128_191:
102.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
103.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
104.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
105.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
106.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
107.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
108.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
109.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
110
111vector192_255:
112.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
113.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
114.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
115.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
116.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
117.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
118.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
119.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
120
121 .text
122
123 .globl _start
124_start:
125 nop
126 nop
TsiChungLiewddd104f2007-07-05 23:06:55 -0500[diff] [blame^]127 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500[diff] [blame]128
TsiChungLiewddd104f2007-07-05 23:06:55 -0500[diff] [blame^]129 /* Set vector base register at the beginning of the Flash */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500[diff] [blame]130 move.l #CFG_FLASH_BASE, %d0
131 movec %d0, %VBR
132
133 move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
134 movec %d0, %RAMBAR0
135
136 /* invalidate and disable cache */
137 move.l #0x01000000, %d0 /* Invalidate cache cmd */
138 movec %d0, %CACR /* Invalidate cache */
139 move.l #0, %d0
140 movec %d0, %ACR0
141 movec %d0, %ACR1
142
143 /* initialize general use internal ram */
144 move.l #0, %d0
145 move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
146 move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a2
147 move.l %d0, (%a1)
148 move.l %d0, (%a2)
149
TsiChungLiewddd104f2007-07-05 23:06:55 -0500[diff] [blame^]150 /* set stackpointer to end of internal ram to get some stackspace for the
151 first c-code */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500[diff] [blame]152 move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
153 clr.l %sp@-
154
TsiChungLiewddd104f2007-07-05 23:06:55 -0500[diff] [blame^]155 move.l #__got_start, %a5 /* put relocation table address to a5 */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500[diff] [blame]156
TsiChungLiewddd104f2007-07-05 23:06:55 -0500[diff] [blame^]157 bsr cpu_init_f /* run low-level CPU init code (from flash) */
158 bsr board_init_f /* run low-level board init code (from flash) */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500[diff] [blame]159
160 /* board_init_f() does not return */
161
162/*------------------------------------------------------------------------------*/
163
164/*
165 * void relocate_code (addr_sp, gd, addr_moni)
166 *
167 * This "function" does not return, instead it continues in RAM
168 * after relocating the monitor code.
169 *
170 * r3 = dest
171 * r4 = src
172 * r5 = length in bytes
173 * r6 = cachelinesize
174 */
175 .globl relocate_code
176relocate_code:
177 link.w %a6,#0
178 move.l 8(%a6), %sp /* set new stack pointer */
179
180 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
181 move.l 16(%a6), %a0 /* Save copy of Destination Address */
182
183 move.l #CFG_MONITOR_BASE, %a1
184 move.l #__init_end, %a2
185 move.l %a0, %a3
186
187 /* copy the code to RAM */
1881:
189 move.l (%a1)+, (%a3)+
190 cmp.l %a1,%a2
191 bgt.s 1b
192
193/*
194 * We are done. Do not return, instead branch to second part of board
195 * initialization, now running from RAM.
196 */
197 move.l %a0, %a1
198 add.l #(in_ram - CFG_MONITOR_BASE), %a1
199 jmp (%a1)
200
201in_ram:
202
203clear_bss:
204 /*
205 * Now clear BSS segment
206 */
207 move.l %a0, %a1
208 add.l #(_sbss - CFG_MONITOR_BASE),%a1
209 move.l %a0, %d1
210 add.l #(_ebss - CFG_MONITOR_BASE),%d1
2116:
212 clr.l (%a1)+
213 cmp.l %a1,%d1
214 bgt.s 6b
215
216 /*
217 * fix got table in RAM
218 */
219 move.l %a0, %a1
220 add.l #(__got_start - CFG_MONITOR_BASE),%a1
221 move.l %a1,%a5 /* * fix got pointer register a5 */
222
223 move.l %a0, %a2
224 add.l #(__got_end - CFG_MONITOR_BASE),%a2
225
2267:
227 move.l (%a1),%d1
228 sub.l #_start,%d1
229 add.l %a0,%d1
230 move.l %d1,(%a1)+
231 cmp.l %a2, %a1
232 bne 7b
233
234 /* calculate relative jump to board_init_r in ram */
235 move.l %a0, %a1
236 add.l #(board_init_r - CFG_MONITOR_BASE), %a1
237
238 /* set parameters for board_init_r */
239 move.l %a0,-(%sp) /* dest_addr */
240 move.l %d0,-(%sp) /* gd */
241 jsr (%a1)
242
243/*------------------------------------------------------------------------------*/
244/* exception code */
245 .globl _fault
246_fault:
247 jmp _fault
248 .globl _exc_handler
249
250_exc_handler:
251 SAVE_ALL
252 movel %sp,%sp@-
253 bsr exc_handler
254 addql #4,%sp
255 RESTORE_ALL
256
257 .globl _int_handler
258_int_handler:
259 SAVE_ALL
260 movel %sp,%sp@-
261 bsr int_handler
262 addql #4,%sp
263 RESTORE_ALL
264
265/*------------------------------------------------------------------------------*/
266/* cache functions */
267 .globl icache_enable
268icache_enable:
269 move.l #0x01000000, %d0 /* Invalidate cache cmd */
270 movec %d0, %CACR /* Invalidate cache */
TsiChungLiewddd104f2007-07-05 23:06:55 -0500[diff] [blame^]271 move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500[diff] [blame]272 movec %d0, %ACR0 /* Enable cache */
TsiChungLiewddd104f2007-07-05 23:06:55 -0500[diff] [blame^]273 move.l #(CFG_CS0_BASE + 0x0000), %d0 /* Setup cache mask */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500[diff] [blame]274 movec %d0, %ACR1 /* Enable cache */
275
TsiChungLiewddd104f2007-07-05 23:06:55 -0500[diff] [blame^]276 move.l #0x80000200, %d0 /* Setup cache mask */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500[diff] [blame]277 movec %d0, %CACR /* Enable cache */
TsiChungLiewddd104f2007-07-05 23:06:55 -0500[diff] [blame^]278 nop
TsiChung Liew8e585f02007-06-18 13:50:13 -0500[diff] [blame]279
280 move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
281 moveq #1, %d0
282 move.l %d0, (%a1)
283 rts
284
285 .globl icache_disable
286icache_disable:
287 move.l #0x00000100, %d0 /* Setup cache mask */
288 movec %d0, %CACR /* Enable cache */
289 clr.l %d0 /* Setup cache mask */
290 movec %d0, %ACR0 /* Enable cache */
291 movec %d0, %ACR1 /* Enable cache */
292
293 move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
294 moveq #0, %d0
295 move.l %d0, (%a1)
296 rts
297
298 .globl icache_status
299icache_status:
300 move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
301 move.l (%a1), %d0
302 rts
303
304 .globl icache_invalid
305icache_invalid:
TsiChungLiewddd104f2007-07-05 23:06:55 -0500[diff] [blame^]306 move.l #0x01000000, %d0 /* Setup cache mask */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500[diff] [blame]307 movec %d0, %CACR /* Enable cache */
308 rts
309
310 .globl dcache_enable
311dcache_enable:
312 move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
313 moveq #1, %d0
314 move.l %d0, (%a1)
315 rts
316
317 /* No dcache, just a dummy function */
318 .globl dcache_disable
319dcache_disable:
320 move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
321 moveq #0, %d0
322 move.l %d0, (%a1)
323 rts
324
325 .globl dcache_status
326dcache_status:
327 move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-4), %a1
328 move.l (%a1), %d0
329 rts
330
331/*------------------------------------------------------------------------------*/
332
333 .globl version_string
334version_string:
335 .ascii U_BOOT_VERSION
336 .ascii " (", __DATE__, " - ", __TIME__, ")"
337 .ascii CONFIG_IDENT_STRING, "\0"