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wdenk42d1f032003-10-15 23:53:47 +00001/*
2 * MPC85xx Internal Memory Map
3 *
4 * Copyright(c) 2002,2003 Motorola Inc.
5 * Xianghua Xiao (x.xiao@motorola.com)
6 *
7 */
8
9#ifndef __IMMAP_85xx__
10#define __IMMAP_85xx__
11
Jon Loeligerde1d0a62005-08-01 13:20:47 -050012/*
13 * Local-Access Registers and ECM Registers(0x0000-0x2000)
14 */
wdenk42d1f032003-10-15 23:53:47 +000015typedef struct ccsr_local_ecm {
16 uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
17 char res1[4];
18 uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
19 char res2[4];
20 uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
21 char res3[12];
22 uint bptr; /* 0x20 - Boot Page Translation Register */
23 char res4[3044];
24 uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
25 char res5[4];
26 uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
27 char res6[20];
28 uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
29 char res7[4];
30 uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
31 char res8[20];
32 uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
33 char res9[4];
34 uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
35 char res10[20];
36 uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */
37 char res11[4];
38 uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */
39 char res12[20];
40 uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */
41 char res13[4];
42 uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */
43 char res14[20];
44 uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */
45 char res15[4];
46 uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */
47 char res16[20];
48 uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */
49 char res17[4];
50 uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */
51 char res18[20];
52 uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
53 char res19[4];
54 uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
55 char res20[780];
56 uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */
57 char res21[12];
58 uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */
59 char res22[3564];
60 uint eedr; /* 0x1e00 - ECM Error Detect Register */
61 char res23[4];
62 uint eeer; /* 0x1e08 - ECM Error Enable Register */
63 uint eeatr; /* 0x1e0c - ECM Error Attributes Capture Register */
64 uint eeadr; /* 0x1e10 - ECM Error Address Capture Register */
65 char res24[492];
66} ccsr_local_ecm_t;
67
Jon Loeligerde1d0a62005-08-01 13:20:47 -050068/*
69 * DDR memory controller registers(0x2000-0x3000)
70 */
wdenk42d1f032003-10-15 23:53:47 +000071typedef struct ccsr_ddr {
72 uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
73 char res1[4];
74 uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */
75 char res2[4];
76 uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */
77 char res3[4];
78 uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */
79 char res4[100];
80 uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */
81 uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
82 uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
83 uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050084 char res5[112];
85 uint ext_refrec; /* 0x2100 - DDR SDRAM Extended Refresh Recovery */
86 uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
wdenk42d1f032003-10-15 23:53:47 +000087 uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
88 uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
89 uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050090 uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
wdenk42d1f032003-10-15 23:53:47 +000091 uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050092 uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2*/
93 uint sdram_md_cntl; /* 0x2120 - DDR SDRAM Mode Control */
wdenk42d1f032003-10-15 23:53:47 +000094 uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050095 uint sdram_data_init; /* 0x2128 - DDR SDRAM Data initialization */
96 char res6[4];
wdenk547b4cb2004-06-09 00:51:50 +000097 uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050098 char res7[20];
99 uint init_address; /* 0x2148 - DDR training initialization address */
100 uint init_ext_address; /* 0x214C - DDR training initialization extended address */
101 char res8_1[2728];
102 uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
103 uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
104 char res8_2[512];
wdenk42d1f032003-10-15 23:53:47 +0000105 uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
106 uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
107 uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
108 char res9[20];
109 uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */
110 uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */
111 uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */
112 char res10[20];
113 uint err_detect; /* 0x2e40 - DDR Memory Error Detect */
114 uint err_disable; /* 0x2e44 - DDR Memory Error Disable */
115 uint err_int_en; /* 0x2e48 - DDR */
116 uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */
117 uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */
118 uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */
119 uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
120 char res11[164];
121 uint debug_1; /* 0x2f00 */
122 uint debug_2;
123 uint debug_3;
124 uint debug_4;
125 char res12[240];
126} ccsr_ddr_t;
127
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500128/*
129 * I2C Registers(0x3000-0x4000)
130 */
wdenk42d1f032003-10-15 23:53:47 +0000131typedef struct ccsr_i2c {
132 u_char i2cadr; /* 0x3000 - I2C Address Register */
133#define MPC85xx_I2CADR_MASK 0xFE
134 char res1[3];
135 u_char i2cfdr; /* 0x3004 - I2C Frequency Divider Register */
136#define MPC85xx_I2CFDR_MASK 0x3F
137 char res2[3];
138 u_char i2ccr; /* 0x3008 - I2C Control Register */
139#define MPC85xx_I2CCR_MEN 0x80
140#define MPC85xx_I2CCR_MIEN 0x40
141#define MPC85xx_I2CCR_MSTA 0x20
142#define MPC85xx_I2CCR_MTX 0x10
143#define MPC85xx_I2CCR_TXAK 0x08
144#define MPC85xx_I2CCR_RSTA 0x04
145#define MPC85xx_I2CCR_BCST 0x01
146 char res3[3];
147 u_char i2csr; /* 0x300c - I2C Status Register */
148#define MPC85xx_I2CSR_MCF 0x80
149#define MPC85xx_I2CSR_MAAS 0x40
150#define MPC85xx_I2CSR_MBB 0x20
151#define MPC85xx_I2CSR_MAL 0x10
152#define MPC85xx_I2CSR_BCSTM 0x08
153#define MPC85xx_I2CSR_SRW 0x04
154#define MPC85xx_I2CSR_MIF 0x02
155#define MPC85xx_I2CSR_RXAK 0x01
156 char res4[3];
157 u_char i2cdr; /* 0x3010 - I2C Data Register */
158#define MPC85xx_I2CDR_DATA 0xFF
159 char res5[3];
160 u_char i2cdfsrr; /* 0x3014 - I2C Digital Filtering Sampling Rate Register */
161#define MPC85xx_I2CDFSRR 0x3F
162 char res6[4075];
163} ccsr_i2c_t;
164
wdenk03f5c552004-10-10 21:21:55 +0000165#if defined(CONFIG_MPC8540) \
166 || defined(CONFIG_MPC8541) \
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500167 || defined(CONFIG_MPC8548) \
wdenk03f5c552004-10-10 21:21:55 +0000168 || defined(CONFIG_MPC8555)
wdenk42d1f032003-10-15 23:53:47 +0000169/* DUART Registers(0x4000-0x5000) */
170typedef struct ccsr_duart {
171 char res1[1280];
172 u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
173 u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
174 u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
175 u_char ulcr1; /* 0x4503 - UART1 Line Control Register */
176 u_char umcr1; /* 0x4504 - UART1 Modem Control Register */
177 u_char ulsr1; /* 0x4505 - UART1 Line Status Register */
178 u_char umsr1; /* 0x4506 - UART1 Modem Status Register */
179 u_char uscr1; /* 0x4507 - UART1 Scratch Register */
180 char res2[8];
181 u_char udsr1; /* 0x4510 - UART1 DMA Status Register */
182 char res3[239];
183 u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
184 u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
185 u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
186 u_char ulcr2; /* 0x4603 - UART2 Line Control Register */
187 u_char umcr2; /* 0x4604 - UART2 Modem Control Register */
188 u_char ulsr2; /* 0x4605 - UART2 Line Status Register */
189 u_char umsr2; /* 0x4606 - UART2 Modem Status Register */
190 u_char uscr2; /* 0x4607 - UART2 Scratch Register */
191 char res4[8];
192 u_char udsr2; /* 0x4610 - UART2 DMA Status Register */
193 char res5[2543];
194} ccsr_duart_t;
195#else /* MPC8560 uses UART on its CPM */
196typedef struct ccsr_duart {
197 char res[4096];
198} ccsr_duart_t;
199#endif
200
201/* Local Bus Controller Registers(0x5000-0x6000) */
202/* Omitting OCeaN(0x6000) and Reserved(0x7000) block */
203
204typedef struct ccsr_lbc {
205 uint br0; /* 0x5000 - LBC Base Register 0 */
206 uint or0; /* 0x5004 - LBC Options Register 0 */
207 uint br1; /* 0x5008 - LBC Base Register 1 */
208 uint or1; /* 0x500c - LBC Options Register 1 */
209 uint br2; /* 0x5010 - LBC Base Register 2 */
210 uint or2; /* 0x5014 - LBC Options Register 2 */
211 uint br3; /* 0x5018 - LBC Base Register 3 */
212 uint or3; /* 0x501c - LBC Options Register 3 */
213 uint br4; /* 0x5020 - LBC Base Register 4 */
214 uint or4; /* 0x5024 - LBC Options Register 4 */
215 uint br5; /* 0x5028 - LBC Base Register 5 */
216 uint or5; /* 0x502c - LBC Options Register 5 */
217 uint br6; /* 0x5030 - LBC Base Register 6 */
218 uint or6; /* 0x5034 - LBC Options Register 6 */
219 uint br7; /* 0x5038 - LBC Base Register 7 */
220 uint or7; /* 0x503c - LBC Options Register 7 */
221 char res1[40];
222 uint mar; /* 0x5068 - LBC UPM Address Register */
223 char res2[4];
224 uint mamr; /* 0x5070 - LBC UPMA Mode Register */
225 uint mbmr; /* 0x5074 - LBC UPMB Mode Register */
226 uint mcmr; /* 0x5078 - LBC UPMC Mode Register */
227 char res3[8];
228 uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
229 uint mdr; /* 0x5088 - LBC UPM Data Register */
230 char res4[8];
231 uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */
232 char res5[8];
233 uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */
234 uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */
235 char res6[8];
236 uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */
237 uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */
238 uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */
239 uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */
240 uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */
241 char res7[12];
242 uint lbcr; /* 0x50d0 - LBC Configuration Register */
243 uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
244 char res8[12072];
245} ccsr_lbc_t;
246
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500247/*
248 * PCI Registers(0x8000-0x9000)
249 * Omitting Reserved(0x9000-0x2_0000)
250 */
wdenk42d1f032003-10-15 23:53:47 +0000251typedef struct ccsr_pcix {
252 uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */
253 uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */
254 uint int_ack; /* 0x8008 - PCIX Interrupt Acknowledge Register */
255 char res1[3060];
256 uint potar0; /* 0x8c00 - PCIX Outbound Transaction Address Register 0 */
257 uint potear0; /* 0x8c04 - PCIX Outbound Translation Extended Address Register 0 */
258 uint powbar0; /* 0x8c08 - PCIX Outbound Window Base Address Register 0 */
259 uint powbear0; /* 0x8c0c - PCIX Outbound Window Base Extended Address Register 0 */
260 uint powar0; /* 0x8c10 - PCIX Outbound Window Attributes Register 0 */
261 char res2[12];
262 uint potar1; /* 0x8c20 - PCIX Outbound Transaction Address Register 1 */
263 uint potear1; /* 0x8c24 - PCIX Outbound Translation Extended Address Register 1 */
264 uint powbar1; /* 0x8c28 - PCIX Outbound Window Base Address Register 1 */
265 uint powbear1; /* 0x8c2c - PCIX Outbound Window Base Extended Address Register 1 */
266 uint powar1; /* 0x8c30 - PCIX Outbound Window Attributes Register 1 */
267 char res3[12];
268 uint potar2; /* 0x8c40 - PCIX Outbound Transaction Address Register 2 */
269 uint potear2; /* 0x8c44 - PCIX Outbound Translation Extended Address Register 2 */
270 uint powbar2; /* 0x8c48 - PCIX Outbound Window Base Address Register 2 */
271 uint powbear2; /* 0x8c4c - PCIX Outbound Window Base Extended Address Register 2 */
272 uint powar2; /* 0x8c50 - PCIX Outbound Window Attributes Register 2 */
273 char res4[12];
274 uint potar3; /* 0x8c60 - PCIX Outbound Transaction Address Register 3 */
275 uint potear3; /* 0x8c64 - PCIX Outbound Translation Extended Address Register 3 */
276 uint powbar3; /* 0x8c68 - PCIX Outbound Window Base Address Register 3 */
277 uint powbear3; /* 0x8c6c - PCIX Outbound Window Base Extended Address Register 3 */
278 uint powar3; /* 0x8c70 - PCIX Outbound Window Attributes Register 3 */
279 char res5[12];
280 uint potar4; /* 0x8c80 - PCIX Outbound Transaction Address Register 4 */
281 uint potear4; /* 0x8c84 - PCIX Outbound Translation Extended Address Register 4 */
282 uint powbar4; /* 0x8c88 - PCIX Outbound Window Base Address Register 4 */
283 uint powbear4; /* 0x8c8c - PCIX Outbound Window Base Extended Address Register 4 */
284 uint powar4; /* 0x8c90 - PCIX Outbound Window Attributes Register 4 */
285 char res6[268];
286 uint pitar3; /* 0x8da0 - PCIX Inbound Translation Address Register 3 */
287 uint pitear3; /* 0x8da4 - PCIX Inbound Translation Extended Address Register 3 */
288 uint piwbar3; /* 0x8da8 - PCIX Inbound Window Base Address Register 3 */
289 uint piwbear3; /* 0x8dac - PCIX Inbound Window Base Extended Address Register 3 */
290 uint piwar3; /* 0x8db0 - PCIX Inbound Window Attributes Register 3 */
291 char res7[12];
292 uint pitar2; /* 0x8dc0 - PCIX Inbound Translation Address Register 2 */
293 uint pitear2; /* 0x8dc4 - PCIX Inbound Translation Extended Address Register 2 */
294 uint piwbar2; /* 0x8dc8 - PCIX Inbound Window Base Address Register 2 */
295 uint piwbear2; /* 0x8dcc - PCIX Inbound Window Base Extended Address Register 2 */
296 uint piwar2; /* 0x8dd0 - PCIX Inbound Window Attributes Register 2 */
297 char res8[12];
298 uint pitar1; /* 0x8de0 - PCIX Inbound Translation Address Register 1 */
299 uint pitear1; /* 0x8de4 - PCIX Inbound Translation Extended Address Register 1 */
300 uint piwbar1; /* 0x8de8 - PCIX Inbound Window Base Address Register 1 */
301 char res9[4];
302 uint piwar1; /* 0x8df0 - PCIX Inbound Window Attributes Register 1 */
303 char res10[12];
304 uint pedr; /* 0x8e00 - PCIX Error Detect Register */
305 uint pecdr; /* 0x8e04 - PCIX Error Capture Disable Register */
306 uint peer; /* 0x8e08 - PCIX Error Enable Register */
307 uint peattrcr; /* 0x8e0c - PCIX Error Attributes Capture Register */
308 uint peaddrcr; /* 0x8e10 - PCIX Error Address Capture Register */
309 uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */
310 uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */
311 uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */
312 char res11[94688];
313} ccsr_pcix_t;
314
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500315/*
316 * L2 Cache Registers(0x2_0000-0x2_1000)
317 */
wdenk42d1f032003-10-15 23:53:47 +0000318typedef struct ccsr_l2cache {
319 uint l2ctl; /* 0x20000 - L2 configuration register 0 */
320 char res1[12];
321 uint l2cewar0; /* 0x20010 - L2 cache external write address register 0 */
322 char res2[4];
323 uint l2cewcr0; /* 0x20018 - L2 cache external write control register 0 */
324 char res3[4];
325 uint l2cewar1; /* 0x20020 - L2 cache external write address register 1 */
326 char res4[4];
327 uint l2cewcr1; /* 0x20028 - L2 cache external write control register 1 */
328 char res5[4];
329 uint l2cewar2; /* 0x20030 - L2 cache external write address register 2 */
330 char res6[4];
331 uint l2cewcr2; /* 0x20038 - L2 cache external write control register 2 */
332 char res7[4];
333 uint l2cewar3; /* 0x20040 - L2 cache external write address register 3 */
334 char res8[4];
335 uint l2cewcr3; /* 0x20048 - L2 cache external write control register 3 */
336 char res9[180];
337 uint l2srbar0; /* 0x20100 - L2 memory-mapped SRAM base address register 0 */
338 char res10[4];
339 uint l2srbar1; /* 0x20108 - L2 memory-mapped SRAM base address register 1 */
340 char res11[3316];
341 uint l2errinjhi; /* 0x20e00 - L2 error injection mask high register */
342 uint l2errinjlo; /* 0x20e04 - L2 error injection mask low register */
343 uint l2errinjctl; /* 0x20e08 - L2 error injection tag/ECC control register */
344 char res12[20];
345 uint l2captdatahi; /* 0x20e20 - L2 error data high capture register */
346 uint l2captdatalo; /* 0x20e24 - L2 error data low capture register */
347 uint l2captecc; /* 0x20e28 - L2 error ECC capture register */
348 char res13[20];
349 uint l2errdet; /* 0x20e40 - L2 error detect register */
350 uint l2errdis; /* 0x20e44 - L2 error disable register */
351 uint l2errinten; /* 0x20e48 - L2 error interrupt enable register */
352 uint l2errattr; /* 0x20e4c - L2 error attributes capture register */
353 uint l2erraddr; /* 0x20e50 - L2 error address capture register */
354 char res14[4];
355 uint l2errctl; /* 0x20e58 - L2 error control register */
356 char res15[420];
357} ccsr_l2cache_t;
358
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500359/*
360 * DMA Registers(0x2_1000-0x2_2000)
361 */
wdenk42d1f032003-10-15 23:53:47 +0000362typedef struct ccsr_dma {
363 char res1[256];
364 uint mr0; /* 0x21100 - DMA 0 Mode Register */
365 uint sr0; /* 0x21104 - DMA 0 Status Register */
366 char res2[4];
367 uint clndar0; /* 0x2110c - DMA 0 Current Link Descriptor Address Register */
368 uint satr0; /* 0x21110 - DMA 0 Source Attributes Register */
369 uint sar0; /* 0x21114 - DMA 0 Source Address Register */
370 uint datr0; /* 0x21118 - DMA 0 Destination Attributes Register */
371 uint dar0; /* 0x2111c - DMA 0 Destination Address Register */
372 uint bcr0; /* 0x21120 - DMA 0 Byte Count Register */
373 char res3[4];
374 uint nlndar0; /* 0x21128 - DMA 0 Next Link Descriptor Address Register */
375 char res4[8];
376 uint clabdar0; /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
377 char res5[4];
378 uint nlsdar0; /* 0x2113c - DMA 0 Next List Descriptor Address Register */
379 uint ssr0; /* 0x21140 - DMA 0 Source Stride Register */
380 uint dsr0; /* 0x21144 - DMA 0 Destination Stride Register */
381 char res6[56];
382 uint mr1; /* 0x21180 - DMA 1 Mode Register */
383 uint sr1; /* 0x21184 - DMA 1 Status Register */
384 char res7[4];
385 uint clndar1; /* 0x2118c - DMA 1 Current Link Descriptor Address Register */
386 uint satr1; /* 0x21190 - DMA 1 Source Attributes Register */
387 uint sar1; /* 0x21194 - DMA 1 Source Address Register */
388 uint datr1; /* 0x21198 - DMA 1 Destination Attributes Register */
389 uint dar1; /* 0x2119c - DMA 1 Destination Address Register */
390 uint bcr1; /* 0x211a0 - DMA 1 Byte Count Register */
391 char res8[4];
392 uint nlndar1; /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
393 char res9[8];
394 uint clabdar1; /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
395 char res10[4];
396 uint nlsdar1; /* 0x211bc - DMA 1 Next List Descriptor Address Register */
397 uint ssr1; /* 0x211c0 - DMA 1 Source Stride Register */
398 uint dsr1; /* 0x211c4 - DMA 1 Destination Stride Register */
399 char res11[56];
400 uint mr2; /* 0x21200 - DMA 2 Mode Register */
401 uint sr2; /* 0x21204 - DMA 2 Status Register */
402 char res12[4];
403 uint clndar2; /* 0x2120c - DMA 2 Current Link Descriptor Address Register */
404 uint satr2; /* 0x21210 - DMA 2 Source Attributes Register */
405 uint sar2; /* 0x21214 - DMA 2 Source Address Register */
406 uint datr2; /* 0x21218 - DMA 2 Destination Attributes Register */
407 uint dar2; /* 0x2121c - DMA 2 Destination Address Register */
408 uint bcr2; /* 0x21220 - DMA 2 Byte Count Register */
409 char res13[4];
410 uint nlndar2; /* 0x21228 - DMA 2 Next Link Descriptor Address Register */
411 char res14[8];
412 uint clabdar2; /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
413 char res15[4];
414 uint nlsdar2; /* 0x2123c - DMA 2 Next List Descriptor Address Register */
415 uint ssr2; /* 0x21240 - DMA 2 Source Stride Register */
416 uint dsr2; /* 0x21244 - DMA 2 Destination Stride Register */
417 char res16[56];
418 uint mr3; /* 0x21280 - DMA 3 Mode Register */
419 uint sr3; /* 0x21284 - DMA 3 Status Register */
420 char res17[4];
421 uint clndar3; /* 0x2128c - DMA 3 Current Link Descriptor Address Register */
422 uint satr3; /* 0x21290 - DMA 3 Source Attributes Register */
423 uint sar3; /* 0x21294 - DMA 3 Source Address Register */
424 uint datr3; /* 0x21298 - DMA 3 Destination Attributes Register */
425 uint dar3; /* 0x2129c - DMA 3 Destination Address Register */
426 uint bcr3; /* 0x212a0 - DMA 3 Byte Count Register */
427 char res18[4];
428 uint nlndar3; /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
429 char res19[8];
430 uint clabdar3; /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
431 char res20[4];
432 uint nlsdar3; /* 0x212bc - DMA 3 Next List Descriptor Address Register */
433 uint ssr3; /* 0x212c0 - DMA 3 Source Stride Register */
434 uint dsr3; /* 0x212c4 - DMA 3 Destination Stride Register */
435 char res21[56];
436 uint dgsr; /* 0x21300 - DMA General Status Register */
437 char res22[11516];
438} ccsr_dma_t;
439
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500440/*
441 * tsec1 tsec2: 24000-26000
442 */
wdenk42d1f032003-10-15 23:53:47 +0000443typedef struct ccsr_tsec {
444 char res1[16];
445 uint ievent; /* 0x24010 - Interrupt Event Register */
446 uint imask; /* 0x24014 - Interrupt Mask Register */
447 uint edis; /* 0x24018 - Error Disabled Register */
448 char res2[4];
449 uint ecntrl; /* 0x24020 - Ethernet Control Register */
450 uint minflr; /* 0x24024 - Minimum Frame Length Register */
451 uint ptv; /* 0x24028 - Pause Time Value Register */
452 uint dmactrl; /* 0x2402c - DMA Control Register */
453 uint tbipa; /* 0x24030 - TBI PHY Address Register */
454 char res3[88];
455 uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
456 char res4[8];
457 uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
458 uint fifo_tx_starve_shutoff; /* 0x2409c - FIFO transmit starve shutoff register */
459 char res5[96];
460 uint tctrl; /* 0x24100 - Transmit Control Register */
461 uint tstat; /* 0x24104 - Transmit Status Register */
462 char res6[4];
463 uint tbdlen; /* 0x2410c - Transmit Buffer Descriptor Data Length Register */
464 char res7[16];
465 uint ctbptrh; /* 0x24120 - Current Transmit Buffer Descriptor Pointer High Register */
466 uint ctbptr; /* 0x24124 - Current Transmit Buffer Descriptor Pointer Register */
467 char res8[88];
468 uint tbptrh; /* 0x24180 - Transmit Buffer Descriptor Pointer High Register */
469 uint tbptr; /* 0x24184 - Transmit Buffer Descriptor Pointer Low Register */
470 char res9[120];
471 uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
472 uint tbase; /* 0x24204 - Transmit Descriptor Base Address Register */
473 char res10[168];
474 uint ostbd; /* 0x242b0 - Out-of-Sequence Transmit Buffer Descriptor Register */
475 uint ostbdp; /* 0x242b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */
476 uint os32tbdp; /* 0x242b8 - Out-of-Sequence 32 Bytes Transmit Data Buffer Pointer Low Register */
477 uint os32iptrh; /* 0x242bc - Out-of-Sequence 32 Bytes Transmit Insert Pointer High Register */
478 uint os32iptrl; /* 0x242c0 - Out-of-Sequence 32 Bytes Transmit Insert Pointer Low Register */
479 uint os32tbdr; /* 0x242c4 - Out-of-Sequence 32 Bytes Transmit Reserved Register */
480 uint os32iil; /* 0x242c8 - Out-of-Sequence 32 Bytes Transmit Insert Index/Length Register */
481 char res11[52];
482 uint rctrl; /* 0x24300 - Receive Control Register */
483 uint rstat; /* 0x24304 - Receive Status Register */
484 char res12[4];
485 uint rbdlen; /* 0x2430c - RxBD Data Length Register */
486 char res13[16];
487 uint crbptrh; /* 0x24320 - Current Receive Buffer Descriptor Pointer High */
488 uint crbptr; /* 0x24324 - Current Receive Buffer Descriptor Pointer */
489 char res14[24];
490 uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
491 uint mrblr2r3; /* 0x24344 - Maximum Receive Buffer Length R2R3 Register */
492 char res15[56];
493 uint rbptrh; /* 0x24380 - Receive Buffer Descriptor Pointer High 0 */
494 uint rbptr; /* 0x24384 - Receive Buffer Descriptor Pointer */
495 uint rbptrh1; /* 0x24388 - Receive Buffer Descriptor Pointer High 1 */
496 uint rbptrl1; /* 0x2438c - Receive Buffer Descriptor Pointer Low 1 */
497 uint rbptrh2; /* 0x24390 - Receive Buffer Descriptor Pointer High 2 */
498 uint rbptrl2; /* 0x24394 - Receive Buffer Descriptor Pointer Low 2 */
499 uint rbptrh3; /* 0x24398 - Receive Buffer Descriptor Pointer High 3 */
500 uint rbptrl3; /* 0x2439c - Receive Buffer Descriptor Pointer Low 3 */
501 char res16[96];
502 uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
503 uint rbase; /* 0x24404 - Receive Descriptor Base Address */
504 uint rbaseh1; /* 0x24408 - Receive Descriptor Base Address High 1 */
505 uint rbasel1; /* 0x2440c - Receive Descriptor Base Address Low 1 */
506 uint rbaseh2; /* 0x24410 - Receive Descriptor Base Address High 2 */
507 uint rbasel2; /* 0x24414 - Receive Descriptor Base Address Low 2 */
508 uint rbaseh3; /* 0x24418 - Receive Descriptor Base Address High 3 */
509 uint rbasel3; /* 0x2441c - Receive Descriptor Base Address Low 3 */
510 char res17[224];
511 uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
512 uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
513 uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
514 uint hafdup; /* 0x2450c - Half Duplex Register */
515 uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
516 char res18[12];
517 uint miimcfg; /* 0x24520 - MII Management Configuration Register */
518 uint miimcom; /* 0x24524 - MII Management Command Register */
519 uint miimadd; /* 0x24528 - MII Management Address Register */
520 uint miimcon; /* 0x2452c - MII Management Control Register */
521 uint miimstat; /* 0x24530 - MII Management Status Register */
522 uint miimind; /* 0x24534 - MII Management Indicator Register */
523 char res19[4];
524 uint ifstat; /* 0x2453c - Interface Status Register */
525 uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
526 uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
527 char res20[312];
528 uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
529 uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
530 uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
531 uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
532 uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
533 uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
534 uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
535 uint rbyt; /* 0x2469c - Receive Byte Counter */
536 uint rpkt; /* 0x246a0 - Receive Packet Counter */
537 uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
538 uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
539 uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
540 uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
541 uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
542 uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
543 uint raln; /* 0x246bc - Receive Alignment Error Counter */
544 uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
545 uint rcde; /* 0x246c4 - Receive Code Error Counter */
546 uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
547 uint rund; /* 0x246cc - Receive Undersize Packet Counter */
548 uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
549 uint rfrg; /* 0x246d4 - Receive Fragments Counter */
550 uint rjbr; /* 0x246d8 - Receive Jabber Counter */
551 uint rdrp; /* 0x246dc - Receive Drop Counter */
552 uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
553 uint tpkt; /* 0x246e4 - Transmit Packet Counter */
554 uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
555 uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
556 uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
557 uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
558 uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
559 uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
560 uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
561 uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
562 uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
563 uint tncl; /* 0x2470c - Transmit Total Collision Counter */
564 char res21[4];
565 uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
566 uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
567 uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
568 uint txcf; /* 0x24720 - Transmit Control Frame Counter */
569 uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
570 uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
571 uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
572 uint car1; /* 0x24730 - Carry Register One */
573 uint car2; /* 0x24734 - Carry Register Two */
574 uint cam1; /* 0x24738 - Carry Mask Register One */
575 uint cam2; /* 0x2473c - Carry Mask Register Two */
576 char res22[192];
577 uint iaddr0; /* 0x24800 - Indivdual address register 0 */
578 uint iaddr1; /* 0x24804 - Indivdual address register 1 */
579 uint iaddr2; /* 0x24808 - Indivdual address register 2 */
580 uint iaddr3; /* 0x2480c - Indivdual address register 3 */
581 uint iaddr4; /* 0x24810 - Indivdual address register 4 */
582 uint iaddr5; /* 0x24814 - Indivdual address register 5 */
583 uint iaddr6; /* 0x24818 - Indivdual address register 6 */
584 uint iaddr7; /* 0x2481c - Indivdual address register 7 */
585 char res23[96];
586 uint gaddr0; /* 0x24880 - Global address register 0 */
587 uint gaddr1; /* 0x24884 - Global address register 1 */
588 uint gaddr2; /* 0x24888 - Global address register 2 */
589 uint gaddr3; /* 0x2488c - Global address register 3 */
590 uint gaddr4; /* 0x24890 - Global address register 4 */
591 uint gaddr5; /* 0x24894 - Global address register 5 */
592 uint gaddr6; /* 0x24898 - Global address register 6 */
593 uint gaddr7; /* 0x2489c - Global address register 7 */
594 char res24[96];
595 uint pmd0; /* 0x24900 - Pattern Match Data Register */
596 char res25[4];
597 uint pmask0; /* 0x24908 - Pattern Mask Register */
598 char res26[4];
599 uint pcntrl0; /* 0x24910 - Pattern Match Control Register */
600 char res27[4];
601 uint pattrb0; /* 0x24918 - Pattern Match Attributes Register */
602 uint pattrbeli0; /* 0x2491c - Pattern Match Attributes Extract Length and Extract Index Register */
603 uint pmd1; /* 0x24920 - Pattern Match Data Register */
604 char res28[4];
605 uint pmask1; /* 0x24928 - Pattern Mask Register */
606 char res29[4];
607 uint pcntrl1; /* 0x24930 - Pattern Match Control Register */
608 char res30[4];
609 uint pattrb1; /* 0x24938 - Pattern Match Attributes Register */
610 uint pattrbeli1; /* 0x2493c - Pattern Match Attributes Extract Length and Extract Index Register */
611 uint pmd2; /* 0x24940 - Pattern Match Data Register */
612 char res31[4];
613 uint pmask2; /* 0x24948 - Pattern Mask Register */
614 char res32[4];
615 uint pcntrl2; /* 0x24950 - Pattern Match Control Register */
616 char res33[4];
617 uint pattrb2; /* 0x24958 - Pattern Match Attributes Register */
618 uint pattrbeli2; /* 0x2495c - Pattern Match Attributes Extract Length and Extract Index Register */
619 uint pmd3; /* 0x24960 - Pattern Match Data Register */
620 char res34[4];
621 uint pmask3; /* 0x24968 - Pattern Mask Register */
622 char res35[4];
623 uint pcntrl3; /* 0x24970 - Pattern Match Control Register */
624 char res36[4];
625 uint pattrb3; /* 0x24978 - Pattern Match Attributes Register */
626 uint pattrbeli3; /* 0x2497c - Pattern Match Attributes Extract Length and Extract Index Register */
627 uint pmd4; /* 0x24980 - Pattern Match Data Register */
628 char res37[4];
629 uint pmask4; /* 0x24988 - Pattern Mask Register */
630 char res38[4];
631 uint pcntrl4; /* 0x24990 - Pattern Match Control Register */
632 char res39[4];
633 uint pattrb4; /* 0x24998 - Pattern Match Attributes Register */
634 uint pattrbeli4; /* 0x2499c - Pattern Match Attributes Extract Length and Extract Index Register */
635 uint pmd5; /* 0x249a0 - Pattern Match Data Register */
636 char res40[4];
637 uint pmask5; /* 0x249a8 - Pattern Mask Register */
638 char res41[4];
639 uint pcntrl5; /* 0x249b0 - Pattern Match Control Register */
640 char res42[4];
641 uint pattrb5; /* 0x249b8 - Pattern Match Attributes Register */
642 uint pattrbeli5; /* 0x249bc - Pattern Match Attributes Extract Length and Extract Index Register */
643 uint pmd6; /* 0x249c0 - Pattern Match Data Register */
644 char res43[4];
645 uint pmask6; /* 0x249c8 - Pattern Mask Register */
646 char res44[4];
647 uint pcntrl6; /* 0x249d0 - Pattern Match Control Register */
648 char res45[4];
649 uint pattrb6; /* 0x249d8 - Pattern Match Attributes Register */
650 uint pattrbeli6; /* 0x249dc - Pattern Match Attributes Extract Length and Extract Index Register */
651 uint pmd7; /* 0x249e0 - Pattern Match Data Register */
652 char res46[4];
653 uint pmask7; /* 0x249e8 - Pattern Mask Register */
654 char res47[4];
655 uint pcntrl7; /* 0x249f0 - Pattern Match Control Register */
656 char res48[4];
657 uint pattrb7; /* 0x249f8 - Pattern Match Attributes Register */
658 uint pattrbeli7; /* 0x249fc - Pattern Match Attributes Extract Length and Extract Index Register */
659 uint pmd8; /* 0x24a00 - Pattern Match Data Register */
660 char res49[4];
661 uint pmask8; /* 0x24a08 - Pattern Mask Register */
662 char res50[4];
663 uint pcntrl8; /* 0x24a10 - Pattern Match Control Register */
664 char res51[4];
665 uint pattrb8; /* 0x24a18 - Pattern Match Attributes Register */
666 uint pattrbeli8; /* 0x24a1c - Pattern Match Attributes Extract Length and Extract Index Register */
667 uint pmd9; /* 0x24a20 - Pattern Match Data Register */
668 char res52[4];
669 uint pmask9; /* 0x24a28 - Pattern Mask Register */
670 char res53[4];
671 uint pcntrl9; /* 0x24a30 - Pattern Match Control Register */
672 char res54[4];
673 uint pattrb9; /* 0x24a38 - Pattern Match Attributes Register */
674 uint pattrbeli9; /* 0x24a3c - Pattern Match Attributes Extract Length and Extract Index Register */
675 uint pmd10; /* 0x24a40 - Pattern Match Data Register */
676 char res55[4];
677 uint pmask10; /* 0x24a48 - Pattern Mask Register */
678 char res56[4];
679 uint pcntrl10; /* 0x24a50 - Pattern Match Control Register */
680 char res57[4];
681 uint pattrb10; /* 0x24a58 - Pattern Match Attributes Register */
682 uint pattrbeli10; /* 0x24a5c - Pattern Match Attributes Extract Length and Extract Index Register */
683 uint pmd11; /* 0x24a60 - Pattern Match Data Register */
684 char res58[4];
685 uint pmask11; /* 0x24a68 - Pattern Mask Register */
686 char res59[4];
687 uint pcntrl11; /* 0x24a70 - Pattern Match Control Register */
688 char res60[4];
689 uint pattrb11; /* 0x24a78 - Pattern Match Attributes Register */
690 uint pattrbeli11; /* 0x24a7c - Pattern Match Attributes Extract Length and Extract Index Register */
691 uint pmd12; /* 0x24a80 - Pattern Match Data Register */
692 char res61[4];
693 uint pmask12; /* 0x24a88 - Pattern Mask Register */
694 char res62[4];
695 uint pcntrl12; /* 0x24a90 - Pattern Match Control Register */
696 char res63[4];
697 uint pattrb12; /* 0x24a98 - Pattern Match Attributes Register */
698 uint pattrbeli12; /* 0x24a9c - Pattern Match Attributes Extract Length and Extract Index Register */
699 uint pmd13; /* 0x24aa0 - Pattern Match Data Register */
700 char res64[4];
701 uint pmask13; /* 0x24aa8 - Pattern Mask Register */
702 char res65[4];
703 uint pcntrl13; /* 0x24ab0 - Pattern Match Control Register */
704 char res66[4];
705 uint pattrb13; /* 0x24ab8 - Pattern Match Attributes Register */
706 uint pattrbeli13; /* 0x24abc - Pattern Match Attributes Extract Length and Extract Index Register */
707 uint pmd14; /* 0x24ac0 - Pattern Match Data Register */
708 char res67[4];
709 uint pmask14; /* 0x24ac8 - Pattern Mask Register */
710 char res68[4];
711 uint pcntrl14; /* 0x24ad0 - Pattern Match Control Register */
712 char res69[4];
713 uint pattrb14; /* 0x24ad8 - Pattern Match Attributes Register */
714 uint pattrbeli14; /* 0x24adc - Pattern Match Attributes Extract Length and Extract Index Register */
715 uint pmd15; /* 0x24ae0 - Pattern Match Data Register */
716 char res70[4];
717 uint pmask15; /* 0x24ae8 - Pattern Mask Register */
718 char res71[4];
719 uint pcntrl15; /* 0x24af0 - Pattern Match Control Register */
720 char res72[4];
721 uint pattrb15; /* 0x24af8 - Pattern Match Attributes Register */
722 uint pattrbeli15; /* 0x24afc - Pattern Match Attributes Extract Length and Extract Index Register */
723 char res73[248];
724 uint attr; /* 0x24bf8 - Attributes Register */
725 uint attreli; /* 0x24bfc - Attributes Extract Length and Extract Index Register */
726 char res74[1024];
727} ccsr_tsec_t;
728
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500729/*
730 * PIC Registers(0x2_6000-0x4_0000-0x8_0000)
731 */
wdenk42d1f032003-10-15 23:53:47 +0000732typedef struct ccsr_pic {
733 char res0[106496]; /* 0x26000-0x40000 */
734 char res1[64];
735 uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
736 char res2[12];
737 uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
738 char res3[12];
739 uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
740 char res4[12];
741 uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
742 char res5[12];
743 uint ctpr; /* 0x40080 - Current Task Priority Register */
744 char res6[12];
745 uint whoami; /* 0x40090 - Who Am I Register */
746 char res7[12];
747 uint iack; /* 0x400a0 - Interrupt Acknowledge Register */
748 char res8[12];
749 uint eoi; /* 0x400b0 - End Of Interrupt Register */
750 char res9[3916];
751 uint frr; /* 0x41000 - Feature Reporting Register */
752 char res10[28];
753 uint gcr; /* 0x41020 - Global Configuration Register */
wdenk343117b2005-05-13 22:49:36 +0000754#define MPC85xx_PICGCR_RST 0x80000000
755#define MPC85xx_PICGCR_M 0x20000000
wdenk42d1f032003-10-15 23:53:47 +0000756 char res11[92];
757 uint vir; /* 0x41080 - Vendor Identification Register */
758 char res12[12];
759 uint pir; /* 0x41090 - Processor Initialization Register */
760 char res13[12];
761 uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */
762 char res14[12];
763 uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */
764 char res15[12];
765 uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */
766 char res16[12];
767 uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */
768 char res17[12];
769 uint svr; /* 0x410e0 - Spurious Vector Register */
770 char res18[12];
771 uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */
772 char res19[12];
773 uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */
774 char res20[12];
775 uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */
776 char res21[12];
777 uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */
778 char res22[12];
779 uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */
780 char res23[12];
781 uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */
782 char res24[12];
783 uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */
784 char res25[12];
785 uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */
786 char res26[12];
787 uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */
788 char res27[12];
789 uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */
790 char res28[12];
791 uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */
792 char res29[12];
793 uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */
794 char res30[12];
795 uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */
796 char res31[12];
797 uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */
798 char res32[12];
799 uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */
800 char res33[12];
801 uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */
802 char res34[12];
803 uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */
804 char res35[268];
805 uint tcr; /* 0x41300 - Timer Control Register */
806 char res36[12];
807 uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */
808 char res37[12];
809 uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */
810 char res38[12];
811 uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */
812 char res39[12];
813 uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */
814 char res40[188];
815 uint msgr0; /* 0x41400 - Message Register 0 */
816 char res41[12];
817 uint msgr1; /* 0x41410 - Message Register 1 */
818 char res42[12];
819 uint msgr2; /* 0x41420 - Message Register 2 */
820 char res43[12];
821 uint msgr3; /* 0x41430 - Message Register 3 */
822 char res44[204];
823 uint mer; /* 0x41500 - Message Enable Register */
824 char res45[12];
825 uint msr; /* 0x41510 - Message Status Register */
826 char res46[60140];
827 uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */
828 char res47[12];
829 uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */
830 char res48[12];
831 uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */
832 char res49[12];
833 uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */
834 char res50[12];
835 uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */
836 char res51[12];
837 uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */
838 char res52[12];
839 uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */
840 char res53[12];
841 uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */
842 char res54[12];
843 uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */
844 char res55[12];
845 uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */
846 char res56[12];
847 uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
848 char res57[12];
849 uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */
850 char res58[12];
851 uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
852 char res59[12];
853 uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */
854 char res60[12];
855 uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
856 char res61[12];
857 uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */
858 char res62[12];
859 uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */
860 char res63[12];
861 uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */
862 char res64[12];
863 uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */
864 char res65[12];
865 uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */
866 char res66[12];
867 uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */
868 char res67[12];
869 uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */
870 char res68[12];
871 uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */
872 char res69[12];
873 uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */
874 char res70[140];
875 uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
876 char res71[12];
877 uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */
878 char res72[12];
879 uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
880 char res73[12];
881 uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */
882 char res74[12];
883 uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
884 char res75[12];
885 uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */
886 char res76[12];
887 uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
888 char res77[12];
889 uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */
890 char res78[12];
891 uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
892 char res79[12];
893 uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */
894 char res80[12];
895 uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
896 char res81[12];
897 uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */
898 char res82[12];
899 uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
900 char res83[12];
901 uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */
902 char res84[12];
903 uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
904 char res85[12];
905 uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */
906 char res86[12];
907 uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
908 char res87[12];
909 uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */
910 char res88[12];
911 uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
912 char res89[12];
913 uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */
914 char res90[12];
915 uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
916 char res91[12];
917 uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */
918 char res92[12];
919 uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
920 char res93[12];
921 uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */
922 char res94[12];
923 uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
924 char res95[12];
925 uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */
926 char res96[12];
927 uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
928 char res97[12];
929 uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */
930 char res98[12];
931 uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
932 char res99[12];
933 uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */
934 char res100[12];
935 uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
936 char res101[12];
937 uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */
938 char res102[12];
939 uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
940 char res103[12];
941 uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */
942 char res104[12];
943 uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
944 char res105[12];
945 uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */
946 char res106[12];
947 uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
948 char res107[12];
949 uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */
950 char res108[12];
951 uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
952 char res109[12];
953 uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */
954 char res110[12];
955 uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
956 char res111[12];
957 uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */
958 char res112[12];
959 uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
960 char res113[12];
961 uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */
962 char res114[12];
963 uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
964 char res115[12];
965 uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */
966 char res116[12];
967 uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
968 char res117[12];
969 uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */
970 char res118[12];
971 uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
972 char res119[12];
973 uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */
974 char res120[12];
975 uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
976 char res121[12];
977 uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */
978 char res122[12];
979 uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
980 char res123[12];
981 uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */
982 char res124[12];
983 uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
984 char res125[12];
985 uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */
986 char res126[12];
987 uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
988 char res127[12];
989 uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */
990 char res128[12];
991 uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
992 char res129[12];
993 uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */
994 char res130[12];
995 uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
996 char res131[12];
997 uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */
998 char res132[12];
999 uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
1000 char res133[12];
1001 uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */
1002 char res134[4108];
1003 uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
1004 char res135[12];
1005 uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */
1006 char res136[12];
1007 uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
1008 char res137[12];
1009 uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */
1010 char res138[12];
1011 uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
1012 char res139[12];
1013 uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */
1014 char res140[12];
1015 uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
1016 char res141[12];
1017 uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */
1018 char res142[59852];
1019 uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
1020 char res143[12];
1021 uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
1022 char res144[12];
1023 uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
1024 char res145[12];
1025 uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
1026 char res146[12];
1027 uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */
1028 char res147[12];
1029 uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */
1030 char res148[12];
1031 uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
1032 char res149[12];
1033 uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */
1034 char res150[130892];
1035} ccsr_pic_t;
1036
Jon Loeligerde1d0a62005-08-01 13:20:47 -05001037/*
1038 * CPM Block(0x8_0000-0xc_0000)
1039 */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -05001040#ifndef CONFIG_CPM2
wdenk42d1f032003-10-15 23:53:47 +00001041typedef struct ccsr_cpm {
1042 char res[262144];
1043} ccsr_cpm_t;
1044#else
Jon Loeligerde1d0a62005-08-01 13:20:47 -05001045/*
1046 * 0x8000-0x8ffff:DPARM
1047 * 0x9000-0x90bff: General SIU
1048 */
wdenk42d1f032003-10-15 23:53:47 +00001049typedef struct ccsr_cpm_siu {
1050 char res1[80];
1051 uint smaer;
1052 uint smser;
1053 uint smevr;
1054 char res2[4];
1055 uint lmaer;
1056 uint lmser;
1057 uint lmevr;
1058 char res3[2964];
1059} ccsr_cpm_siu_t;
1060
1061/* 0x90c00-0x90cff: Interrupt Controller */
1062typedef struct ccsr_cpm_intctl {
1063 ushort sicr;
1064 char res1[2];
1065 uint sivec;
1066 uint sipnrh;
1067 uint sipnrl;
1068 uint siprr;
1069 uint scprrh;
1070 uint scprrl;
1071 uint simrh;
1072 uint simrl;
1073 uint siexr;
1074 char res2[88];
1075 uint sccr;
1076 char res3[124];
1077} ccsr_cpm_intctl_t;
1078
1079/* 0x90d00-0x90d7f: input/output port */
1080typedef struct ccsr_cpm_iop {
1081 uint pdira;
1082 uint ppara;
1083 uint psora;
1084 uint podra;
1085 uint pdata;
1086 char res1[12];
1087 uint pdirb;
1088 uint pparb;
1089 uint psorb;
1090 uint podrb;
1091 uint pdatb;
1092 char res2[12];
1093 uint pdirc;
1094 uint pparc;
1095 uint psorc;
1096 uint podrc;
1097 uint pdatc;
1098 char res3[12];
1099 uint pdird;
1100 uint ppard;
1101 uint psord;
1102 uint podrd;
1103 uint pdatd;
1104 char res4[12];
1105} ccsr_cpm_iop_t;
1106
1107/* 0x90d80-0x91017: CPM timers */
1108typedef struct ccsr_cpm_timer {
1109 u_char tgcr1;
1110 char res1[3];
1111 u_char tgcr2;
1112 char res2[11];
1113 ushort tmr1;
1114 ushort tmr2;
1115 ushort trr1;
1116 ushort trr2;
1117 ushort tcr1;
1118 ushort tcr2;
1119 ushort tcn1;
1120 ushort tcn2;
1121 ushort tmr3;
1122 ushort tmr4;
1123 ushort trr3;
1124 ushort trr4;
1125 ushort tcr3;
1126 ushort tcr4;
1127 ushort tcn3;
1128 ushort tcn4;
1129 ushort ter1;
1130 ushort ter2;
1131 ushort ter3;
1132 ushort ter4;
1133 char res3[608];
1134} ccsr_cpm_timer_t;
1135
1136/* 0x91018-0x912ff: SDMA */
1137typedef struct ccsr_cpm_sdma {
1138 uchar sdsr;
1139 char res1[3];
1140 uchar sdmr;
1141 char res2[739];
1142} ccsr_cpm_sdma_t;
1143
1144/* 0x91300-0x9131f: FCC1 */
1145typedef struct ccsr_cpm_fcc1 {
1146 uint gfmr;
1147 uint fpsmr;
1148 ushort ftodr;
1149 char res1[2];
1150 ushort fdsr;
1151 char res2[2];
1152 ushort fcce;
1153 char res3[2];
1154 ushort fccm;
1155 char res4[2];
1156 u_char fccs;
1157 char res5[3];
1158 u_char ftirr_phy[4];
1159} ccsr_cpm_fcc1_t;
1160
1161/* 0x91320-0x9133f: FCC2 */
1162typedef struct ccsr_cpm_fcc2 {
1163 uint gfmr;
1164 uint fpsmr;
1165 ushort ftodr;
1166 char res1[2];
1167 ushort fdsr;
1168 char res2[2];
1169 ushort fcce;
1170 char res3[2];
1171 ushort fccm;
1172 char res4[2];
1173 u_char fccs;
1174 char res5[3];
1175 u_char ftirr_phy[4];
1176} ccsr_cpm_fcc2_t;
1177
1178/* 0x91340-0x9137f: FCC3 */
1179typedef struct ccsr_cpm_fcc3 {
1180 uint gfmr;
1181 uint fpsmr;
1182 ushort ftodr;
1183 char res1[2];
1184 ushort fdsr;
1185 char res2[2];
1186 ushort fcce;
1187 char res3[2];
1188 ushort fccm;
1189 char res4[2];
1190 u_char fccs;
1191 char res5[3];
1192 char res[36];
1193} ccsr_cpm_fcc3_t;
1194
1195/* 0x91380-0x9139f: FCC1 extended */
1196typedef struct ccsr_cpm_fcc1_ext {
1197 uint firper;
1198 uint firer;
1199 uint firsr_h;
1200 uint firsr_l;
1201 u_char gfemr;
1202 char res[15];
1203
1204} ccsr_cpm_fcc1_ext_t;
1205
1206/* 0x913a0-0x913cf: FCC2 extended */
1207typedef struct ccsr_cpm_fcc2_ext {
1208 uint firper;
1209 uint firer;
1210 uint firsr_h;
1211 uint firsr_l;
1212 u_char gfemr;
1213 char res[31];
1214} ccsr_cpm_fcc2_ext_t;
1215
1216/* 0x913d0-0x913ff: FCC3 extended */
1217typedef struct ccsr_cpm_fcc3_ext {
1218 u_char gfemr;
1219 char res[47];
1220} ccsr_cpm_fcc3_ext_t;
1221
1222/* 0x91400-0x915ef: TC layers */
1223typedef struct ccsr_cpm_tmp1 {
1224 char res[496];
1225} ccsr_cpm_tmp1_t;
1226
1227/* 0x915f0-0x9185f: BRGs:5,6,7,8 */
1228typedef struct ccsr_cpm_brg2 {
1229 uint brgc5;
1230 uint brgc6;
1231 uint brgc7;
1232 uint brgc8;
1233 char res[608];
1234} ccsr_cpm_brg2_t;
1235
1236/* 0x91860-0x919bf: I2C */
1237typedef struct ccsr_cpm_i2c {
1238 u_char i2mod;
1239 char res1[3];
1240 u_char i2add;
1241 char res2[3];
1242 u_char i2brg;
1243 char res3[3];
1244 u_char i2com;
1245 char res4[3];
1246 u_char i2cer;
1247 char res5[3];
1248 u_char i2cmr;
1249 char res6[331];
1250} ccsr_cpm_i2c_t;
1251
1252/* 0x919c0-0x919ef: CPM core */
1253typedef struct ccsr_cpm_cp {
1254 uint cpcr;
1255 uint rccr;
1256 char res1[14];
1257 ushort rter;
1258 char res2[2];
1259 ushort rtmr;
1260 ushort rtscr;
1261 char res3[2];
1262 uint rtsr;
1263 char res4[12];
1264} ccsr_cpm_cp_t;
1265
1266/* 0x919f0-0x919ff: BRGs:1,2,3,4 */
1267typedef struct ccsr_cpm_brg1 {
1268 uint brgc1;
1269 uint brgc2;
1270 uint brgc3;
1271 uint brgc4;
1272} ccsr_cpm_brg1_t;
1273
1274/* 0x91a00-0x91a9f: SCC1-SCC4 */
1275typedef struct ccsr_cpm_scc {
1276 uint gsmrl;
1277 uint gsmrh;
1278 ushort psmr;
1279 char res1[2];
1280 ushort todr;
1281 ushort dsr;
1282 ushort scce;
1283 char res2[2];
1284 ushort sccm;
1285 char res3;
1286 u_char sccs;
1287 char res4[8];
1288} ccsr_cpm_scc_t;
1289
1290/* 0x91a80-0x91a9f */
1291typedef struct ccsr_cpm_tmp2 {
1292 char res[32];
1293} ccsr_cpm_tmp2_t;
1294
1295/* 0x91aa0-0x91aff: SPI */
1296typedef struct ccsr_cpm_spi {
1297 ushort spmode;
1298 char res1[4];
1299 u_char spie;
1300 char res2[3];
1301 u_char spim;
1302 char res3[2];
1303 u_char spcom;
1304 char res4[82];
1305} ccsr_cpm_spi_t;
1306
1307/* 0x91b00-0x91b1f: CPM MUX */
1308typedef struct ccsr_cpm_mux {
1309 u_char cmxsi1cr;
1310 char res1;
1311 u_char cmxsi2cr;
1312 char res2;
1313 uint cmxfcr;
1314 uint cmxscr;
1315 char res3[2];
1316 ushort cmxuar;
1317 char res4[16];
1318} ccsr_cpm_mux_t;
1319
1320/* 0x91b20-0xbffff: SI,MCC,etc */
1321typedef struct ccsr_cpm_tmp3 {
1322 char res[58592];
1323} ccsr_cpm_tmp3_t;
1324
1325typedef struct ccsr_cpm_iram {
1326 unsigned long iram[8192];
1327 char res[98304];
1328} ccsr_cpm_iram_t;
1329
1330typedef struct ccsr_cpm {
1331 /* Some references are into the unique and known dpram spaces,
1332 * others are from the generic base.
1333 */
1334#define im_dprambase im_dpram1
1335 u_char im_dpram1[16*1024];
1336 char res1[16*1024];
1337 u_char im_dpram2[16*1024];
1338 char res2[16*1024];
wdenk42d1f032003-10-15 23:53:47 +00001339 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
1340 ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */
1341 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
1342 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
1343 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
1344 ccsr_cpm_fcc1_t im_cpm_fcc1;
1345 ccsr_cpm_fcc2_t im_cpm_fcc2;
1346 ccsr_cpm_fcc3_t im_cpm_fcc3;
1347 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
1348 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
1349 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
1350 ccsr_cpm_tmp1_t im_cpm_tmp1;
1351 ccsr_cpm_brg2_t im_cpm_brg2;
1352 ccsr_cpm_i2c_t im_cpm_i2c;
1353 ccsr_cpm_cp_t im_cpm_cp;
1354 ccsr_cpm_brg1_t im_cpm_brg1;
1355 ccsr_cpm_scc_t im_cpm_scc[4];
1356 ccsr_cpm_tmp2_t im_cpm_tmp2;
1357 ccsr_cpm_spi_t im_cpm_spi;
1358 ccsr_cpm_mux_t im_cpm_mux;
1359 ccsr_cpm_tmp3_t im_cpm_tmp3;
1360 ccsr_cpm_iram_t im_cpm_iram;
1361} ccsr_cpm_t;
1362#endif
wdenk42d1f032003-10-15 23:53:47 +00001363
Jon Loeligerde1d0a62005-08-01 13:20:47 -05001364/*
1365 * RapidIO Registers(0xc_0000-0xe_0000)
1366 */
wdenk42d1f032003-10-15 23:53:47 +00001367typedef struct ccsr_rio {
1368 uint didcar; /* 0xc0000 - Device Identity Capability Register */
1369 uint dicar; /* 0xc0004 - Device Information Capability Register */
1370 uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */
1371 uint aicar; /* 0xc000c - Assembly Information Capability Register */
1372 uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */
1373 uint spicar; /* 0xc0014 - Switch Port Information Capability Register */
1374 uint socar; /* 0xc0018 - Source Operations Capability Register */
1375 uint docar; /* 0xc001c - Destination Operations Capability Register */
1376 char res1[32];
1377 uint msr; /* 0xc0040 - Mailbox Command And Status Register */
1378 uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
1379 char res2[4];
1380 uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
1381 char res3[12];
1382 uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
1383 uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */
1384 char res4[4];
1385 uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
1386 uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */
1387 char res5[144];
1388 uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
1389 char res6[28];
1390 uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
1391 uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
1392 char res7[20];
1393 uint pgccsr; /* 0xc013c - Port General Command and Status Register */
1394 uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
1395 uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
1396 uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
1397 char res8[12];
1398 uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */
1399 uint pccsr; /* 0xc015c - Port Control Command and Status Register */
1400 char res9[65184];
1401 uint cr; /* 0xd0000 - Port Control Command and Status Register */
1402 char res10[12];
1403 uint pcr; /* 0xd0010 - Port Configuration Register */
1404 uint peir; /* 0xd0014 - Port Error Injection Register */
1405 char res11[3048];
1406 uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
1407 char res12[12];
1408 uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
1409 char res13[12];
1410 uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
1411 char res14[4];
1412 uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
1413 char res15[4];
1414 uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
1415 char res16[12];
1416 uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
1417 char res17[4];
1418 uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
1419 char res18[4];
1420 uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
1421 char res19[12];
1422 uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
1423 char res20[4];
1424 uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
1425 char res21[4];
1426 uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
1427 char res22[12];
1428 uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
1429 char res23[4];
1430 uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
1431 char res24[4];
1432 uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
1433 char res25[12];
1434 uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
1435 char res26[4];
1436 uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
1437 char res27[4];
1438 uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
1439 char res28[12];
1440 uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
1441 char res29[4];
1442 uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
1443 char res30[4];
1444 uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
1445 char res31[12];
1446 uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
1447 char res32[4];
1448 uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
1449 char res33[4];
1450 uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
1451 char res34[12];
1452 uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
1453 char res35[4];
1454 uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
1455 char res36[4];
1456 uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
1457 char res37[76];
1458 uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
1459 char res38[4];
1460 uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
1461 char res39[4];
1462 uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
1463 char res40[12];
1464 uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
1465 char res41[4];
1466 uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
1467 char res42[4];
1468 uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
1469 char res43[12];
1470 uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
1471 char res44[4];
1472 uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
1473 char res45[4];
1474 uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
1475 char res46[12];
1476 uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
1477 char res47[4];
1478 uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
1479 char res48[4];
1480 uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
1481 char res49[12];
1482 uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
1483 char res50[12];
1484 uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
1485 char res51[12];
1486 uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
1487 uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
1488 uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
1489 uint pecr; /* 0xd0e0c - Port Error Control Register */
1490 uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
1491 uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */
1492 uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */
1493 char res52[4];
1494 uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */
1495 char res53[4];
1496 uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */
1497 uint prtr; /* 0xd0e2c - Port Retry Threshold Register */
1498 char res54[464];
1499 uint omr; /* 0xd1000 - Outbound Mode Register */
1500 uint osr; /* 0xd1004 - Outbound Status Register */
1501 uint eodqtpar; /* 0xd1008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
1502 uint odqtpar; /* 0xd100c - Outbound Descriptor Queue Tail Pointer Address Register */
1503 uint eosar; /* 0xd1010 - Extended Outbound Unit Source Address Register */
1504 uint osar; /* 0xd1014 - Outbound Unit Source Address Register */
1505 uint odpr; /* 0xd1018 - Outbound Destination Port Register */
1506 uint odatr; /* 0xd101c - Outbound Destination Attributes Register */
1507 uint odcr; /* 0xd1020 - Outbound Doubleword Count Register */
1508 uint eodqhpar; /* 0xd1024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
1509 uint odqhpar; /* 0xd1028 - Outbound Descriptor Queue Head Pointer Address Register */
1510 char res55[52];
1511 uint imr; /* 0xd1060 - Outbound Mode Register */
1512 uint isr; /* 0xd1064 - Inbound Status Register */
1513 uint eidqtpar; /* 0xd1068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
1514 uint idqtpar; /* 0xd106c - Inbound Descriptor Queue Tail Pointer Address Register */
1515 uint eifqhpar; /* 0xd1070 - Extended Inbound Frame Queue Head Pointer Address Register */
1516 uint ifqhpar; /* 0xd1074 - Inbound Frame Queue Head Pointer Address Register */
1517 char res56[1000];
1518 uint dmr; /* 0xd1460 - Doorbell Mode Register */
1519 uint dsr; /* 0xd1464 - Doorbell Status Register */
1520 uint edqtpar; /* 0xd1468 - Extended Doorbell Queue Tail Pointer Address Register */
1521 uint dqtpar; /* 0xd146c - Doorbell Queue Tail Pointer Address Register */
1522 uint edqhpar; /* 0xd1470 - Extended Doorbell Queue Head Pointer Address Register */
1523 uint dqhpar; /* 0xd1474 - Doorbell Queue Head Pointer Address Register */
1524 char res57[104];
1525 uint pwmr; /* 0xd14e0 - Port-Write Mode Register */
1526 uint pwsr; /* 0xd14e4 - Port-Write Status Register */
1527 uint epwqbar; /* 0xd14e8 - Extended Port-Write Queue Base Address Register */
1528 uint pwqbar; /* 0xd14ec - Port-Write Queue Base Address Register */
1529 char res58[60176];
1530} ccsr_rio_t;
1531
Jon Loeligerde1d0a62005-08-01 13:20:47 -05001532/*
1533 * Global Utilities Register Block(0xe_0000-0xf_ffff)
1534 */
wdenk42d1f032003-10-15 23:53:47 +00001535typedef struct ccsr_gur {
1536 uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
1537 uint porbmsr; /* 0xe0004 - POR boot mode status register */
1538 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
1539 uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
1540 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
1541 char res1[12];
1542 uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
1543 char res2[12];
1544 uint gpiocr; /* 0xe0030 - GPIO control register */
1545 char res3[12];
1546 uint gpoutdr; /* 0xe0040 - General-purpose output data register */
1547 char res4[12];
1548 uint gpindr; /* 0xe0050 - General-purpose input data register */
1549 char res5[12];
1550 uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
1551 char res6[12];
1552 uint devdisr; /* 0xe0070 - Device disable control */
1553 char res7[12];
1554 uint powmgtcsr; /* 0xe0080 - Power management status and control register */
1555 char res8[12];
1556 uint mcpsumr; /* 0xe0090 - Machine check summary register */
1557 char res9[12];
1558 uint pvr; /* 0xe00a0 - Processor version register */
1559 uint svr; /* 0xe00a4 - System version register */
1560 char res10[3416];
1561 uint clkocr; /* 0xe0e00 - Clock out select register */
1562 char res11[12];
1563 uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
1564 char res12[12];
1565 uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001566 char res13[248];
1567 uint lbiuiplldcr0; /* 0xe0f1c -- LBIU PLL Debug Reg 0 */
1568 uint lbiuiplldcr1; /* 0xe0f20 -- LBIU PLL Debug Reg 1 */
1569 uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */
1570 uint res14; /* 0xe0f28 */
1571 uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
1572 char res15[61651];
wdenk42d1f032003-10-15 23:53:47 +00001573} ccsr_gur_t;
1574
1575typedef struct immap {
1576 ccsr_local_ecm_t im_local_ecm;
1577 ccsr_ddr_t im_ddr;
1578 ccsr_i2c_t im_i2c;
1579 ccsr_duart_t im_duart;
1580 ccsr_lbc_t im_lbc;
1581 ccsr_pcix_t im_pcix;
1582 ccsr_l2cache_t im_l2cache;
1583 ccsr_dma_t im_dma;
1584 ccsr_tsec_t im_tsec1;
1585 ccsr_tsec_t im_tsec2;
1586 ccsr_pic_t im_pic;
1587 ccsr_cpm_t im_cpm;
1588 ccsr_rio_t im_rio;
1589 ccsr_gur_t im_gur;
1590} immap_t;
1591
1592extern immap_t *immr;
1593
1594#endif /*__IMMAP_85xx__*/