blob: 29feb7bba13210df6710df0a1501edab53af0993 [file] [log] [blame]
Jon Smirlc9969942009-06-14 18:21:28 -04001/*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2006
6 * Eric Schumann, Phytec Messatechnik GmbH
7 *
8 * (C) Copyright 2009
9 * Jon Smirl <jonsmirl@gmail.com>
10 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020011 * SPDX-License-Identifier: GPL-2.0+
Jon Smirlc9969942009-06-14 18:21:28 -040012 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
17#define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny"
18
19/*-----------------------------------------------------------------------------
20High Level Configuration Options
21(easy to change)
22-----------------------------------------------------------------------------*/
Masahiro Yamadab2a6dfe2014-01-16 11:03:07 +090023#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
Jon Smirlc9969942009-06-14 18:21:28 -040024#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */
25#define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */
26 /* FEC configuration and IDE */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020027
28/*
29 * Valid values for CONFIG_SYS_TEXT_BASE are:
30 * 0xFFF00000 boot high (standard configuration)
31 * 0xFF000000 boot low
32 * 0x00100000 boot from RAM (for testing only)
33 */
34#ifndef CONFIG_SYS_TEXT_BASE
35#define CONFIG_SYS_TEXT_BASE 0xFFF00000
36#endif
37
Jon Smirlc9969942009-06-14 18:21:28 -040038#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
Jon Smirlc9969942009-06-14 18:21:28 -040039
40/*-----------------------------------------------------------------------------
41Serial console configuration
42-----------------------------------------------------------------------------*/
43#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 -> */
44 /*define gps port conf. */
45 /* register later on to */
46 /*enable UART function! */
47#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
48#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
49
50/*
51 * Command line configuration.
52 */
Jon Smirlc9969942009-06-14 18:21:28 -040053#define CONFIG_CMD_DATE
54#define CONFIG_CMD_DHCP
55#define CONFIG_CMD_EEPROM
56#define CONFIG_CMD_I2C
57#define CONFIG_CMD_JFFS2
58#define CONFIG_CMD_MII
Jon Smirlc9969942009-06-14 18:21:28 -040059#define CONFIG_CMD_PCI
60
61#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
62
Wolfgang Denk14d0a022010-10-07 21:51:12 +020063#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low */
Jon Smirlc9969942009-06-14 18:21:28 -040064#define CONFIG_SYS_LOWBOOT 1
65#endif
66/* RAMBOOT will be defined automatically in memory section */
67
68#define CONFIG_JFFS2_CMDLINE
69#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
70#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
71 "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
72
73/*-----------------------------------------------------------------------------
74Autobooting
75-----------------------------------------------------------------------------*/
76#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
77#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */
78 /* even with bootdelay=0 */
79#undef CONFIG_BOOTARGS
80
81
82#define CONFIG_PREBOOT "echo;" \
83 "echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\
84 "mount root filesystem over NFS;" \
85 "echo"
86
87#define CONFIG_EXTRA_ENV_SETTINGS \
88 "netdev=eth0\0" \
89 "uimage=uImage-pcm030\0" \
90 "oftree=oftree-pcm030.dtb\0" \
91 "jffs2=root-pcm030.jffs2\0" \
92 "uboot=u-boot-pcm030.bin\0" \
93 "bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)" \
94 " $(mtdparts) rw\0" \
95 "bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2" \
96 " rootfstype=jffs2\0" \
97 "bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs" \
98 " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::" \
99 "$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
100 "bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \
101 " tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \
102 "bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - " \
103 "0xfff40000\0" \
104 " cp.b 0x400000 0xff040000 $(filesize)\0" \
105 "prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \
106 "cp.b 0x400000 0xff200000 $(filesize)\0" \
107 "prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \
108 " cp.b 0x400000 0xfff40000 $(filesize)\0" \
109 "update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \
110 " cp.b 0x400000 0xFFF00000 $(filesize)\0" \
111 "unlock=yes\0" \
112 ""
113
114#define CONFIG_BOOTCOMMAND "run bcmd_flash"
115
116/*--------------------------------------------------------------------------
117IPB Bus clocking configuration.
118 ---------------------------------------------------------------------------*/
119#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
120
121/*-------------------------------------------------------------------------
122 * PCI Mapping:
123 * 0x40000000 - 0x4fffffff - PCI Memory
124 * 0x50000000 - 0x50ffffff - PCI IO Space
125 * -----------------------------------------------------------------------*/
126#define CONFIG_PCI 1
127#define CONFIG_PCI_PNP 1
128#define CONFIG_PCI_SCAN_SHOW 1
129#define CONFIG_PCI_MEM_BUS 0x40000000
130#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
131#define CONFIG_PCI_MEM_SIZE 0x10000000
132#define CONFIG_PCI_IO_BUS 0x50000000
133#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
134#define CONFIG_PCI_IO_SIZE 0x01000000
135#define CONFIG_SYS_XLB_PIPELINING 1
136
137/*---------------------------------------------------------------------------
138 I2C configuration
139---------------------------------------------------------------------------*/
140#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
141#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
142#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
143#define CONFIG_SYS_I2C_SLAVE 0x7F
144
145/*---------------------------------------------------------------------------
146 EEPROM CAT24WC32 configuration
147---------------------------------------------------------------------------*/
148#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */
149#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */
150#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
151#define CONFIG_SYS_EEPROM_SIZE 2048
152#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
153#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
154
155/*---------------------------------------------------------------------------
156RTC configuration
157---------------------------------------------------------------------------*/
158#define RTC
159#define CONFIG_RTC_PCF8563 1
160#define CONFIG_SYS_I2C_RTC_ADDR 0x51
161
162/*---------------------------------------------------------------------------
163 Flash configuration
164---------------------------------------------------------------------------*/
165
166#define CONFIG_SYS_FLASH_BASE 0xff000000
167#define CONFIG_SYS_FLASH_SIZE 0x01000000
168#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
169
170#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
171#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
172#define CONFIG_SYS_FLASH_EMPTY_INFO
173#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */
174#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
175 /* (= chip selects) */
176#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
177
178/*
179 * Use also hardware protection. This seems required, as the BDI uses
180 * hardware protection. Without this, U-Boot can't work with this sectors,
181 * as its protection is software only by default
182 */
183#define CONFIG_SYS_FLASH_PROTECTION 1
184
185/*---------------------------------------------------------------------------
186 Environment settings
187---------------------------------------------------------------------------*/
188
189/* pcm030 ships with environment is EEPROM by default */
190#define CONFIG_ENV_IS_IN_EEPROM 1
191#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
192 /*beginning of the EEPROM */
193#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE
194
195#define CONFIG_ENV_OVERWRITE 1
196
197/*-----------------------------------------------------------------------------
198 Memory map
199-----------------------------------------------------------------------------*/
200#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
201 /* bootloader or debugger config */
202#define CONFIG_SYS_SDRAM_BASE 0x00000000
203#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
204/* Use SRAM until RAM will be available */
205#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200206#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used */
Jon Smirlc9969942009-06-14 18:21:28 -0400207 /* area in DPRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200208#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200209 GENERATED_GBL_DATA_SIZE)
Jon Smirlc9969942009-06-14 18:21:28 -0400210#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
211
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200212#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jon Smirlc9969942009-06-14 18:21:28 -0400213#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
214# define CONFIG_SYS_RAMBOOT 1
215#endif
216
217#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
218#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
219#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
220
221/*-----------------------------------------------------------------------------
222 Ethernet configuration
223-----------------------------------------------------------------------------*/
224#define CONFIG_MPC5xxx_FEC 1
225#define CONFIG_MPC5xxx_FEC_MII100
226#define CONFIG_PHY_ADDR 0x01
227
228/*---------------------------------------------------------------------------
229 GPIO configuration
230 ---------------------------------------------------------------------------*/
231
232/* GPIO port configuration
233 *
234 * Pin mapping:
235 *
236 * [29:31] = 01x
237 * PSC1_0 -> AC97 SDATA out
238 * PSC1_1 -> AC97 SDTA in
239 * PSC1_2 -> AC97 SYNC out
240 * PSC1_3 -> AC97 bitclock out
241 * PSC1_4 -> AC97 reset out
242 *
243 * [25:27] = 001
244 * PSC2_0 -> CAN 1 Tx out
245 * PSC2_1 -> CAN 1 Rx in
246 * PSC2_2 -> CAN 2 Tx out
247 * PSC2_3 -> CAN 2 Rx in
248 * PSC2_4 -> GPIO (claimed for ATA reset, active low)
249 *
250 *
251 * [20:23] = 1100
252 * PSC3_0 -> UART Tx out
253 * PSC3_1 -> UART Rx in
254 * PSC3_2 -> UART RTS (in/out FIXME)
255 * PSC3_3 -> UART CTS (in/out FIXME)
256 * PSC3_4 -> LocalPlus Bus CS6 \
257 * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5]
258 * PSC3_6 -> dedicated SPI MOSI out (master case)
259 * PSC3_7 -> dedicated SPI MISO in (master case)
260 * PSC3_8 -> dedicated SPI SS out (master case)
261 * PSC3_9 -> dedicated SPI CLK out (master case)
262 *
263 * [18:19] = 01
264 * USB_0 -> USB OE out
265 * USB_1 -> USB Tx- out
266 * USB_2 -> USB Tx+ out
267 * USB_3 -> USB RxD (in/out FIXME)
268 * USB_4 -> USB Rx+ in
269 * USB_5 -> USB Rx- in
270 * USB_6 -> USB PortPower out
271 * USB_7 -> USB speed out
272 * USB_8 -> USB suspend (in/out FIXME)
273 * USB_9 -> USB overcurrent in
274 *
275 * [17] = 0
276 * USB differential mode
277 *
278 * [16] = 0
279 * PCI enabled
280 *
281 * [12:15] = 0101
282 * ETH_0 -> ETH Txen
283 * ETH_1 -> ETH TxD0
284 * ETH_2 -> ETH TxD1
285 * ETH_3 -> ETH TxD2
286 * ETH_4 -> ETH TxD3
287 * ETH_5 -> ETH Txerr
288 * ETH_6 -> ETH MDC
289 * ETH_7 -> ETH MDIO
290 * ETH_8 -> ETH RxDv
291 * ETH_9 -> ETH RxCLK
292 * ETH_10 -> ETH Collision
293 * ETH_11 -> ETH TxD
294 * ETH_12 -> ETH RxD0
295 * ETH_13 -> ETH RxD1
296 * ETH_14 -> ETH RxD2
297 * ETH_15 -> ETH RxD3
298 * ETH_16 -> ETH Rxerr
299 * ETH_17 -> ETH CRS
300 *
301 * [9:11] = 101
302 * PSC6_0 -> UART RxD in
303 * PSC6_1 -> UART CTS (in/out FIXME)
304 * PSC6_2 -> UART TxD out
305 * PSC6_3 -> UART RTS (in/out FIXME)
306 *
307 * [2:3/6:7] = 00/11
308 * TMR_0 -> ATA_CS0 out
309 * TMR_1 -> ATA_CS1 out
310 * TMR_2 -> GPIO
311 * TMR_3 -> GPIO
312 * TMR_4 -> GPIO
313 * TMR_5 -> GPIO
314 * TMR_6 -> GPIO
315 * TMR_7 -> GPIO
316 * I2C_0 -> I2C 1 Clock out
317 * I2C_1 -> I2C 1 IO in/out
318 * I2C_2 -> I2C 2 Clock out
319 * I2C_3 -> I2C 2 IO in/out
320 *
321 * [4] = 1
322 * PSC3_5 is used as CS7
323 *
324 * [5] = 1
325 * PSC3_4 is used as CS6
326 *
327 * [1] = 0
328 * gpio_wkup_7 is GPIO
329 *
330 * [0] = 0
331 * gpio_wkup_6 is GPIO
332 *
333 */
334#define CONFIG_SYS_GPS_PORT_CONFIG 0x0f551c12
335
336/*-----------------------------------------------------------------------------
337 Miscellaneous configurable options
338-------------------------------------------------------------------------------*/
339#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Smirlc9969942009-06-14 18:21:28 -0400340
341#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
342
343#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
344#if defined(CONFIG_CMD_KGDB)
345#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
346#endif
347
348#if defined(CONFIG_CMD_KGDB)
349#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
350#else
351#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
352#endif
353#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
354 /* Print Buffer Size */
355#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
356#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
357
358#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
359#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
360
361#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
Jon Smirlc9969942009-06-14 18:21:28 -0400362
363#define CONFIG_DISPLAY_BOARDINFO 1
364
365/*-----------------------------------------------------------------------------
366 Various low-level settings
367-----------------------------------------------------------------------------*/
368#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
369#define CONFIG_SYS_HID0_FINAL HID0_ICE
370
371/* no burst access on the LPB */
372#define CONFIG_SYS_CS_BURST 0x00000000
373/* one deadcycle for the 33MHz statemachine */
374#define CONFIG_SYS_CS_DEADCYCLE 0x33333331
375/* one additional waitstate for the 33MHz statemachine */
376#define CONFIG_SYS_BOOTCS_CFG 0x0001dd00
377#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
378#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
379
380#define CONFIG_SYS_RESET_ADDRESS 0xff000000
381
382/*-----------------------------------------------------------------------
383 * USB stuff
384 *-----------------------------------------------------------------------
385 */
386#define CONFIG_USB_CLOCK 0x0001BBBB
387#define CONFIG_USB_CONFIG 0x00001000
388
389/*---------------------------------------------------------------------------
390 IDE/ATA stuff Supports IDE harddisk
391----------------------------------------------------------------------------*/
392
393#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
394#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
395#undef CONFIG_IDE_LED /* LED for ide not supported */
396#define CONFIG_SYS_ATA_CS_ON_TIMER01
397#define CONFIG_IDE_RESET 1 /* reset for ide supported */
398#define CONFIG_IDE_PREINIT
399#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
400#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
401#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
402#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
403/* Offset for data I/O */
404#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
405/* Offset for normal register accesses */
406#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
407/* Offset for alternate registers */
408#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
409/* Interval between registers */
410#define CONFIG_SYS_ATA_STRIDE 4
411#define CONFIG_ATAPI 1
412
413/* we enable IDE and FAT support, so we also need partition support */
414#define CONFIG_DOS_PARTITION 1
415
416/* USB */
417#define CONFIG_USB_OHCI
418#define CONFIG_USB_STORAGE
419
420/* pass open firmware flat tree */
421#define CONFIG_OF_LIBFDT 1
422#define CONFIG_OF_BOARD_SETUP 1
423
424#define OF_CPU "PowerPC,5200@0"
425#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
426#define OF_SOC "soc5200@f0000000"
427#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2400"
428
429#endif /* __CONFIG_H */