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wdenk5f2d51b2002-04-26 15:23:50 +00001/*
2 * (C) Copyright 2001
3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk5f2d51b2002-04-26 15:23:50 +00006 */
7
8
wdenk5f2d51b2002-04-26 15:23:50 +00009#ifndef _PIIX4_PCI_H
10#define _PIIX4_PCI_H
11
12/***************************************************************************
13* Defines PIIX4 Config Registers
14****************************************************************************/
15
16/* Function 0 ISA Bridge */
17#define PCI_CFG_PIIX4_IORT 0x4C /* 8 bit ISA Recovery Timer Reg (default 0x4D) */
18#define PCI_CFG_PIIX4_XBCS 0x4E /* 16 bit XBus Chip select reg (default 0x0003) */
19#define PCI_CFG_PIIX4_PIRQC 0x60 /* PCI IRQ Route Register 4 x 8bit (default )*/
20#define PCI_CFG_PIIX4_SERIRQ 0x64
21#define PCI_CFG_PIIX4_TOM 0x69
22#define PCI_CFG_PIIX4_MSTAT 0x6A
23#define PCI_CFG_PIIX4_MBDMA 0x76
24#define PCI_CFG_PIIX4_APICBS 0x80
25#define PCI_CFG_PIIX4_DLC 0x82
26#define PCI_CFG_PIIX4_PDMACFG 0x90
27#define PCI_CFG_PIIX4_DDMABS 0x92
28#define PCI_CFG_PIIX4_GENCFG 0xB0
29#define PCI_CFG_PIIX4_RTCCFG 0xCB
30
31/* IO Addresses */
32#define PIIX4_ISA_DMA1_CH0BA 0x00
33#define PIIX4_ISA_DMA1_CH0CA 0x01
34#define PIIX4_ISA_DMA1_CH1BA 0x02
35#define PIIX4_ISA_DMA1_CH1CA 0x03
36#define PIIX4_ISA_DMA1_CH2BA 0x04
37#define PIIX4_ISA_DMA1_CH2CA 0x05
38#define PIIX4_ISA_DMA1_CH3BA 0x06
39#define PIIX4_ISA_DMA1_CH3CA 0x07
40#define PIIX4_ISA_DMA1_CMDST 0x08
41#define PIIX4_ISA_DMA1_REQ 0x09
42#define PIIX4_ISA_DMA1_WSBM 0x0A
43#define PIIX4_ISA_DMA1_CH_MOD 0x0B
44#define PIIX4_ISA_DMA1_CLR_PT 0x0C
45#define PIIX4_ISA_DMA1_M_CLR 0x0D
46#define PIIX4_ISA_DMA1_CLR_M 0x0E
47#define PIIX4_ISA_DMA1_RWAMB 0x0F
48
49#define PIIX4_ISA_DMA2_CH0BA 0xC0
50#define PIIX4_ISA_DMA2_CH0CA 0xC1
51#define PIIX4_ISA_DMA2_CH1BA 0xC2
52#define PIIX4_ISA_DMA2_CH1CA 0xC3
53#define PIIX4_ISA_DMA2_CH2BA 0xC4
54#define PIIX4_ISA_DMA2_CH2CA 0xC5
55#define PIIX4_ISA_DMA2_CH3BA 0xC6
56#define PIIX4_ISA_DMA2_CH3CA 0xC7
57#define PIIX4_ISA_DMA2_CMDST 0xD0
58#define PIIX4_ISA_DMA2_REQ 0xD2
59#define PIIX4_ISA_DMA2_WSBM 0xD4
60#define PIIX4_ISA_DMA2_CH_MOD 0xD6
61#define PIIX4_ISA_DMA2_CLR_PT 0xD8
62#define PIIX4_ISA_DMA2_M_CLR 0xDA
63#define PIIX4_ISA_DMA2_CLR_M 0xDC
64#define PIIX4_ISA_DMA2_RWAMB 0xDE
65
66#define PIIX4_ISA_INT1_ICW1 0x20
67#define PIIX4_ISA_INT1_OCW2 0x20
68#define PIIX4_ISA_INT1_OCW3 0x20
69#define PIIX4_ISA_INT1_ICW2 0x21
70#define PIIX4_ISA_INT1_ICW3 0x21
71#define PIIX4_ISA_INT1_ICW4 0x21
72#define PIIX4_ISA_INT1_OCW1 0x21
73
74#define PIIX4_ISA_INT1_ELCR 0x4D0
75
76#define PIIX4_ISA_INT2_ICW1 0xA0
77#define PIIX4_ISA_INT2_OCW2 0xA0
78#define PIIX4_ISA_INT2_OCW3 0xA0
79#define PIIX4_ISA_INT2_ICW2 0xA1
80#define PIIX4_ISA_INT2_ICW3 0xA1
81#define PIIX4_ISA_INT2_ICW4 0xA1
82#define PIIX4_ISA_INT2_OCW1 0xA1
83#define PIIX4_ISA_INT2_IMR 0xA1 /* read only */
84
85#define PIIX4_ISA_INT2_ELCR 0x4D1
86
87#define PIIX4_ISA_TMR0_CNT_ST 0x40
88#define PIIX4_ISA_TMR1_CNT_ST 0x41
89#define PIIX4_ISA_TMR2_CNT_ST 0x42
90#define PIIX4_ISA_TMR_TCW 0x43
91
92#define PIIX4_ISA_RST_XBUS 0x60
93
94#define PIIX4_ISA_NMI_CNT_ST 0x61
95#define PIIX4_ISA_NMI_ENABLE 0x70
96
97#define PIIX4_ISA_RTC_INDEX 0x70
98#define PIIX4_ISA_RTC_DATA 0x71
99#define PIIX4_ISA_RTCEXT_IND 0x70
100#define PIIX4_ISA_RTCEXT_DATA 0x71
101
102#define PIIX4_ISA_DMA1_CH2LPG 0x81
103#define PIIX4_ISA_DMA1_CH3LPG 0x82
104#define PIIX4_ISA_DMA1_CH1LPG 0x83
105#define PIIX4_ISA_DMA1_CH0LPG 0x87
106#define PIIX4_ISA_DMA2_CH2LPG 0x89
107#define PIIX4_ISA_DMA2_CH3LPG 0x8A
108#define PIIX4_ISA_DMA2_CH1LPG 0x8B
109#define PIIX4_ISA_DMA2_LPGRFR 0x8F
110
111#define PIIX4_ISA_PORT_92 0x92
112
113#define PIIX4_ISA_APM_CONTRL 0xB2
114#define PIIX4_ISA_APM_STATUS 0xB3
115
116#define PIIX4_ISA_COCPU_ERROR 0xF0
117
118/* Function 1 IDE Controller */
119#define PCI_CFG_PIIX4_BMIBA 0x20
120#define PCI_CFG_PIIX4_IDETIM 0x40
121#define PCI_CFG_PIIX4_SIDETIM 0x44
122#define PCI_CFG_PIIX4_UDMACTL 0x48
123#define PCI_CFG_PIIX4_UDMATIM 0x4A
124
125/* Function 2 USB Controller */
126#define PCI_CFG_PIIX4_SBRNUM 0x60
127#define PCI_CFG_PIIX4_LEGSUP 0xC0
128
129/* Function 3 Power Management */
wdenk7205e402003-09-10 22:30:53 +0000130#define PCI_CFG_PIIX4_PMBA 0x40
wdenk5f2d51b2002-04-26 15:23:50 +0000131#define PCI_CFG_PIIX4_CNTA 0x44
132#define PCI_CFG_PIIX4_CNTB 0x48
133#define PCI_CFG_PIIX4_GPICTL 0x4C
134#define PCI_CFG_PIIX4_DEVRESD 0x50
135#define PCI_CFG_PIIX4_DEVACTA 0x54
136#define PCI_CFG_PIIX4_DEVACTB 0x58
137#define PCI_CFG_PIIX4_DEVRESA 0x5C
138#define PCI_CFG_PIIX4_DEVRESB 0x60
139#define PCI_CFG_PIIX4_DEVRESC 0x64
140#define PCI_CFG_PIIX4_DEVRESE 0x68
141#define PCI_CFG_PIIX4_DEVRESF 0x6C
142#define PCI_CFG_PIIX4_DEVRESG 0x70
143#define PCI_CFG_PIIX4_DEVRESH 0x74
144#define PCI_CFG_PIIX4_DEVRESI 0x78
145#define PCI_CFG_PIIX4_PMMISC 0x80
146#define PCI_CFG_PIIX4_SMBBA 0x90
147
148
wdenk5f2d51b2002-04-26 15:23:50 +0000149#endif