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wdenk012771d2002-03-08 21:31:05 +00001/*
2 * (C) Copyright 2001
3 * Denis Peter, MPL AG Switzerland
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk012771d2002-03-08 21:31:05 +00006 *
7 * Note: Part of this code has been derived from linux
wdenk012771d2002-03-08 21:31:05 +00008 */
9#ifndef _USB_UHCI_H_
10#define _USB_UHCI_H_
11
12
13/* Command register */
14#define USBCMD 0
15#define USBCMD_RS 0x0001 /* Run/Stop */
16#define USBCMD_HCRESET 0x0002 /* Host reset */
17#define USBCMD_GRESET 0x0004 /* Global reset */
18#define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
19#define USBCMD_FGR 0x0010 /* Force Global Resume */
20#define USBCMD_SWDBG 0x0020 /* SW Debug mode */
21#define USBCMD_CF 0x0040 /* Config Flag (sw only) */
22#define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
23
24/* Status register */
25#define USBSTS 2
26#define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */
27#define USBSTS_ERROR 0x0002 /* Interrupt due to error */
28#define USBSTS_RD 0x0004 /* Resume Detect */
29#define USBSTS_HSE 0x0008 /* Host System Error - basically PCI problems */
30#define USBSTS_HCPE 0x0010 /* Host Controller Process Error - the scripts were buggy */
31#define USBSTS_HCH 0x0020 /* HC Halted */
32
33/* Interrupt enable register */
34#define USBINTR 4
35#define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */
36#define USBINTR_RESUME 0x0002 /* Resume interrupt enable */
37#define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */
38#define USBINTR_SP 0x0008 /* Short packet interrupt enable */
39
40#define USBFRNUM 6
41#define USBFLBASEADD 8
42#define USBSOF 12
43
44/* USB port status and control registers */
45#define USBPORTSC1 16
46#define USBPORTSC2 18
47#define USBPORTSC_CCS 0x0001 /* Current Connect Status ("device present") */
48#define USBPORTSC_CSC 0x0002 /* Connect Status Change */
49#define USBPORTSC_PE 0x0004 /* Port Enable */
50#define USBPORTSC_PEC 0x0008 /* Port Enable Change */
51#define USBPORTSC_LS 0x0030 /* Line Status */
52#define USBPORTSC_RD 0x0040 /* Resume Detect */
53#define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */
54#define USBPORTSC_PR 0x0200 /* Port Reset */
55#define USBPORTSC_SUSP 0x1000 /* Suspend */
56
57/* Legacy support register */
58#define USBLEGSUP 0xc0
59#define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
60
61#define UHCI_NULL_DATA_SIZE 0x7ff /* for UHCI controller TD */
62#define UHCI_PID 0xff /* PID MASK */
63
64#define UHCI_PTR_BITS 0x000F
65#define UHCI_PTR_TERM 0x0001
66#define UHCI_PTR_QH 0x0002
67#define UHCI_PTR_DEPTH 0x0004
68
69/* for TD <status>: */
70#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */
71#define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */
72#define TD_CTRL_LS (1 << 26) /* Low Speed Device */
73#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */
74#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */
75#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */
76#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */
77#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */
78#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */
79#define TD_CTRL_NAK (1 << 19) /* NAK Received */
80#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */
81#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */
82#define TD_CTRL_ACTLEN_MASK 0x7ff /* actual length, encoded as n - 1 */
83
84#define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
85 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
86
87#define TD_TOKEN_TOGGLE 19
88
89/* ------------------------------------------------------------------------------------
90 Virtual Root HUB
91 ------------------------------------------------------------------------------------ */
92/* destination of request */
93#define RH_INTERFACE 0x01
94#define RH_ENDPOINT 0x02
95#define RH_OTHER 0x03
96
97#define RH_CLASS 0x20
98#define RH_VENDOR 0x40
99
100/* Requests: bRequest << 8 | bmRequestType */
101#define RH_GET_STATUS 0x0080
102#define RH_CLEAR_FEATURE 0x0100
103#define RH_SET_FEATURE 0x0300
104#define RH_SET_ADDRESS 0x0500
105#define RH_GET_DESCRIPTOR 0x0680
106#define RH_SET_DESCRIPTOR 0x0700
107#define RH_GET_CONFIGURATION 0x0880
108#define RH_SET_CONFIGURATION 0x0900
109#define RH_GET_STATE 0x0280
110#define RH_GET_INTERFACE 0x0A80
111#define RH_SET_INTERFACE 0x0B00
112#define RH_SYNC_FRAME 0x0C80
113/* Our Vendor Specific Request */
114#define RH_SET_EP 0x2000
115
116/* Hub port features */
117#define RH_PORT_CONNECTION 0x00
118#define RH_PORT_ENABLE 0x01
119#define RH_PORT_SUSPEND 0x02
120#define RH_PORT_OVER_CURRENT 0x03
121#define RH_PORT_RESET 0x04
122#define RH_PORT_POWER 0x08
123#define RH_PORT_LOW_SPEED 0x09
124#define RH_C_PORT_CONNECTION 0x10
125#define RH_C_PORT_ENABLE 0x11
126#define RH_C_PORT_SUSPEND 0x12
127#define RH_C_PORT_OVER_CURRENT 0x13
128#define RH_C_PORT_RESET 0x14
129
130/* Hub features */
131#define RH_C_HUB_LOCAL_POWER 0x00
132#define RH_C_HUB_OVER_CURRENT 0x01
133
134#define RH_DEVICE_REMOTE_WAKEUP 0x00
135#define RH_ENDPOINT_STALL 0x01
136
137/* Our Vendor Specific feature */
138#define RH_REMOVE_EP 0x00
139
140
141#define RH_ACK 0x01
142#define RH_REQ_ERR -1
143#define RH_NACK 0x00
144
145
146/* Transfer descriptor structure */
147typedef struct {
148 unsigned long link; /* next td/qh (LE)*/
149 unsigned long status; /* status of the td */
150 unsigned long info; /* Max Lenght / Endpoint / device address and PID */
151 unsigned long buffer; /* pointer to data buffer (LE) */
152 unsigned long dev_ptr; /* pointer to the assigned device (BE) */
153 unsigned long res[3]; /* reserved (TDs must be 8Byte aligned) */
154} uhci_td_t, *puhci_td_t;
155
156/* Queue Header structure */
157typedef struct {
158 unsigned long head; /* Next QH (LE)*/
159 unsigned long element; /* Queue element pointer (LE) */
160 unsigned long res[5]; /* reserved */
161 unsigned long dev_ptr; /* if 0 no tds have been assigned to this qh */
162} uhci_qh_t, *puhci_qh_t;
163
164struct virt_root_hub {
165 int devnum; /* Address of Root Hub endpoint */
166 int numports; /* number of ports */
167 int c_p_r[8]; /* C_PORT_RESET */
168};
169
170
171#endif /* _USB_UHCI_H_ */