blob: ef84aad819cb873de59152d314ad177405fbfc94 [file] [log] [blame]
Dave Gerlacheb541682021-04-23 11:27:32 -05001// SPDX-License-Identifier: GPL-2.0
2/*
3 * AM642: SoC specific initialization
4 *
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6 * Keerthy <j-keerthy@ti.com>
7 * Dave Gerlach <d-gerlach@ti.com>
8 */
9
10#include <common.h>
Aswath Govindraju669a03e2021-06-04 22:00:33 +053011#include <fdt_support.h>
Dave Gerlacheb541682021-04-23 11:27:32 -050012#include <spl.h>
13#include <asm/io.h>
Keerthy57dba042021-04-23 11:27:33 -050014#include <asm/arch/hardware.h>
Andrew Davisf5e49442023-04-06 11:38:16 -050015#include "sysfw-loader.h"
Dave Gerlachd2edabf2021-04-23 11:27:36 -050016#include <asm/arch/sys_proto.h>
Dave Gerlacheb541682021-04-23 11:27:32 -050017#include "common.h"
Dave Gerlachd2edabf2021-04-23 11:27:36 -050018#include <asm/arch/sys_proto.h>
19#include <linux/soc/ti/ti_sci_protocol.h>
20#include <dm.h>
21#include <dm/uclass-internal.h>
22#include <dm/pinctrl.h>
Dave Gerlachf4686c32021-04-23 11:27:37 -050023#include <mmc.h>
Lokesh Vutlab5425a92021-05-06 16:44:52 +053024#include <dm/root.h>
Dave Gerlacheb541682021-04-23 11:27:32 -050025
Hari Nagalla92e46092022-03-09 14:42:30 -060026#define CTRLMMR_MCU_RST_CTRL 0x04518170
Dave Gerlacheb541682021-04-23 11:27:32 -050027
Dave Gerlachb4a8c3b2021-04-23 11:27:34 -050028static void ctrl_mmr_unlock(void)
29{
30 /* Unlock all PADCFG_MMR1 module registers */
31 mmr_unlock(PADCFG_MMR1_BASE, 1);
32
Hari Nagalla92e46092022-03-09 14:42:30 -060033 /* Unlock all MCU_CTRL_MMR0 module registers */
34 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
35 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
36 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
37 mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
38 mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
39 mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
40
Dave Gerlachb4a8c3b2021-04-23 11:27:34 -050041 /* Unlock all CTRL_MMR0 module registers */
42 mmr_unlock(CTRL_MMR0_BASE, 0);
43 mmr_unlock(CTRL_MMR0_BASE, 1);
44 mmr_unlock(CTRL_MMR0_BASE, 2);
45 mmr_unlock(CTRL_MMR0_BASE, 3);
46 mmr_unlock(CTRL_MMR0_BASE, 5);
47 mmr_unlock(CTRL_MMR0_BASE, 6);
Christian Gmeiner761157d2022-05-12 08:21:01 +020048
49 /* Unlock all MCU_PADCFG_MMR1 module registers */
50 mmr_unlock(MCU_PADCFG_MMR1_BASE, 1);
Dave Gerlachb4a8c3b2021-04-23 11:27:34 -050051}
52
Dave Gerlach6d52c9d2021-04-23 11:27:35 -050053/*
54 * This uninitialized global variable would normal end up in the .bss section,
55 * but the .bss is cleared between writing and reading this variable, so move
56 * it to the .data section.
57 */
58u32 bootindex __section(".data");
Marek BehĂșn236f2ec2021-05-20 13:23:52 +020059static struct rom_extended_boot_data bootdata __section(".data");
Dave Gerlach6d52c9d2021-04-23 11:27:35 -050060
61static void store_boot_info_from_rom(void)
62{
63 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
Bryan Brattlof4c710fa2022-11-22 13:28:11 -060064 memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
Dave Gerlach6d52c9d2021-04-23 11:27:35 -050065 sizeof(struct rom_extended_boot_data));
66}
67
Dave Gerlachf4686c32021-04-23 11:27:37 -050068#if defined(CONFIG_K3_LOAD_SYSFW) && CONFIG_IS_ENABLED(DM_MMC)
69void k3_mmc_stop_clock(void)
70{
71 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
72 struct mmc *mmc = find_mmc_device(0);
73
74 if (!mmc)
75 return;
76
77 mmc->saved_clock = mmc->clock;
78 mmc_set_clock(mmc, 0, true);
79 }
80}
81
82void k3_mmc_restart_clock(void)
83{
84 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
85 struct mmc *mmc = find_mmc_device(0);
86
87 if (!mmc)
88 return;
89
90 mmc_set_clock(mmc, mmc->saved_clock, false);
91 }
92}
93#else
94void k3_mmc_stop_clock(void) {}
95void k3_mmc_restart_clock(void) {}
96#endif
97
Lokesh Vutlab5425a92021-05-06 16:44:52 +053098#ifdef CONFIG_SPL_OF_LIST
99void do_dt_magic(void)
100{
101 int ret, rescan;
102
Andrew Davise25fe5b2023-04-06 11:38:17 -0500103 /* Perform board detection */
104 do_board_detect();
Lokesh Vutlab5425a92021-05-06 16:44:52 +0530105
106 /*
107 * Board detection has been done.
108 * Let us see if another dtb wouldn't be a better match
109 * for our board
110 */
111 if (IS_ENABLED(CONFIG_CPU_V7R)) {
112 ret = fdtdec_resetup(&rescan);
113 if (!ret && rescan) {
114 dm_uninit();
115 dm_init_and_scan(true);
116 }
117 }
118}
119#endif
120
Aswath Govindraju669a03e2021-06-04 22:00:33 +0530121#if CONFIG_IS_ENABLED(USB_STORAGE)
122static int fixup_usb_boot(const void *fdt_blob)
123{
124 int ret = 0;
125
126 switch (spl_boot_device()) {
127 case BOOT_DEVICE_USB:
128 /*
129 * If the boot mode is host, fixup the dr_mode to host
130 * before cdns3 bind takes place
131 */
132 ret = fdt_find_and_setprop((void *)fdt_blob,
133 "/bus@f4000/cdns-usb@f900000/usb@f400000",
134 "dr_mode", "host", 5, 0);
135 if (ret)
136 printf("%s: fdt_find_and_setprop() failed:%d\n",
137 __func__, ret);
138 fallthrough;
139 default:
140 break;
141 }
142
143 return ret;
144}
145
146int fdtdec_board_setup(const void *fdt_blob)
147{
148 /* Can use the pointer from the function parameters */
149 return fixup_usb_boot(fdt_blob);
150}
151#endif
152
Hari Nagalla92e46092022-03-09 14:42:30 -0600153#if defined(CONFIG_ESM_K3)
154static void enable_mcu_esm_reset(void)
155{
156 /* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z to '0' (low active) */
157 u32 stat = readl(CTRLMMR_MCU_RST_CTRL);
158
159 stat &= 0xFFFDFFFF;
160 writel(stat, CTRLMMR_MCU_RST_CTRL);
161}
162#endif
163
Dave Gerlacheb541682021-04-23 11:27:32 -0500164void board_init_f(ulong dummy)
165{
Hari Nagalla92e46092022-03-09 14:42:30 -0600166#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM64_DDRSS) || defined(CONFIG_ESM_K3)
Dave Gerlachd2edabf2021-04-23 11:27:36 -0500167 struct udevice *dev;
168 int ret;
169#endif
170
Dave Gerlacheb541682021-04-23 11:27:32 -0500171#if defined(CONFIG_CPU_V7R)
172 setup_k3_mpu_regions();
173#endif
174
Dave Gerlach6d52c9d2021-04-23 11:27:35 -0500175 /*
176 * Cannot delay this further as there is a chance that
177 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
178 */
179 store_boot_info_from_rom();
180
Dave Gerlachb4a8c3b2021-04-23 11:27:34 -0500181 ctrl_mmr_unlock();
182
Dave Gerlacheb541682021-04-23 11:27:32 -0500183 /* Init DM early */
184 spl_early_init();
185
186 preloader_console_init();
Dave Gerlachd2edabf2021-04-23 11:27:36 -0500187
Lokesh Vutlab5425a92021-05-06 16:44:52 +0530188 do_dt_magic();
189
Dave Gerlachd2edabf2021-04-23 11:27:36 -0500190#if defined(CONFIG_K3_LOAD_SYSFW)
191 /*
192 * Process pinctrl for serial3 a.k.a. MAIN UART1 module and continue
193 * regardless of the result of pinctrl. Do this without probing the
194 * device, but instead by searching the device that would request the
195 * given sequence number if probed. The UART will be used by the system
196 * firmware (SYSFW) image for various purposes and SYSFW depends on us
197 * to initialize its pin settings.
198 */
199 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev);
200 if (!ret)
201 pinctrl_select_state(dev, "default");
202
203 /*
204 * Load, start up, and configure system controller firmware.
205 * This will determine whether or not ROM has already loaded
206 * system firmware and if so, will only perform needed config
207 * and not attempt to load firmware again.
208 */
Dave Gerlachf4686c32021-04-23 11:27:37 -0500209 k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata), k3_mmc_stop_clock,
210 k3_mmc_restart_clock);
Dave Gerlachd2edabf2021-04-23 11:27:36 -0500211#endif
212
213 /* Output System Firmware version info */
214 k3_sysfw_print_ver();
Dave Gerlachd411f092021-05-04 18:00:53 -0500215
Hari Nagalla92e46092022-03-09 14:42:30 -0600216#if defined(CONFIG_ESM_K3)
217 /* Probe/configure ESM0 */
218 ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev);
219 if (ret)
220 printf("esm main init failed: %d\n", ret);
221
222 /* Probe/configure MCUESM */
223 ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev);
224 if (ret)
225 printf("esm mcu init failed: %d\n", ret);
226
227 enable_mcu_esm_reset();
228#endif
229
Dave Gerlachd411f092021-05-04 18:00:53 -0500230#if defined(CONFIG_K3_AM64_DDRSS)
231 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
232 if (ret)
233 panic("DRAM init failed: %d\n", ret);
234#endif
Vignesh Raghavendra93c43a82021-12-24 12:55:32 +0530235 if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) &&
236 spl_boot_device() == BOOT_DEVICE_ETHERNET) {
237 struct udevice *cpswdev;
238
239 if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss), &cpswdev))
240 printf("Failed to probe am65_cpsw_nuss driver\n");
241 }
Dave Gerlacheb541682021-04-23 11:27:32 -0500242}
Keerthy57dba042021-04-23 11:27:33 -0500243
Andre Przywara59073572021-07-12 11:06:49 +0100244u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
Keerthy57dba042021-04-23 11:27:33 -0500245{
246 switch (boot_device) {
247 case BOOT_DEVICE_MMC1:
248 return MMCSD_MODE_EMMCBOOT;
249
250 case BOOT_DEVICE_MMC2:
251 return MMCSD_MODE_FS;
252
253 default:
254 return MMCSD_MODE_RAW;
255 }
256}
257
258static u32 __get_backup_bootmedia(u32 main_devstat)
259{
260 u32 bkup_bootmode =
261 (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
262 MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
263 u32 bkup_bootmode_cfg =
264 (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
265 MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
266
267 switch (bkup_bootmode) {
268 case BACKUP_BOOT_DEVICE_UART:
269 return BOOT_DEVICE_UART;
270
Aswath Govindraju3ae127c2021-06-04 22:00:32 +0530271 case BACKUP_BOOT_DEVICE_DFU:
272 if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
273 return BOOT_DEVICE_USB;
274 return BOOT_DEVICE_DFU;
275
Keerthy57dba042021-04-23 11:27:33 -0500276
277 case BACKUP_BOOT_DEVICE_ETHERNET:
278 return BOOT_DEVICE_ETHERNET;
279
280 case BACKUP_BOOT_DEVICE_MMC:
281 if (bkup_bootmode_cfg)
282 return BOOT_DEVICE_MMC2;
283 return BOOT_DEVICE_MMC1;
284
285 case BACKUP_BOOT_DEVICE_SPI:
286 return BOOT_DEVICE_SPI;
287
288 case BACKUP_BOOT_DEVICE_I2C:
289 return BOOT_DEVICE_I2C;
290 };
291
292 return BOOT_DEVICE_RAM;
293}
294
295static u32 __get_primary_bootmedia(u32 main_devstat)
296{
297 u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
298 MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
299 u32 bootmode_cfg =
300 (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
301 MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
302
303 switch (bootmode) {
304 case BOOT_DEVICE_OSPI:
305 fallthrough;
306 case BOOT_DEVICE_QSPI:
307 fallthrough;
308 case BOOT_DEVICE_XSPI:
309 fallthrough;
310 case BOOT_DEVICE_SPI:
311 return BOOT_DEVICE_SPI;
312
313 case BOOT_DEVICE_ETHERNET_RGMII:
314 fallthrough;
315 case BOOT_DEVICE_ETHERNET_RMII:
316 return BOOT_DEVICE_ETHERNET;
317
318 case BOOT_DEVICE_EMMC:
319 return BOOT_DEVICE_MMC1;
320
321 case BOOT_DEVICE_MMC:
322 if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
323 MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
324 return BOOT_DEVICE_MMC2;
325 return BOOT_DEVICE_MMC1;
326
Aswath Govindraju3ae127c2021-06-04 22:00:32 +0530327 case BOOT_DEVICE_DFU:
328 if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
329 MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
330 return BOOT_DEVICE_USB;
331 return BOOT_DEVICE_DFU;
332
Keerthy57dba042021-04-23 11:27:33 -0500333 case BOOT_DEVICE_NOBOOT:
334 return BOOT_DEVICE_RAM;
335 }
336
337 return bootmode;
338}
339
340u32 spl_boot_device(void)
341{
342 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
343
344 if (bootindex == K3_PRIMARY_BOOTMODE)
345 return __get_primary_bootmedia(devstat);
346 else
347 return __get_backup_bootmedia(devstat);
348}