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Rajeshwari Shindea2d8e0a2012-10-25 19:49:23 +00001/*
2 * Copyright (C) 2012 Samsung Electronics
3 * R. Chadrasekar <rcsekar@samsung.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Rajeshwari Shindea2d8e0a2012-10-25 19:49:23 +00006 */
7
8#ifndef __WM8994_H__
9#define __WM8994_H__
10
11/* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */
12#define WM8994_SYSCLK_MCLK1 1
13#define WM8994_SYSCLK_MCLK2 2
14#define WM8994_SYSCLK_FLL1 3
15#define WM8994_SYSCLK_FLL2 4
16
17/* Avilable audi interface ports in wm8994 codec */
18enum en_audio_interface {
19 WM8994_AIF1 = 1,
20 WM8994_AIF2,
21 WM8994_AIF3
22};
23
24/* OPCLK is also configured with set_dai_sysclk, specify division*10 as rate. */
25#define WM8994_SYSCLK_OPCLK 5
26
27#define WM8994_FLL1 1
28#define WM8994_FLL2 2
29
30#define WM8994_FLL_SRC_MCLK1 1
31#define WM8994_FLL_SRC_MCLK2 2
32#define WM8994_FLL_SRC_LRCLK 3
33#define WM8994_FLL_SRC_BCLK 4
34
35/* maximum available digital interfac in the dac to configure */
36#define WM8994_MAX_AIF 2
37
38#define WM8994_MAX_INPUT_CLK_FREQ 13500000
39#define WM8994_ID 0x8994
40
41enum wm8994_vmid_mode {
42 WM8994_VMID_NORMAL,
43 WM8994_VMID_FORCE,
44};
45
46/* wm 8994 family devices */
47enum wm8994_type {
48 WM8994 = 0,
49 WM8958 = 1,
50 WM1811 = 2,
51};
52
53/*
54 * intialise wm8994 sound codec device for the given configuration
55 *
Rajeshwari Shinde6647c7a2012-12-26 20:03:18 +000056 * @param blob FDT node for codec values
Rajeshwari Shindea2d8e0a2012-10-25 19:49:23 +000057 * @param aif_id enum value of codec interface port in which
58 * soc i2s is connected
59 * @param sampling_rate Sampling rate ranges between from 8khz to 96khz
60 * @param mclk_freq Master clock frequency.
61 * @param bits_per_sample bits per Sample can be 16 or 24
62 * @param channels Number of channnels, maximum 2
63 *
64 * @returns -1 for error and 0 Success.
65 */
Rajeshwari Shinde6647c7a2012-12-26 20:03:18 +000066int wm8994_init(const void *blob, enum en_audio_interface aif_id,
Rajeshwari Shindea2d8e0a2012-10-25 19:49:23 +000067 int sampling_rate, int mclk_freq,
68 int bits_per_sample, unsigned int channels);
69#endif /*__WM8994_H__ */