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wdenk2262cfe2002-11-18 00:14:45 +00001/*
2 * (C) Copyright 2002
Graeme Russ0ea76e92011-02-12 15:11:35 +11003 * Daniel Engstr�m, Omicron Ceti AB <daniel@omicron.se>.
wdenk2262cfe2002-11-18 00:14:45 +00004 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* stuff specific for the sc520,
25 * but idependent of implementation */
26
wdenk2262cfe2002-11-18 00:14:45 +000027#include <common.h>
wdenk2262cfe2002-11-18 00:14:45 +000028#include <asm/io.h>
Graeme Russ0c24c9c2011-02-12 15:11:32 +110029#include <asm/processor-flags.h>
wdenk2262cfe2002-11-18 00:14:45 +000030#include <asm/ic/sc520.h>
31
Wolfgang Denkd87080b2006-03-31 18:32:53 +020032DECLARE_GLOBAL_DATA_PTR;
33
Graeme Russc2cbbaf2011-02-12 15:11:36 +110034sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE;
wdenk2262cfe2002-11-18 00:14:45 +000035
Graeme Russ0ea76e92011-02-12 15:11:35 +110036int cpu_init_f(void)
wdenk2262cfe2002-11-18 00:14:45 +000037{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038 if (CONFIG_SYS_SC520_HIGH_SPEED) {
Graeme Russ8ffb2e82010-10-07 20:03:21 +110039 /* set it to 133 MHz and write back */
40 writeb(0x02, &sc520_mmcr->cpuctl);
wdenk2262cfe2002-11-18 00:14:45 +000041 gd->cpu_clk = 133000000;
wdenk2262cfe2002-11-18 00:14:45 +000042 } else {
Graeme Russ8ffb2e82010-10-07 20:03:21 +110043 /* set it to 100 MHz and write back */
44 writeb(0x01, &sc520_mmcr->cpuctl);
wdenk2262cfe2002-11-18 00:14:45 +000045 gd->cpu_clk = 100000000;
46 }
wdenk8bde7f72003-06-27 21:31:46 +000047
wdenk2262cfe2002-11-18 00:14:45 +000048 /* wait at least one millisecond */
Graeme Russ8ffb2e82010-10-07 20:03:21 +110049 asm("movl $0x2000, %%ecx\n"
Graeme Russcfb3a732009-08-23 12:59:46 +100050 "0: pushl %%ecx\n"
wdenk2262cfe2002-11-18 00:14:45 +000051 "popl %%ecx\n"
Graeme Russcfb3a732009-08-23 12:59:46 +100052 "loop 0b\n": : : "ecx");
wdenk2262cfe2002-11-18 00:14:45 +000053
Graeme Russ0ea76e92011-02-12 15:11:35 +110054 return x86_cpu_init_f();
wdenk2262cfe2002-11-18 00:14:45 +000055}
56
Graeme Russ6002bf02011-02-12 15:12:12 +110057int cpu_init_r(void)
58{
59 /* Disable the PAR used for CAR */
60 writel(0x0000000, &sc520_mmcr->par[2]);
61
62 /* turn on the SDRAM write buffer */
63 writeb(0x11, &sc520_mmcr->dbctl);
64
65 return x86_cpu_init_r();
66}
67
Graeme Russ6d83e3a2009-02-24 21:12:20 +110068#ifdef CONFIG_SYS_SC520_RESET
Graeme Russead056b2008-12-07 10:29:03 +110069void reset_cpu(ulong addr)
70{
71 printf("Resetting using SC520 MMCR\n");
72 /* Write a '1' to the SYS_RST of the RESCFG MMCR */
Graeme Russ64a0a492010-04-24 00:05:37 +100073 writeb(0x01, &sc520_mmcr->rescfg);
Graeme Russead056b2008-12-07 10:29:03 +110074
75 /* NOTREACHED */
76}
77#endif