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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 4ae78e55b051a416942c00266327869b8e5bd4c8 / . / arch / arm / dts / zynqmp-zcu102.dts
blob: d6cee07890c500d0ec32c2cbd902b098a3505a06 [file] [log] [blame]
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]1/*
2 * dts file for Xilinx ZynqMP ZCU102
3 *
4 * (C) Copyright 2015, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
14#include "zynqmp-clk.dtsi"
15
16/ {
17 model = "ZynqMP ZCU102 RevA";
18 compatible = "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
19
20 aliases {
21 ethernet0 = &gem3;
22 gpio0 = &gpio;
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 mmc0 = &sdhci1;
26 rtc0 = &rtc;
27 serial0 = &uart0;
28 serial1 = &uart1;
29 spi0 = &qspi;
30 usb0 = &usb0;
31 };
32
33 chosen {
34 bootargs = "earlycon";
35 stdout-path = "serial0:115200n8";
36 };
37
Michal Simekc926e6f2016-11-11 13:21:04 +0100[diff] [blame]38 memory@0 {
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]39 device_type = "memory";
40 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
41 };
Michal Simek4ae78e52016-04-20 13:12:25 +0200[diff] [blame^]42
43 leds {
44 compatible = "gpio-leds";
45 heartbeat_led {
46 label = "heartbeat";
47 gpios = <&gpio 23 0>;
48 linux,default-trigger = "heartbeat";
49 };
50 };
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]51};
52
53&can1 {
54 status = "okay";
55};
56
57/* fpd_dma clk 667MHz, lpd_dma 500MHz */
58&fpd_dma_chan1 {
59 status = "okay";
60 xlnx,include-sg; /* for testing purpose */
61 xlnx,overfetch; /* for testing purpose */
62 xlnx,ratectrl = <0>; /* for testing purpose */
63 xlnx,src-issue = <31>;
64};
65
66&fpd_dma_chan2 {
67 status = "okay";
68 xlnx,ratectrl = <100>; /* for testing purpose */
69 xlnx,src-issue = <4>; /* for testing purpose */
70};
71
72&fpd_dma_chan3 {
73 status = "okay";
74};
75
76&fpd_dma_chan4 {
77 status = "okay";
78 xlnx,include-sg; /* for testing purpose */
79};
80
81&fpd_dma_chan5 {
82 status = "okay";
83};
84
85&fpd_dma_chan6 {
86 status = "okay";
87 xlnx,include-sg; /* for testing purpose */
88};
89
90&fpd_dma_chan7 {
91 status = "okay";
92};
93
94&fpd_dma_chan8 {
95 status = "okay";
96 xlnx,include-sg; /* for testing purpose */
97};
98
99&gem3 {
100 status = "okay";
101 local-mac-address = [00 0a 35 00 02 90];
102 phy-handle = <&phy0>;
103 phy-mode = "rgmii-id";
104 phy0: phy@21 {
105 reg = <21>;
106 ti,rx-internal-delay = <0x8>;
107 ti,tx-internal-delay = <0xa>;
108 ti,fifo-depth = <0x1>;
109 };
110};
111
112&gpio {
113 status = "okay";
114};
115
116&gpu {
117 status = "okay";
118};
119
120&i2c0 {
121 status = "okay";
122 clock-frequency = <400000>;
123
124 tca6416_u97: gpio@20 {
125 /*
126 * Enable all GTs to out from U-Boot
127 * i2c mw 20 6 0 - setup IO to output
128 * i2c mw 20 2 ef - setup output values on pins 0-7
129 * i2c mw 20 3 ff - setup output values on pins 10-17
130 */
131 compatible = "ti,tca6416";
132 reg = <0x20>;
133 gpio-controller;
134 #gpio-cells = <2>;
135 /*
136 * IRQ not connected
137 * Lines:
138 * 0 - PS_GTR_LAN_SEL0
139 * 1 - PS_GTR_LAN_SEL1
140 * 2 - PS_GTR_LAN_SEL2
141 * 3 - PS_GTR_LAN_SEL3
142 * 4 - PCI_CLK_DIR_SEL
143 * 5 - IIC_MUX_RESET_B
144 * 6 - GEM3_EXP_RESET_B
145 * 7, 10 - 17 - not connected
146 */
147
148 gtr_sel0 {
149 gpio-hog;
150 gpios = <0 0>;
151 output-high; /* PCIE = 0, DP = 1 */
152 line-name = "sel0";
153 };
154 gtr_sel1 {
155 gpio-hog;
156 gpios = <1 0>;
157 output-high; /* PCIE = 0, DP = 1 */
158 line-name = "sel1";
159 };
160 gtr_sel2 {
161 gpio-hog;
162 gpios = <2 0>;
163 output-high; /* PCIE = 0, USB0 = 1 */
164 line-name = "sel2";
165 };
166 gtr_sel3 {
167 gpio-hog;
168 gpios = <3 0>;
169 output-high; /* PCIE = 0, SATA = 1 */
170 line-name = "sel3";
171 };
172 };
173
174 tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
175 compatible = "ti,tca6416";
176 reg = <0x21>;
177 gpio-controller;
178 #gpio-cells = <2>;
179 /*
180 * IRQ not connected
181 * Lines:
182 * 0 - VCCPSPLL_EN
183 * 1 - MGTRAVCC_EN
184 * 2 - MGTRAVTT_EN
185 * 3 - VCCPSDDRPLL_EN
186 * 4 - MIO26_PMU_INPUT_LS
187 * 5 - PL_PMBUS_ALERT
188 * 6 - PS_PMBUS_ALERT
189 * 7 - MAXIM_PMBUS_ALERT
190 * 10 - PL_DDR4_VTERM_EN
191 * 11 - PL_DDR4_VPP_2V5_EN
192 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
193 * 13 - PS_DIMM_SUSPEND_EN
194 * 14 - PS_DDR4_VTERM_EN
195 * 15 - PS_DDR4_VPP_2V5_EN
196 * 16 - 17 - not connected
197 */
198 };
199
200 i2cswitch@75 { /* u60 */
201 compatible = "nxp,pca9544";
202 #address-cells = <1>;
203 #size-cells = <0>;
204 reg = <0x75>;
205 i2c@0 { /* i2c mw 75 0 1 */
206 #address-cells = <1>;
207 #size-cells = <0>;
208 reg = <0>;
209 /* PS_PMBUS */
210 ina226@40 { /* u76 */
211 compatible = "ti,ina226";
212 reg = <0x40>;
213 shunt-resistor = <5000>;
214 };
215 ina226@41 { /* u77 */
216 compatible = "ti,ina226";
217 reg = <0x41>;
218 shunt-resistor = <5000>;
219 };
220 ina226@42 { /* u78 */
221 compatible = "ti,ina226";
222 reg = <0x42>;
223 shunt-resistor = <5000>;
224 };
225 ina226@43 { /* u87 */
226 compatible = "ti,ina226";
227 reg = <0x43>;
228 shunt-resistor = <5000>;
229 };
230 ina226@44 { /* u85 */
231 compatible = "ti,ina226";
232 reg = <0x44>;
233 shunt-resistor = <5000>;
234 };
235 ina226@45 { /* u86 */
236 compatible = "ti,ina226";
237 reg = <0x45>;
238 shunt-resistor = <5000>;
239 };
240 ina226@46 { /* u93 */
241 compatible = "ti,ina226";
242 reg = <0x46>;
243 shunt-resistor = <5000>;
244 };
245 ina226@47 { /* u88 */
246 compatible = "ti,ina226";
247 reg = <0x47>;
248 shunt-resistor = <5000>;
249 };
250 ina226@4a { /* u15 */
251 compatible = "ti,ina226";
252 reg = <0x4a>;
253 shunt-resistor = <5000>;
254 };
255 ina226@4b { /* u92 */
256 compatible = "ti,ina226";
257 reg = <0x4b>;
258 shunt-resistor = <5000>;
259 };
260 };
261 i2c@1 { /* i2c mw 75 0 1 */
262 #address-cells = <1>;
263 #size-cells = <0>;
264 reg = <1>;
265 /* PL_PMBUS */
266 ina226@40 { /* u79 */
267 compatible = "ti,ina226";
268 reg = <0x40>;
269 shunt-resistor = <2000>;
270 };
271 ina226@41 { /* u81 */
272 compatible = "ti,ina226";
273 reg = <0x41>;
274 shunt-resistor = <5000>;
275 };
276 ina226@42 { /* u80 */
277 compatible = "ti,ina226";
278 reg = <0x42>;
279 shunt-resistor = <5000>;
280 };
281 ina226@43 { /* u84 */
282 compatible = "ti,ina226";
283 reg = <0x43>;
284 shunt-resistor = <5000>;
285 };
286 ina226@44 { /* u16 */
287 compatible = "ti,ina226";
288 reg = <0x44>;
289 shunt-resistor = <5000>;
290 };
291 ina226@45 { /* u65 */
292 compatible = "ti,ina226";
293 reg = <0x45>;
294 shunt-resistor = <5000>;
295 };
296 ina226@46 { /* u74 */
297 compatible = "ti,ina226";
298 reg = <0x46>;
299 shunt-resistor = <5000>;
300 };
301 ina226@47 { /* u75 */
302 compatible = "ti,ina226";
303 reg = <0x47>;
304 shunt-resistor = <5000>;
305 };
306 };
307 i2c@2 { /* i2c mw 75 0 1 */
308 #address-cells = <1>;
309 #size-cells = <0>;
310 reg = <2>;
311 /* MAXIM_PMBUS - 00 */
312 max15301@a { /* u46 */
313 compatible = "max15301";
314 reg = <0xa>;
315 };
316 max15303@b { /* u4 */
317 compatible = "max15303";
318 reg = <0xb>;
319 };
320 max15303@10 { /* u13 */
321 compatible = "max15303";
322 reg = <0x10>;
323 };
324 max15301@13 { /* u47 */
325 compatible = "max15301";
326 reg = <0x13>;
327 };
328 max15303@14 { /* u7 */
329 compatible = "max15303";
330 reg = <0x14>;
331 };
332 max15303@15 { /* u6 */
333 compatible = "max15303";
334 reg = <0x15>;
335 };
336 max15303@16 { /* u10 */
337 compatible = "max15303";
338 reg = <0x16>;
339 };
340 max15303@17 { /* u9 */
341 compatible = "max15303";
342 reg = <0x17>;
343 };
344 max15301@18 { /* u63 */
345 compatible = "max15301";
346 reg = <0x18>;
347 };
348 max15303@1a { /* u49 */
349 compatible = "max15303";
350 reg = <0x1a>;
351 };
352 max15303@1d { /* u18 */
353 compatible = "max15303";
354 reg = <0x1d>;
355 };
356 max15303@20 { /* u8 */
357 compatible = "max15303";
358 status = "disabled"; /* unreachable */
359 reg = <0x20>;
360 };
361
362/* drivers/hwmon/pmbus/Kconfig:86: be called max20751.
363drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o
364*/
365 max20751@72 { /* u95 FIXME - not detected */
366 compatible = "max20751";
367 reg = <0x72>;
368 };
369 max20751@73 { /* u96 FIXME - not detected */
370 compatible = "max20751";
371 reg = <0x73>;
372 };
373 };
374 /* Bus 3 is not connected */
375 };
376
377 /* FIXME PL connection - u55 , PMOD - j160 */
378 /* FIXME MSP430F - u41 - not detected */
379};
380
381&i2c1 {
382 status = "okay";
383 clock-frequency = <400000>;
384 /* FIXME PL i2c via PCA9306 - u45 */
385 /* FIXME MSP430 - u41 - not detected */
386 i2cswitch@74 { /* u34 */
387 compatible = "nxp,pca9548";
388 #address-cells = <1>;
389 #size-cells = <0>;
390 reg = <0x74>;
391 i2c@0 { /* i2c mw 74 0 1 */
392 #address-cells = <1>;
393 #size-cells = <0>;
394 reg = <0>;
395 /*
396 * IIC_EEPROM 1kB memory which uses 256B blocks
397 * where every block has different address.
398 * 0 - 256B address 0x54
399 * 256B - 512B address 0x55
400 * 512B - 768B address 0x56
401 * 768B - 1024B address 0x57
402 */
403 eeprom@54 { /* u23 */
404 compatible = "at,24c08";
405 reg = <0x54>;
406 };
407 };
408 i2c@1 { /* i2c mw 74 0 2 */
409 #address-cells = <1>;
410 #size-cells = <0>;
411 reg = <1>;
412 si5341: clock-generator1@36 { /* SI5341 - u69 */
413 compatible = "si5341";
414 reg = <0x36>;
415 };
416
417 };
418 i2c@2 { /* i2c mw 74 0 4 */
419 #address-cells = <1>;
420 #size-cells = <0>;
421 reg = <2>;
422 si570_1: clock-generator2@5d { /* USER SI570 - u42 */
423 #clock-cells = <0>;
424 compatible = "silabs,si570";
425 reg = <0x5d>;
426 temperature-stability = <50>;
427 factory-fout = <300000000>;
428 clock-frequency = <300000000>;
429 };
430 };
431 i2c@3 { /* i2c mw 74 0 8 */
432 #address-cells = <1>;
433 #size-cells = <0>;
434 reg = <3>;
435 si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
436 #clock-cells = <0>;
437 compatible = "silabs,si570";
438 reg = <0x5d>;
439 temperature-stability = <50>; /* copy from zc702 */
440 factory-fout = <156250000>;
441 clock-frequency = <148500000>;
442 };
443 };
444 i2c@4 { /* i2c mw 74 0 10 */
445 #address-cells = <1>;
446 #size-cells = <0>;
447 reg = <4>;
448 si5328: clock-generator4@69 {/* SI5328 - u20 */
449 compatible = "silabs,si5328";
450 reg = <0x69>;
451 };
452 };
453 /* 5 - 7 unconnected */
454 };
455
456 i2cswitch@75 {
457 compatible = "nxp,pca9548"; /* u135 */
458 #address-cells = <1>;
459 #size-cells = <0>;
460 reg = <0x75>;
461
462 i2c@0 {
463 #address-cells = <1>;
464 #size-cells = <0>;
465 reg = <0>;
466 /* HPC0_IIC */
467 };
468 i2c@1 {
469 #address-cells = <1>;
470 #size-cells = <0>;
471 reg = <1>;
472 /* HPC1_IIC */
473 };
474 i2c@2 {
475 #address-cells = <1>;
476 #size-cells = <0>;
477 reg = <2>;
478 /* SYSMON */
479 };
480 i2c@3 { /* i2c mw 75 0 8 */
481 #address-cells = <1>;
482 #size-cells = <0>;
483 reg = <3>;
484 /* DDR4 SODIMM */
485 dev@19 { /* u-boot detection */
486 compatible = "xxx";
487 reg = <0x19>;
488 };
489 dev@30 { /* u-boot detection */
490 compatible = "xxx";
491 reg = <0x30>;
492 };
493 dev@35 { /* u-boot detection */
494 compatible = "xxx";
495 reg = <0x35>;
496 };
497 dev@36 { /* u-boot detection */
498 compatible = "xxx";
499 reg = <0x36>;
500 };
501 dev@51 { /* u-boot detection - maybe SPD */
502 compatible = "xxx";
503 reg = <0x51>;
504 };
505 };
506 i2c@4 {
507 #address-cells = <1>;
508 #size-cells = <0>;
509 reg = <4>;
510 /* SEP 3 */
511 };
512 i2c@5 {
513 #address-cells = <1>;
514 #size-cells = <0>;
515 reg = <5>;
516 /* SEP 2 */
517 };
518 i2c@6 {
519 #address-cells = <1>;
520 #size-cells = <0>;
521 reg = <6>;
522 /* SEP 1 */
523 };
524 i2c@7 {
525 #address-cells = <1>;
526 #size-cells = <0>;
527 reg = <7>;
528 /* SEP 0 */
529 };
530 };
531};
532
533&pcie {
534/* status = "okay"; */
535};
536
537&qspi {
538 status = "okay";
539 is-dual = <1>;
540 flash@0 {
541 compatible = "m25p80"; /* 32MB */
542 #address-cells = <1>;
543 #size-cells = <1>;
544 reg = <0x0>;
545 spi-tx-bus-width = <1>;
546 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
547 spi-max-frequency = <108000000>; /* Based on DC1 spec */
548 partition@qspi-fsbl-uboot { /* for testing purpose */
549 label = "qspi-fsbl-uboot";
550 reg = <0x0 0x100000>;
551 };
552 partition@qspi-linux { /* for testing purpose */
553 label = "qspi-linux";
554 reg = <0x100000 0x500000>;
555 };
556 partition@qspi-device-tree { /* for testing purpose */
557 label = "qspi-device-tree";
558 reg = <0x600000 0x20000>;
559 };
560 partition@qspi-rootfs { /* for testing purpose */
561 label = "qspi-rootfs";
562 reg = <0x620000 0x5E0000>;
563 };
564 };
565};
566
567&rtc {
568 status = "okay";
569};
570
571&sata {
572 status = "okay";
573 /* SATA OOB timing settings */
574 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
575 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
576 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
577 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
578 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
579 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
580 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
581 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
582};
583
584/* SD1 with level shifter */
585&sdhci1 {
586 status = "okay";
587 no-1-8-v; /* for 1.0 silicon */
588};
589
590&uart0 {
591 status = "okay";
592};
593
594&uart1 {
595 status = "okay";
596};
597
598/* ULPI SMSC USB3320 */
599&usb0 {
600 status = "okay";
601};
602
603&dwc3_0 {
604 status = "okay";
605 dr_mode = "host";
606};
607
608&xilinx_drm {
609 status = "okay";
610 clocks = <&si570_1>;
611};
612
613&xlnx_dp {
614 status = "okay";
615};
616
617&xlnx_dp_sub {
618 status = "okay";
619 xlnx,vid-clk-pl;
620};
621
622&xlnx_dp_snd_pcm0 {
623 status = "okay";
624};
625
626&xlnx_dp_snd_pcm1 {
627 status = "okay";
628};
629
630&xlnx_dp_snd_card {
631 status = "okay";
632};
633
634&xlnx_dp_snd_codec0 {
635 status = "okay";
636};
637
638&xlnx_dpdma {
639 status = "okay";
640};