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wdenk6f213472003-08-29 22:00:43 +00001/*
2 * Board specific setup info
3 *
4 * (C) Copyright 2003
5 * Texas Instruments, <www.ti.com>
6 * Kshitij Gupta <Kshitij@ti.com>
7 *
wdenk63e73c92004-02-23 22:22:28 +00008 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
wdenk028ab6b2004-02-23 23:54:43 +00009 *
wdenk6f213472003-08-29 22:00:43 +000010 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <config.h>
30#include <version.h>
31
32#if defined(CONFIG_OMAP1610)
33#include <./configs/omap1510.h>
34#endif
35
36
37_TEXT_BASE:
38 .word TEXT_BASE /* sdram load addr from config.mk */
39
40.globl platformsetup
41platformsetup:
42
43
wdenk80885a92004-02-26 23:46:20 +000044 /*------------------------------------------------------*
45 *mask all IRQs by setting all bits in the INTMR default*
46 *------------------------------------------------------*/
wdenk0c852a22004-02-26 23:01:04 +000047 mov r1, #0xffffffff
48 ldr r0, =REG_IHL1_MIR
49 str r1, [r0]
50 ldr r0, =REG_IHL2_MIR
51 str r1, [r0]
wdenk80885a92004-02-26 23:46:20 +000052
wdenk6f213472003-08-29 22:00:43 +000053 /*------------------------------------------------------*
54 * Set up ARM CLM registers (IDLECT1) *
55 *------------------------------------------------------*/
56 ldr r0, REG_ARM_IDLECT1
57 ldr r1, VAL_ARM_IDLECT1
58 str r1, [r0]
59
60 /*------------------------------------------------------*
61 * Set up ARM CLM registers (IDLECT2) *
62 *------------------------------------------------------*/
63 ldr r0, REG_ARM_IDLECT2
64 ldr r1, VAL_ARM_IDLECT2
65 str r1, [r0]
66
67 /*------------------------------------------------------*
68 * Set up ARM CLM registers (IDLECT3) *
69 *------------------------------------------------------*/
70 ldr r0, REG_ARM_IDLECT3
71 ldr r1, VAL_ARM_IDLECT3
72 str r1, [r0]
73
wdenk3ff02c22004-06-09 15:25:53 +000074#ifdef CONFIG_CS_AUTOBOOT /* do the setup depending on boot mode */
75 ldr r0, CONF_STATUS
76 ldr r1, [r0]
77 tst r1, #0x02
78 beq disable_wd /* booting from RAM, skip setup */
79#endif
wdenk6f213472003-08-29 22:00:43 +000080
81 mov r1, #0x01 /* PER_EN bit */
82 ldr r0, REG_ARM_RSTCT2
83 strh r1, [r0] /* CLKM; Peripheral reset. */
84
85 /* Set CLKM to Sync-Scalable */
86 /* I supposedly need to enable the dsp clock before switching */
87 mov r1, #0x0000
88 ldr r0, REG_ARM_SYSST
89 strh r1, [r0]
90 mov r0, #0x400
911:
92 subs r0, r0, #0x1 /* wait for any bubbles to finish */
93 bne 1b
94 ldr r1, VAL_ARM_CKCTL
95 ldr r0, REG_ARM_CKCTL
96 strh r1, [r0]
97
98 /* a few nops to let settle */
99 nop
100 nop
101 nop
102 nop
103 nop
104 nop
105 nop
106 nop
107 nop
108 nop
109
110 /* setup DPLL 1 */
111 /* Ramp up the clock to 96Mhz */
112 ldr r1, VAL_DPLL1_CTL
113 ldr r0, REG_DPLL1_CTL
114 strh r1, [r0]
115 ands r1, r1, #0x10 /* Check if PLL is enabled. */
116 beq lock_end /* Do not look for lock if BYPASS selected */
1172:
118 ldrh r1, [r0]
119 ands r1, r1, #0x01 /* Check the LOCK bit.*/
120 beq 2b /* loop until bit goes hi. */
121lock_end:
122
123
124 /*------------------------------------------------------*
125 * Turn off the watchdog during init... *
126 *------------------------------------------------------*/
wdenk3ff02c22004-06-09 15:25:53 +0000127disable_wd:
wdenk6f213472003-08-29 22:00:43 +0000128 ldr r0, REG_WATCHDOG
129 ldr r1, WATCHDOG_VAL1
130 str r1, [r0]
131 ldr r1, WATCHDOG_VAL2
132 str r1, [r0]
133 ldr r0, REG_WSPRDOG
134 ldr r1, WSPRDOG_VAL1
135 str r1, [r0]
136 ldr r0, REG_WWPSDOG
137
138watch1Wait:
139 ldr r1, [r0]
140 tst r1, #0x10
141 bne watch1Wait
142
143 ldr r0, REG_WSPRDOG
144 ldr r1, WSPRDOG_VAL2
145 str r1, [r0]
146 ldr r0, REG_WWPSDOG
147watch2Wait:
148 ldr r1, [r0]
149 tst r1, #0x10
150 bne watch2Wait
151
152
wdenk6f213472003-08-29 22:00:43 +0000153 /* Set memory timings corresponding to the new clock speed */
154
155 /* Check execution location to determine current execution location
156 * and branch to appropriate initialization code.
157 */
158 /* Load physical SDRAM base. */
159 mov r0, #0x10000000
160 /* Get current execution location. */
161 mov r1, pc
162 /* Compare. */
163 cmp r1, r0
164 /* Skip over EMIF-fast initialization if running from SDRAM. */
165 bge skip_sdram
166
167 /*
168 * Delay for SDRAM initialization.
169 */
170 mov r3, #0x1800 /* value should be checked */
1713:
172 subs r3, r3, #0x1 /* Decrement count */
173 bne 3b
174
175
176 /*
177 * Set SDRAM control values. Disable refresh before MRS command.
178 */
179
180 /* mobile ddr operation */
181 ldr r0, REG_SDRAM_OPERATION
182 mov r2, #07
183 str r2, [r0]
184
185 /* config register */
186 ldr r0, REG_SDRAM_CONFIG
187 ldr r1, SDRAM_CONFIG_VAL
188 str r1, [r0]
189
190 /* manual command register */
191 ldr r0, REG_SDRAM_MANUAL_CMD
192 /* issue set cke high */
193 mov r1, #CMD_SDRAM_CKE_SET_HIGH
194 str r1, [r0]
195 /* issue nop */
196 mov r1, #CMD_SDRAM_NOP
197 str r1, [r0]
198
199 mov r2, #0x0100
200waitMDDR1:
201 subs r2, r2, #1
202 bne waitMDDR1 /* delay loop */
203
204 /* issue precharge */
205 mov r1, #CMD_SDRAM_PRECHARGE
206 str r1, [r0]
207
208 /* issue autorefresh x 2 */
209 mov r1, #CMD_SDRAM_AUTOREFRESH
210 str r1, [r0]
211 str r1, [r0]
212
213 /* mrs register ddr mobile */
214 ldr r0, REG_SDRAM_MRS
215 mov r1, #0x33
216 str r1, [r0]
217
218 /* emrs1 low-power register */
219 ldr r0, REG_SDRAM_EMRS1
220 /* self refresh on all banks */
221 mov r1, #0
222 str r1, [r0]
223
224 ldr r0, REG_DLL_URD_CONTROL
225 ldr r1, DLL_URD_CONTROL_VAL
226 str r1, [r0]
227
228 ldr r0, REG_DLL_LRD_CONTROL
229 ldr r1, DLL_LRD_CONTROL_VAL
230 str r1, [r0]
231
232 ldr r0, REG_DLL_WRT_CONTROL
233 ldr r1, DLL_WRT_CONTROL_VAL
234 str r1, [r0]
235
236 /* delay loop */
237 mov r2, #0x0100
238waitMDDR2:
239 subs r2, r2, #1
240 bne waitMDDR2
241
242 /*
243 * Delay for SDRAM initialization.
244 */
245 mov r3, #0x1800
2464:
247 subs r3, r3, #1 /* Decrement count. */
248 bne 4b
249 b common_tc
250
251skip_sdram:
252
253 ldr r0, REG_SDRAM_CONFIG
254 ldr r1, SDRAM_CONFIG_VAL
255 str r1, [r0]
256
257common_tc:
258 /* slow interface */
259 ldr r1, VAL_TC_EMIFS_CS0_CONFIG
260 ldr r0, REG_TC_EMIFS_CS0_CONFIG
261 str r1, [r0] /* Chip Select 0 */
262
263 ldr r1, VAL_TC_EMIFS_CS1_CONFIG
264 ldr r0, REG_TC_EMIFS_CS1_CONFIG
265 str r1, [r0] /* Chip Select 1 */
266 ldr r1, VAL_TC_EMIFS_CS3_CONFIG
267 ldr r0, REG_TC_EMIFS_CS3_CONFIG
268 str r1, [r0] /* Chip Select 3 */
wdenk63e73c92004-02-23 22:22:28 +0000269
wdenk028ab6b2004-02-23 23:54:43 +0000270#ifdef CONFIG_H2_OMAP1610
wdenk63e73c92004-02-23 22:22:28 +0000271 /* inserting additional 2 clock cycle hold time for LAN */
272 ldr r0, REG_TC_EMIFS_CS1_ADVANCED
273 ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
274 str r1, [r0]
275#endif
276 /* Start MPU Timer 1 */
277 ldr r0, REG_MPU_LOAD_TIMER
278 ldr r1, VAL_MPU_LOAD_TIMER
279 str r1, [r0]
280
281 ldr r0, REG_MPU_CNTL_TIMER
282 ldr r1, VAL_MPU_CNTL_TIMER
283 str r1, [r0]
284
wdenk6f213472003-08-29 22:00:43 +0000285 /* back to arch calling code */
286 mov pc, lr
287
288 /* the literal pools origin */
289 .ltorg
290
wdenk3ff02c22004-06-09 15:25:53 +0000291#ifdef CONFIG_CS_AUTOBOOT
292CONF_STATUS:
293 .word 0xfffe1130 /* 32 bits */
294#endif
wdenk6f213472003-08-29 22:00:43 +0000295
296REG_TC_EMIFS_CONFIG: /* 32 bits */
297 .word 0xfffecc0c
298REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
299 .word 0xfffecc10
300REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
301 .word 0xfffecc14
302REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
303 .word 0xfffecc18
304REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
305 .word 0xfffecc1c
306
wdenk63e73c92004-02-23 22:22:28 +0000307#ifdef CONFIG_H2_OMAP1610
308REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
309 .word 0xfffecc54
310#endif
311
wdenk6f213472003-08-29 22:00:43 +0000312/* MPU clock/reset/power mode control registers */
313REG_ARM_CKCTL: /* 16 bits */
314 .word 0xfffece00
315
316REG_ARM_IDLECT3: /* 16 bits */
317 .word 0xfffece24
318REG_ARM_IDLECT2: /* 16 bits */
wdenk42d1f032003-10-15 23:53:47 +0000319 .word 0xfffece08
wdenk6f213472003-08-29 22:00:43 +0000320REG_ARM_IDLECT1: /* 16 bits */
321 .word 0xfffece04
322
323REG_ARM_RSTCT2: /* 16 bits */
324 .word 0xfffece14
325REG_ARM_SYSST: /* 16 bits */
326 .word 0xfffece18
327/* DPLL control registers */
328REG_DPLL1_CTL: /* 16 bits */
329 .word 0xfffecf00
330
331/* Watch Dog register */
332/* secure watchdog stop */
333REG_WSPRDOG:
334 .word 0xfffeb048
335/* watchdog write pending */
336REG_WWPSDOG:
wdenk42d1f032003-10-15 23:53:47 +0000337 .word 0xfffeb034
wdenk6f213472003-08-29 22:00:43 +0000338
339WSPRDOG_VAL1:
340 .word 0x0000aaaa
341WSPRDOG_VAL2:
342 .word 0x00005555
343
344/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
345 counter @8192 rows, 10 ns, 8 burst */
346REG_SDRAM_CONFIG:
347 .word 0xfffecc20
348
349/* Operation register */
350REG_SDRAM_OPERATION:
351 .word 0xfffecc80
352
353/* Manual command register */
354REG_SDRAM_MANUAL_CMD:
355 .word 0xfffecc84
356
357/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
358REG_SDRAM_MRS:
359 .word 0xfffecc70
360
361/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
362REG_SDRAM_EMRS1:
363 .word 0xfffecc78
364
365/* WRT DLL register */
366REG_DLL_WRT_CONTROL:
367 .word 0xfffecc68
368DLL_WRT_CONTROL_VAL:
369 .word 0x03f00002
370
371/* URD DLL register */
372REG_DLL_URD_CONTROL:
373 .word 0xfffeccc0
374DLL_URD_CONTROL_VAL:
375 .word 0x00800002
376
377/* LRD DLL register */
378REG_DLL_LRD_CONTROL:
379 .word 0xfffecccc
380
381REG_WATCHDOG:
382 .word 0xfffec808
383
wdenk63e73c92004-02-23 22:22:28 +0000384REG_MPU_LOAD_TIMER:
385 .word 0xfffec600
386REG_MPU_CNTL_TIMER:
387 .word 0xfffec500
388
wdenk6f213472003-08-29 22:00:43 +0000389/* 96 MHz Samsung Mobile DDR */
390SDRAM_CONFIG_VAL:
wdenk42d1f032003-10-15 23:53:47 +0000391 .word 0x001200f4
wdenk6f213472003-08-29 22:00:43 +0000392
393DLL_LRD_CONTROL_VAL:
394 .word 0x00800002
395
396VAL_ARM_CKCTL:
397 .word 0x3000
398VAL_DPLL1_CTL:
399 .word 0x2830
400
wdenk63e73c92004-02-23 22:22:28 +0000401#ifdef CONFIG_INNOVATOROMAP1610
wdenk6f213472003-08-29 22:00:43 +0000402VAL_TC_EMIFS_CS0_CONFIG:
403 .word 0x002130b0
404VAL_TC_EMIFS_CS1_CONFIG:
405 .word 0x00001131
406VAL_TC_EMIFS_CS2_CONFIG:
407 .word 0x000055f0
408VAL_TC_EMIFS_CS3_CONFIG:
409 .word 0x88011131
wdenk63e73c92004-02-23 22:22:28 +0000410#endif
411
412#ifdef CONFIG_H2_OMAP1610
413VAL_TC_EMIFS_CS0_CONFIG:
414 .word 0x00203331
415VAL_TC_EMIFS_CS1_CONFIG:
416 .word 0x8180fff3
417VAL_TC_EMIFS_CS2_CONFIG:
418 .word 0xf800f22a
419VAL_TC_EMIFS_CS3_CONFIG:
420 .word 0x88011131
421VAL_TC_EMIFS_CS1_ADVANCED:
422 .word 0x00000022
423#endif
424
wdenk6f213472003-08-29 22:00:43 +0000425VAL_TC_EMIFF_SDRAM_CONFIG:
426 .word 0x010290fc
427VAL_TC_EMIFF_MRS:
428 .word 0x00000027
429
430VAL_ARM_IDLECT1:
431 .word 0x00000400
432
433VAL_ARM_IDLECT2:
434 .word 0x00000886
435VAL_ARM_IDLECT3:
436 .word 0x00000015
437
438WATCHDOG_VAL1:
439 .word 0x000000f5
440WATCHDOG_VAL2:
441 .word 0x000000a0
442
wdenk63e73c92004-02-23 22:22:28 +0000443VAL_MPU_LOAD_TIMER:
444 .word 0xffffffff
445VAL_MPU_CNTL_TIMER:
446 .word 0xffffffa1
447
wdenk6f213472003-08-29 22:00:43 +0000448/* command values */
449.equ CMD_SDRAM_NOP, 0x00000000
450.equ CMD_SDRAM_PRECHARGE, 0x00000001
451.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
452.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007