blob: a1f526de6ff1c2113002850e257b905ef3434340 [file] [log] [blame]
wdenkdb01a2e2004-04-15 23:14:49 +00001/*
2 * Copyright (c) 2004 Picture Elements, Inc.
3 * Stephen Williams (steve@icarus.com)
4 *
5 * This source code is free software; you can redistribute it
6 * and/or modify it in source code form under the terms of the GNU
7 * General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
19 */
20
21#include <common.h>
22#include <ppc4xx.h>
23#include <asm/processor.h>
24
25# define SDRAM_LEN 0x08000000
26
27/*
28 * this is even after checkboard. It returns the size of the SDRAM
29 * that we have installed. This function is called by board_init_f
30 * in lib_ppc/board.c to initialize the memory and return what I
31 * found.
32 */
Becky Bruce9973e3c2008-06-09 16:03:40 -050033phys_size_t initdram (int board_type)
wdenkdb01a2e2004-04-15 23:14:49 +000034{
35 /* Configure the SDRAMS */
36
37 /* disable memory controller */
38 mtdcr (memcfga, mem_mcopt1);
39 mtdcr (memcfgd, 0x00000000);
40
41 udelay (500);
42
43 /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
44 mtdcr (memcfga, mem_besra);
45 mtdcr (memcfgd, 0xffffffff);
46
47 /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
48 mtdcr (memcfga, mem_besrb);
49 mtdcr (memcfgd, 0xffffffff);
50
51 /* Clear SDRAM0_ECCCFG (disable ECC) */
52 mtdcr (memcfga, mem_ecccf);
53 mtdcr (memcfgd, 0x00000000);
54
55 /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
56 mtdcr (memcfga, mem_eccerr);
57 mtdcr (memcfgd, 0xffffffff);
58
59 /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */
60 mtdcr (memcfga, mem_sdtr1);
61 mtdcr (memcfgd, 0x010a4016);
62
63 /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */
64 mtdcr (memcfga, mem_mb0cf);
65 mtdcr (memcfgd, 0x00084001);
66
67 /* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */
68 mtdcr (memcfga, mem_mb1cf);
69 mtdcr (memcfgd, 0x04084001);
70
71 /* Memory Bank 2 Config == BE=0 */
72 mtdcr (memcfga, mem_mb2cf);
73 mtdcr (memcfgd, 0x00000000);
74
75 /* Memory Bank 3 Config == BE=0 */
76 mtdcr (memcfga, mem_mb3cf);
77 mtdcr (memcfgd, 0x00000000);
78
79 /* refresh timer = 0x400 */
80 mtdcr (memcfga, mem_rtr);
81 mtdcr (memcfgd, 0x04000000);
82
83 /* Power management idle timer set to the default. */
84 mtdcr (memcfga, mem_pmit);
85 mtdcr (memcfgd, 0x07c00000);
86
87 udelay (500);
88
89 /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */
90 mtdcr (memcfga, mem_mcopt1);
91 mtdcr (memcfgd, 0x80e00000);
92
93 return SDRAM_LEN;
94}
95
96/*
97 * The U-Boot core, as part of the initialization to prepare for
98 * loading the monitor into SDRAM, requests of this function that the
99 * memory be tested. Return 0 if the memory tests OK.
100 */
101int testdram (void)
102{
103 unsigned long idx;
104 unsigned val;
105 unsigned errors;
106 volatile unsigned long *sdram;
107
108#ifdef DEBUG
109 printf ("SDRAM Controller Registers --\n");
110
111 mtdcr (memcfga, mem_mcopt1);
112 val = mfdcr (memcfgd);
113 printf (" SDRAM0_CFG : 0x%08x\n", val);
114
115 mtdcr (memcfga, 0x24);
116 val = mfdcr (memcfgd);
117 printf (" SDRAM0_STATUS: 0x%08x\n", val);
118
119 mtdcr (memcfga, mem_mb0cf);
120 val = mfdcr (memcfgd);
121 printf (" SDRAM0_B0CR : 0x%08x\n", val);
122
123 mtdcr (memcfga, mem_mb1cf);
124 val = mfdcr (memcfgd);
125 printf (" SDRAM0_B1CR : 0x%08x\n", val);
126
127 mtdcr (memcfga, mem_sdtr1);
128 val = mfdcr (memcfgd);
129 printf (" SDRAM0_TR : 0x%08x\n", val);
130
131 mtdcr (memcfga, mem_rtr);
132 val = mfdcr (memcfgd);
133 printf (" SDRAM0_RTR : 0x%08x\n", val);
134#endif
135
136 /* Wait for memory to be ready by testing MRSCMPbit
137 bit. Really, there should already have been plenty of time,
138 given it was started long ago. But, best to check. */
139 for (idx = 0; idx < 1000000; idx += 1) {
140 mtdcr (memcfga, 0x24);
141 val = mfdcr (memcfgd);
142 if (val & 0x80000000)
143 break;
144 }
145
146 if (!(val & 0x80000000)) {
147 printf ("SDRAM ERROR: SDRAM0_STATUS never set!\n");
148 return 1;
149 }
150
151 /* Start memory test. */
152 printf ("test: %u MB - ", SDRAM_LEN / 1048576);
153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154 sdram = (unsigned long *) CONFIG_SYS_SDRAM_BASE;
wdenkdb01a2e2004-04-15 23:14:49 +0000155
156 printf ("write - ");
157 for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
158 sdram[idx + 0] = idx;
159 sdram[idx + 1] = ~idx;
160 }
161
162 printf ("read - ");
163 errors = 0;
164 for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
165 if (sdram[idx + 0] != idx)
166 errors += 1;
167 if (sdram[idx + 1] != ~idx)
168 errors += 1;
169 if (errors > 0)
170 break;
171 }
172
173 if (errors > 0) {
174 printf ("NOT OK\n");
175 printf ("FIRST ERROR at %p: 0x%08lx:0x%08lx != 0x%08lx:0x%08lx\n",
176 sdram + idx, sdram[idx + 0], sdram[idx + 1], idx, ~idx);
177 return 1;
178 }
179
180 printf ("ok\n");
181 return 0;
182}