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Bin Meng5dad97e2014-12-17 15:50:48 +08001#
2# Copyright (C) 2014, Simon Glass <sjg@chromium.org>
3# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4#
5# SPDX-License-Identifier: GPL-2.0+
6#
7
8U-Boot on x86
9=============
10
11This document describes the information about U-Boot running on x86 targets,
12including supported boards, build instructions, todo list, etc.
13
14Status
15------
16U-Boot supports running as a coreboot [1] payload on x86. So far only Link
Bin Meng1ae5b782015-05-07 21:34:12 +080017(Chromebook Pixel) and QEMU [2] x86 targets have been tested, but it should
18work with minimal adjustments on other x86 boards since coreboot deals with
19most of the low-level details.
Bin Meng5dad97e2014-12-17 15:50:48 +080020
21U-Boot also supports booting directly from x86 reset vector without coreboot,
Bin Meng1ae5b782015-05-07 21:34:12 +080022aka raw support or bare support. Currently Link, QEMU x86 targets and all
23Intel boards support running U-Boot 'bare metal'.
Bin Meng5dad97e2014-12-17 15:50:48 +080024
Simon Glass3a1a18f2015-01-27 22:13:47 -070025As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
26Linux kernel as part of a FIT image. It also supports a compressed zImage.
Bin Meng5dad97e2014-12-17 15:50:48 +080027
28Build Instructions
29------------------
30Building U-Boot as a coreboot payload is just like building U-Boot for targets
31on other architectures, like below:
32
33$ make coreboot-x86_defconfig
34$ make all
35
Bin Meng1ae5b782015-05-07 21:34:12 +080036Note this default configuration will build a U-Boot payload for the QEMU board.
Bin Meng617b8672015-01-06 22:14:24 +080037To build a coreboot payload against another board, you can change the build
38configuration during the 'make menuconfig' process.
39
40x86 architecture --->
41 ...
Bin Meng1ae5b782015-05-07 21:34:12 +080042 (qemu-x86) Board configuration file
Bin Meng683b09d2015-06-03 09:20:04 +080043 (qemu-x86_i440fx) Board Device Tree Source (dts) file
Bin Meng1ae5b782015-05-07 21:34:12 +080044 (0x01920000) Board specific Cache-As-RAM (CAR) address
Bin Meng617b8672015-01-06 22:14:24 +080045 (0x4000) Board specific Cache-As-RAM (CAR) size
46
47Change the 'Board configuration file' and 'Board Device Tree Source (dts) file'
48to point to a new board. You can also change the Cache-As-RAM (CAR) related
49settings here if the default values do not fit your new board.
50
Simon Glass3a1a18f2015-01-27 22:13:47 -070051Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
Bin Meng5dad97e2014-12-17 15:50:48 +080052little bit tricky, as generally it requires several binary blobs which are not
53shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
54not turned on by default in the U-Boot source tree. Firstly, you need turn it
Simon Glasseea0f112015-01-27 22:13:32 -070055on by enabling the ROM build:
Bin Meng5dad97e2014-12-17 15:50:48 +080056
Simon Glasseea0f112015-01-27 22:13:32 -070057$ export BUILD_ROM=y
58
59This tells the Makefile to build u-boot.rom as a target.
Bin Meng5dad97e2014-12-17 15:50:48 +080060
61Link-specific instructions:
62
63First, you need the following binary blobs:
64
65* descriptor.bin - Intel flash descriptor
66* me.bin - Intel Management Engine
67* mrc.bin - Memory Reference Code, which sets up SDRAM
68* video ROM - sets up the display
69
70You can get these binary blobs by:
71
72$ git clone http://review.coreboot.org/p/blobs.git
73$ cd blobs
74
75Find the following files:
76
77* ./mainboard/google/link/descriptor.bin
78* ./mainboard/google/link/me.bin
Simon Glass8712af92015-04-19 22:05:37 -060079* ./northbridge/intel/sandybridge/systemagent-r6.bin
Bin Meng5dad97e2014-12-17 15:50:48 +080080
81The 3rd one should be renamed to mrc.bin.
Bin Meng786a08e2015-07-06 16:31:33 +080082As for the video ROM, you can get it here [3] and rename it to vga.bin.
Bin Meng5dad97e2014-12-17 15:50:48 +080083Make sure all these binary blobs are put in the board directory.
84
85Now you can build U-Boot and obtain u-boot.rom:
86
87$ make chromebook_link_defconfig
88$ make all
89
90Intel Crown Bay specific instructions:
91
Bin Meng1ae5b782015-05-07 21:34:12 +080092U-Boot support of Intel Crown Bay board [4] relies on a binary blob called
93Firmware Support Package [5] to perform all the necessary initialization steps
Bin Meng5dad97e2014-12-17 15:50:48 +080094as documented in the BIOS Writer Guide, including initialization of the CPU,
95memory controller, chipset and certain bus interfaces.
96
97Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T,
98install it on your host and locate the FSP binary blob. Note this platform
99also requires a Chipset Micro Code (CMC) state machine binary to be present in
100the SPI flash where u-boot.rom resides, and this CMC binary blob can be found
101in this FSP package too.
102
103* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd
104* ./Microcode/C0_22211.BIN
105
106Rename the first one to fsp.bin and second one to cmc.bin and put them in the
107board directory.
108
Bin Meng83d97122015-03-05 11:21:03 +0800109Note the FSP release version 001 has a bug which could cause random endless
110loop during the FspInit call. This bug was published by Intel although Intel
111did not describe any details. We need manually apply the patch to the FSP
112binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP
113binary, change the following five bytes values from orginally E8 42 FF FF FF
114to B8 00 80 0B 00.
115
Bin Meng7aaff9b2015-07-06 16:31:35 +0800116As for the video ROM, you need manually extract it from the Intel provided
117BIOS for Crown Bay here [6], using the AMI MMTool [7]. Check PCI option ROM
118ID 8086:4108, extract and save it as vga.bin in the board directory.
119
Bin Meng617b8672015-01-06 22:14:24 +0800120Now you can build U-Boot and obtain u-boot.rom
Bin Meng5dad97e2014-12-17 15:50:48 +0800121
122$ make crownbay_defconfig
123$ make all
124
Simon Glass3a1a18f2015-01-27 22:13:47 -0700125Intel Minnowboard Max instructions:
126
127This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
128Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
129the time of writing). Put it in the board directory:
130board/intel/minnowmax/fsp.bin
131
132Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
133directory: board/intel/minnowmax/vga.bin
134
Simon Glass68522482015-04-25 11:46:43 -0600135You still need two more binary blobs. The first comes from the original
136firmware image available from:
137
138http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
139
140Unzip it:
141
142 $ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
Simon Glass3a1a18f2015-01-27 22:13:47 -0700143
144Use ifdtool in the U-Boot tools directory to extract the images from that
145file, for example:
146
Simon Glass68522482015-04-25 11:46:43 -0600147 $ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin
148
149This will provide the descriptor file - copy this into the correct place:
150
151 $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
152
153Then do the same with the sample SPI image provided in the FSP (SPI.bin at
154the time of writing) to obtain the last image. Note that this will also
155produce a flash descriptor file, but it does not seem to work, probably
156because it is not designed for the Minnowmax. That is why you need to get
157the flash descriptor from the original firmware as above.
158
Simon Glass3a1a18f2015-01-27 22:13:47 -0700159 $ ./tools/ifdtool -x BayleyBay/SPI.bin
160 $ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin
Simon Glass3a1a18f2015-01-27 22:13:47 -0700161
162Now you can build U-Boot and obtain u-boot.rom
163
164$ make minnowmax_defconfig
165$ make all
166
Simon Glassdf898672015-07-03 18:28:28 -0600167Checksums are as follows (but note that newer versions will invalidate this):
168
169$ md5sum -b board/intel/minnowmax/*.bin
170ffda9a3b94df5b74323afb328d51e6b4 board/intel/minnowmax/descriptor.bin
17169f65b9a580246291d20d08cbef9d7c5 board/intel/minnowmax/fsp.bin
172894a97d371544ec21de9c3e8e1716c4b board/intel/minnowmax/me.bin
173a2588537da387da592a27219d56e9962 board/intel/minnowmax/vga.bin
174
Simon Glass537ccba2015-07-03 18:28:24 -0600175The ROM image is broken up into these parts:
176
177Offset Description Controlling config
178------------------------------------------------------------
179000000 descriptor.bin Hard-coded to 0 in ifdtool
180001000 me.bin Set by the descriptor
181500000 <spare>
182700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE
183790000 vga.bin CONFIG_X86_OPTION_ROM_ADDR
1847c0000 fsp.bin CONFIG_FSP_ADDR
1857f8000 <spare> (depends on size of fsp.bin)
1867fe000 Environment CONFIG_ENV_OFFSET
1877ff800 U-Boot 16-bit boot CONFIG_SYS_X86_START16
188
189Overall ROM image size is controlled by CONFIG_ROM_SIZE.
190
191
Bin Meng67582c02015-02-04 16:26:14 +0800192Intel Galileo instructions:
193
194Only one binary blob is needed for Remote Management Unit (RMU) within Intel
195Quark SoC. Not like FSP, U-Boot does not call into the binary. The binary is
196needed by the Quark SoC itself.
197
198You can get the binary blob from Quark Board Support Package from Intel website:
199
200* ./QuarkSocPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin
201
202Rename the file and put it to the board directory by:
203
204 $ cp RMU.bin board/intel/galileo/rmu.bin
205
206Now you can build U-Boot and obtain u-boot.rom
207
208$ make galileo_defconfig
209$ make all
Simon Glass3a1a18f2015-01-27 22:13:47 -0700210
Bin Meng1ae5b782015-05-07 21:34:12 +0800211QEMU x86 target instructions:
212
213To build u-boot.rom for QEMU x86 targets, just simply run
214
215$ make qemu-x86_defconfig
216$ make all
217
Bin Meng683b09d2015-06-03 09:20:04 +0800218Note this default configuration will build a U-Boot for the QEMU x86 i440FX
219board. To build a U-Boot against QEMU x86 Q35 board, you can change the build
220configuration during the 'make menuconfig' process like below:
221
222Device Tree Control --->
223 ...
224 (qemu-x86_q35) Default Device Tree for DT control
225
Bin Meng617b8672015-01-06 22:14:24 +0800226Test with coreboot
227------------------
228For testing U-Boot as the coreboot payload, there are things that need be paid
229attention to. coreboot supports loading an ELF executable and a 32-bit plain
230binary, as well as other supported payloads. With the default configuration,
231U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the
232generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool
233provided by coreboot) manually as coreboot's 'make menuconfig' does not provide
234this capability yet. The command is as follows:
235
236# in the coreboot root directory
237$ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \
238 -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110015
239
240Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the
241symbol address of _start (in arch/x86/cpu/start.S).
242
243If you want to use ELF as the coreboot payload, change U-Boot configuration to
Simon Glasseea0f112015-01-27 22:13:32 -0700244use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
Bin Meng617b8672015-01-06 22:14:24 +0800245
Simon Glass3a1a18f2015-01-27 22:13:47 -0700246To enable video you must enable these options in coreboot:
247
248 - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
249 - Keep VESA framebuffer
250
251At present it seems that for Minnowboard Max, coreboot does not pass through
252the video information correctly (it always says the resolution is 0x0). This
253works correctly for link though.
254
Bin Meng1ae5b782015-05-07 21:34:12 +0800255Test with QEMU
256--------------
257QEMU is a fancy emulator that can enable us to test U-Boot without access to
Bin Meng9c4f5412015-05-11 07:36:30 +0800258a real x86 board. Please make sure your QEMU version is 2.3.0 or above test
259U-Boot. To launch QEMU with u-boot.rom, call QEMU as follows:
Bin Meng1ae5b782015-05-07 21:34:12 +0800260
261$ qemu-system-i386 -nographic -bios path/to/u-boot.rom
262
263This will instantiate an emulated x86 board with i440FX and PIIX chipset. QEMU
264also supports emulating an x86 board with Q35 and ICH9 based chipset, which is
265also supported by U-Boot. To instantiate such a machine, call QEMU with:
266
267$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -M q35
268
269Note by default QEMU instantiated boards only have 128 MiB system memory. But
270it is enough to have U-Boot boot and function correctly. You can increase the
271system memory by pass '-m' parameter to QEMU if you want more memory:
272
273$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024
274
275This creates a board with 1 GiB system memory. Currently U-Boot for QEMU only
276supports 3 GiB maximum system memory and reserves the last 1 GiB address space
277for PCI device memory-mapped I/O and other stuff, so the maximum value of '-m'
278would be 3072.
Simon Glass3a1a18f2015-01-27 22:13:47 -0700279
Bin Meng9c4f5412015-05-11 07:36:30 +0800280QEMU emulates a graphic card which U-Boot supports. Removing '-nographic' will
281show QEMU's VGA console window. Note this will disable QEMU's serial output.
282If you want to check both consoles, use '-serial stdio'.
283
Bin Meng5dad97e2014-12-17 15:50:48 +0800284CPU Microcode
285-------------
Bin Meng7aaff9b2015-07-06 16:31:35 +0800286Modern CPUs usually require a special bit stream called microcode [8] to be
Bin Meng5dad97e2014-12-17 15:50:48 +0800287loaded on the processor after power up in order to function properly. U-Boot
288has already integrated these as hex dumps in the source tree.
289
Bin Meng1281a1f2015-06-23 12:18:53 +0800290SMP Support
291-----------
292On a multicore system, U-Boot is executed on the bootstrap processor (BSP).
293Additional application processors (AP) can be brought up by U-Boot. In order to
294have an SMP kernel to discover all of the available processors, U-Boot needs to
295prepare configuration tables which contain the multi-CPUs information before
296loading the OS kernel. Currently U-Boot supports generating two types of tables
Bin Meng7aaff9b2015-07-06 16:31:35 +0800297for SMP, called Simple Firmware Interface (SFI) [9] and Multi-Processor (MP)
298[10] tables. The writing of these two tables are controlled by two Kconfig
299options GENERATE_SFI_TABLE and GENERATE_MP_TABLE.
Bin Meng1281a1f2015-06-23 12:18:53 +0800300
Bin Meng5dad97e2014-12-17 15:50:48 +0800301Driver Model
302------------
303x86 has been converted to use driver model for serial and GPIO.
304
305Device Tree
306-----------
307x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to
Bin Meng617b8672015-01-06 22:14:24 +0800308be turned on. Not every device on the board is configured via device tree, but
Bin Meng5dad97e2014-12-17 15:50:48 +0800309more and more devices will be added as time goes by. Check out the directory
310arch/x86/dts/ for these device tree source files.
311
Simon Glasscb3b2e62015-01-01 16:18:15 -0700312Useful Commands
313---------------
Simon Glasscb3b2e62015-01-01 16:18:15 -0700314In keeping with the U-Boot philosophy of providing functions to check and
315adjust internal settings, there are several x86-specific commands that may be
316useful:
317
318hob - Display information about Firmware Support Package (FSP) Hand-off
319 Block. This is only available on platforms which use FSP, mostly
320 Atom.
321iod - Display I/O memory
322iow - Write I/O memory
323mtrr - List and set the Memory Type Range Registers (MTRR). These are used to
324 tell the CPU whether memory is cacheable and if so the cache write
325 mode to use. U-Boot sets up some reasonable values but you can
326 adjust then with this command.
327
Simon Glass00bdd952015-01-27 22:13:46 -0700328Development Flow
329----------------
Simon Glass00bdd952015-01-27 22:13:46 -0700330These notes are for those who want to port U-Boot to a new x86 platform.
331
332Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment.
333The Dediprog em100 can be used on Linux. The em100 tool is available here:
334
335 http://review.coreboot.org/p/em100.git
336
337On Minnowboard Max the following command line can be used:
338
339 sudo em100 -s -p LOW -d u-boot.rom -c W25Q64DW -r
340
341A suitable clip for connecting over the SPI flash chip is here:
342
343 http://www.dediprog.com/pd/programmer-accessories/EM-TC-8
344
345This allows you to override the SPI flash contents for development purposes.
346Typically you can write to the em100 in around 1200ms, considerably faster
347than programming the real flash device each time. The only important
348limitation of the em100 is that it only supports SPI bus speeds up to 20MHz.
349This means that images must be set to boot with that speed. This is an
350Intel-specific feature - e.g. tools/ifttool has an option to set the SPI
351speed in the SPI descriptor region.
352
353If your chip/board uses an Intel Firmware Support Package (FSP) it is fairly
354easy to fit it in. You can follow the Minnowboard Max implementation, for
355example. Hopefully you will just need to create new files similar to those
356in arch/x86/cpu/baytrail which provide Bay Trail support.
357
358If you are not using an FSP you have more freedom and more responsibility.
359The ivybridge support works this way, although it still uses a ROM for
360graphics and still has binary blobs containing Intel code. You should aim to
361support all important peripherals on your platform including video and storage.
362Use the device tree for configuration where possible.
363
364For the microcode you can create a suitable device tree file using the
365microcode tool:
366
367 ./tools/microcode-tool -d microcode.dat create <model>
368
369or if you only have header files and not the full Intel microcode.dat database:
370
371 ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \
372 -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \
373 create all
374
375These are written to arch/x86/dts/microcode/ by default.
376
377Note that it is possible to just add the micrcode for your CPU if you know its
378model. U-Boot prints this information when it starts
379
380 CPU: x86_64, vendor Intel, device 30673h
381
382so here we can use the M0130673322 file.
383
384If you platform can display POST codes on two little 7-segment displays on
385the board, then you can use post_code() calls from C or assembler to monitor
386boot progress. This can be good for debugging.
387
388If not, you can try to get serial working as early as possible. The early
389debug serial port may be useful here. See setup_early_uart() for an example.
390
Bin Meng5dad97e2014-12-17 15:50:48 +0800391TODO List
392---------
Bin Meng5dad97e2014-12-17 15:50:48 +0800393- Audio
394- Chrome OS verified boot
395- SMI and ACPI support, to provide platform info and facilities to Linux
396
397References
398----------
399[1] http://www.coreboot.org
Bin Meng1ae5b782015-05-07 21:34:12 +0800400[2] http://www.qemu.org
401[3] http://www.coreboot.org/~stepan/pci8086,0166.rom
402[4] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
403[5] http://www.intel.com/fsp
Bin Meng7aaff9b2015-07-06 16:31:35 +0800404[6] http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/e6xx-35-b1-cmc22211.html
405[7] http://www.ami.com/products/bios-uefi-tools-and-utilities/bios-uefi-utilities/
406[8] http://en.wikipedia.org/wiki/Microcode
407[9] http://simplefirmware.org
408[10] http://www.intel.com/design/archives/processors/pro/docs/242016.htm