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Lukasz Majewski38517a72011-10-27 10:36:46 +02001/* linux/arch/arm/plat-s3c/include/plat/regs-otg.h
2 *
3 * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
4 *
5 * Registers remapping:
6 * Lukasz Majewski <l.majewski@samsumg.com>
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Lukasz Majewski38517a72011-10-27 10:36:46 +02009 */
10
11#ifndef __ASM_ARCH_REGS_USB_OTG_HS_H
12#define __ASM_ARCH_REGS_USB_OTG_HS_H
13
14/* USB2.0 OTG Controller register */
15struct s3c_usbotg_phy {
16 u32 phypwr;
17 u32 phyclk;
18 u32 rstcon;
19};
20
21/* Device Logical IN Endpoint-Specific Registers */
22struct s3c_dev_in_endp {
23 u32 diepctl;
24 u8 res1[4];
25 u32 diepint;
26 u8 res2[4];
27 u32 dieptsiz;
28 u32 diepdma;
29 u8 res3[4];
30 u32 diepdmab;
31};
32
33/* Device Logical OUT Endpoint-Specific Registers */
34struct s3c_dev_out_endp {
35 u32 doepctl;
36 u8 res1[4];
37 u32 doepint;
38 u8 res2[4];
39 u32 doeptsiz;
40 u32 doepdma;
41 u8 res3[4];
42 u32 doepdmab;
43};
44
45struct ep_fifo {
46 u32 fifo;
47 u8 res[4092];
48};
49
50/* USB2.0 OTG Controller register */
51struct s3c_usbotg_reg {
52 /* Core Global Registers */
53 u32 gotgctl; /* OTG Control & Status */
54 u32 gotgint; /* OTG Interrupt */
55 u32 gahbcfg; /* Core AHB Configuration */
56 u32 gusbcfg; /* Core USB Configuration */
57 u32 grstctl; /* Core Reset */
58 u32 gintsts; /* Core Interrupt */
59 u32 gintmsk; /* Core Interrupt Mask */
60 u32 grxstsr; /* Receive Status Debug Read/Status Read */
61 u32 grxstsp; /* Receive Status Debug Pop/Status Pop */
62 u32 grxfsiz; /* Receive FIFO Size */
63 u32 gnptxfsiz; /* Non-Periodic Transmit FIFO Size */
64 u8 res1[216];
65 u32 dieptxf[15]; /* Device Periodic Transmit FIFO size register */
66 u8 res2[1728];
67 /* Device Configuration */
68 u32 dcfg; /* Device Configuration Register */
69 u32 dctl; /* Device Control */
70 u32 dsts; /* Device Status */
71 u8 res3[4];
72 u32 diepmsk; /* Device IN Endpoint Common Interrupt Mask */
73 u32 doepmsk; /* Device OUT Endpoint Common Interrupt Mask */
74 u32 daint; /* Device All Endpoints Interrupt */
75 u32 daintmsk; /* Device All Endpoints Interrupt Mask */
76 u8 res4[224];
77 struct s3c_dev_in_endp in_endp[16];
78 struct s3c_dev_out_endp out_endp[16];
79 u8 res5[768];
80 struct ep_fifo ep[16];
81};
82
83/*===================================================================== */
84/*definitions related to CSR setting */
85
86/* S3C_UDC_OTG_GOTGCTL */
87#define B_SESSION_VALID (0x1<<19)
88#define A_SESSION_VALID (0x1<<18)
89
90/* S3C_UDC_OTG_GAHBCFG */
91#define PTXFE_HALF (0<<8)
92#define PTXFE_ZERO (1<<8)
93#define NPTXFE_HALF (0<<7)
94#define NPTXFE_ZERO (1<<7)
95#define MODE_SLAVE (0<<5)
96#define MODE_DMA (1<<5)
97#define BURST_SINGLE (0<<1)
98#define BURST_INCR (1<<1)
99#define BURST_INCR4 (3<<1)
100#define BURST_INCR8 (5<<1)
101#define BURST_INCR16 (7<<1)
102#define GBL_INT_UNMASK (1<<0)
103#define GBL_INT_MASK (0<<0)
104
105/* S3C_UDC_OTG_GRSTCTL */
106#define AHB_MASTER_IDLE (1u<<31)
107#define CORE_SOFT_RESET (0x1<<0)
108
109/* S3C_UDC_OTG_GINTSTS/S3C_UDC_OTG_GINTMSK core interrupt register */
110#define INT_RESUME (1u<<31)
111#define INT_DISCONN (0x1<<29)
112#define INT_CONN_ID_STS_CNG (0x1<<28)
113#define INT_OUT_EP (0x1<<19)
114#define INT_IN_EP (0x1<<18)
115#define INT_ENUMDONE (0x1<<13)
116#define INT_RESET (0x1<<12)
117#define INT_SUSPEND (0x1<<11)
118#define INT_EARLY_SUSPEND (0x1<<10)
119#define INT_NP_TX_FIFO_EMPTY (0x1<<5)
120#define INT_RX_FIFO_NOT_EMPTY (0x1<<4)
121#define INT_SOF (0x1<<3)
122#define INT_DEV_MODE (0x0<<0)
123#define INT_HOST_MODE (0x1<<1)
124#define INT_GOUTNakEff (0x01<<7)
125#define INT_GINNakEff (0x01<<6)
126
127#define FULL_SPEED_CONTROL_PKT_SIZE 8
128#define FULL_SPEED_BULK_PKT_SIZE 64
129
130#define HIGH_SPEED_CONTROL_PKT_SIZE 64
131#define HIGH_SPEED_BULK_PKT_SIZE 512
132
133#define RX_FIFO_SIZE (1024*4)
134#define NPTX_FIFO_SIZE (1024*4)
135#define PTX_FIFO_SIZE (1536*1)
136
137#define DEPCTL_TXFNUM_0 (0x0<<22)
138#define DEPCTL_TXFNUM_1 (0x1<<22)
139#define DEPCTL_TXFNUM_2 (0x2<<22)
140#define DEPCTL_TXFNUM_3 (0x3<<22)
141#define DEPCTL_TXFNUM_4 (0x4<<22)
142
143/* Enumeration speed */
144#define USB_HIGH_30_60MHZ (0x0<<1)
145#define USB_FULL_30_60MHZ (0x1<<1)
146#define USB_LOW_6MHZ (0x2<<1)
147#define USB_FULL_48MHZ (0x3<<1)
148
149/* S3C_UDC_OTG_GRXSTSP STATUS */
150#define OUT_PKT_RECEIVED (0x2<<17)
151#define OUT_TRANSFER_COMPLELTED (0x3<<17)
152#define SETUP_TRANSACTION_COMPLETED (0x4<<17)
153#define SETUP_PKT_RECEIVED (0x6<<17)
154#define GLOBAL_OUT_NAK (0x1<<17)
155
156/* S3C_UDC_OTG_DCTL device control register */
157#define NORMAL_OPERATION (0x1<<0)
158#define SOFT_DISCONNECT (0x1<<1)
159
160/* S3C_UDC_OTG_DAINT device all endpoint interrupt register */
161#define DAINT_OUT_BIT (16)
162#define DAINT_MASK (0xFFFF)
163
164/* S3C_UDC_OTG_DIEPCTL0/DOEPCTL0 device
165 control IN/OUT endpoint 0 control register */
166#define DEPCTL_EPENA (0x1<<31)
167#define DEPCTL_EPDIS (0x1<<30)
168#define DEPCTL_SETD1PID (0x1<<29)
169#define DEPCTL_SETD0PID (0x1<<28)
170#define DEPCTL_SNAK (0x1<<27)
171#define DEPCTL_CNAK (0x1<<26)
172#define DEPCTL_STALL (0x1<<21)
173#define DEPCTL_TYPE_BIT (18)
174#define DEPCTL_TYPE_MASK (0x3<<18)
175#define DEPCTL_CTRL_TYPE (0x0<<18)
176#define DEPCTL_ISO_TYPE (0x1<<18)
177#define DEPCTL_BULK_TYPE (0x2<<18)
178#define DEPCTL_INTR_TYPE (0x3<<18)
179#define DEPCTL_USBACTEP (0x1<<15)
180#define DEPCTL_NEXT_EP_BIT (11)
181#define DEPCTL_MPS_BIT (0)
182#define DEPCTL_MPS_MASK (0x7FF)
183
184#define DEPCTL0_MPS_64 (0x0<<0)
185#define DEPCTL0_MPS_32 (0x1<<0)
186#define DEPCTL0_MPS_16 (0x2<<0)
187#define DEPCTL0_MPS_8 (0x3<<0)
188#define DEPCTL_MPS_BULK_512 (512<<0)
189#define DEPCTL_MPS_INT_MPS_16 (16<<0)
190
191#define DIEPCTL0_NEXT_EP_BIT (11)
192
193
194/* S3C_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint
195 common interrupt mask register */
196/* S3C_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */
197#define BACK2BACK_SETUP_RECEIVED (0x1<<6)
198#define INTKNEPMIS (0x1<<5)
199#define INTKN_TXFEMP (0x1<<4)
200#define NON_ISO_IN_EP_TIMEOUT (0x1<<3)
201#define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1<<3)
202#define AHB_ERROR (0x1<<2)
203#define EPDISBLD (0x1<<1)
204#define TRANSFER_DONE (0x1<<0)
205
206#define USB_PHY_CTRL_EN0 (0x1 << 0)
207
208/* OPHYPWR */
209#define PHY_0_SLEEP (0x1 << 5)
210#define OTG_DISABLE_0 (0x1 << 4)
211#define ANALOG_PWRDOWN (0x1 << 3)
212#define FORCE_SUSPEND_0 (0x1 << 0)
213
214/* URSTCON */
215#define HOST_SW_RST (0x1 << 4)
216#define PHY_SW_RST1 (0x1 << 3)
217#define PHYLNK_SW_RST (0x1 << 2)
218#define LINK_SW_RST (0x1 << 1)
219#define PHY_SW_RST0 (0x1 << 0)
220
221/* OPHYCLK */
222#define COMMON_ON_N1 (0x1 << 7)
223#define COMMON_ON_N0 (0x1 << 4)
224#define ID_PULLUP0 (0x1 << 2)
225#define CLK_SEL_24MHZ (0x3 << 0)
226#define CLK_SEL_12MHZ (0x2 << 0)
227#define CLK_SEL_48MHZ (0x0 << 0)
228
Piotr Wilczek4498cf22013-11-21 15:46:44 +0100229#define EXYNOS4X12_ID_PULLUP0 (0x01 << 3)
230#define EXYNOS4X12_COMMON_ON_N0 (0x01 << 4)
231#define EXYNOS4X12_CLK_SEL_12MHZ (0x02 << 0)
232#define EXYNOS4X12_CLK_SEL_24MHZ (0x05 << 0)
233
Lukasz Majewski38517a72011-10-27 10:36:46 +0200234/* Device Configuration Register DCFG */
235#define DEV_SPEED_HIGH_SPEED_20 (0x0 << 0)
236#define DEV_SPEED_FULL_SPEED_20 (0x1 << 0)
237#define DEV_SPEED_LOW_SPEED_11 (0x2 << 0)
238#define DEV_SPEED_FULL_SPEED_11 (0x3 << 0)
239#define EP_MISS_CNT(x) (x << 18)
240#define DEVICE_ADDRESS(x) (x << 4)
241
242/* Core Reset Register (GRSTCTL) */
243#define TX_FIFO_FLUSH (0x1 << 5)
244#define RX_FIFO_FLUSH (0x1 << 4)
245#define TX_FIFO_NUMBER(x) (x << 6)
246#define TX_FIFO_FLUSH_ALL TX_FIFO_NUMBER(0x10)
247
248/* Masks definitions */
249#define GINTMSK_INIT (INT_OUT_EP | INT_IN_EP | INT_RESUME | INT_ENUMDONE\
250 | INT_RESET | INT_SUSPEND)
251#define DOEPMSK_INIT (CTRL_OUT_EP_SETUP_PHASE_DONE | AHB_ERROR|TRANSFER_DONE)
252#define DIEPMSK_INIT (NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE)
253#define GAHBCFG_INIT (PTXFE_HALF | NPTXFE_HALF | MODE_DMA | BURST_INCR4\
254 | GBL_INT_UNMASK)
255
256/* Device Endpoint X Transfer Size Register (DIEPTSIZX) */
257#define DIEPT_SIZ_PKT_CNT(x) (x << 19)
258#define DIEPT_SIZ_XFER_SIZE(x) (x << 0)
259
260/* Device OUT Endpoint X Transfer Size Register (DOEPTSIZX) */
261#define DOEPT_SIZ_PKT_CNT(x) (x << 19)
262#define DOEPT_SIZ_XFER_SIZE(x) (x << 0)
263#define DOEPT_SIZ_XFER_SIZE_MAX_EP0 (0x7F << 0)
264#define DOEPT_SIZ_XFER_SIZE_MAX_EP (0x7FFF << 0)
265
266/* Device Endpoint-N Control Register (DIEPCTLn/DOEPCTLn) */
267#define DIEPCTL_TX_FIFO_NUM(x) (x << 22)
268#define DIEPCTL_TX_FIFO_NUM_MASK (~DIEPCTL_TX_FIFO_NUM(0xF))
269
270/* Device ALL Endpoints Interrupt Register (DAINT) */
271#define DAINT_IN_EP_INT(x) (x << 0)
272#define DAINT_OUT_EP_INT(x) (x << 16)
273#endif